Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.81 99.07 97.83 100.00 92.31 99.33 98.84 83.26


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
46.58 46.58 63.71 63.71 48.95 48.95 85.96 85.96 0.00 0.00 67.99 67.99 49.61 49.61 9.85 9.85 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2786818663
74.42 27.84 88.69 24.99 80.78 31.83 91.89 5.94 71.15 71.15 90.76 22.77 84.59 34.97 13.10 3.25 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1110028096
79.77 5.34 95.33 6.64 88.93 8.14 94.18 2.28 71.79 0.64 96.23 5.47 89.11 4.53 22.79 9.69 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3813791682
82.18 2.41 96.34 1.01 90.19 1.26 95.21 1.03 77.56 5.77 96.97 0.74 91.33 2.22 27.66 4.87 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2603203008
84.22 2.04 97.29 0.95 90.92 0.73 95.21 0.00 88.46 10.90 97.78 0.81 92.20 0.87 27.66 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.252292424
86.22 2.01 97.63 0.34 91.61 0.68 96.12 0.91 88.46 0.00 97.78 0.00 93.83 1.64 38.13 10.47 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.623605765
87.19 0.97 97.65 0.02 92.09 0.48 96.80 0.68 88.46 0.00 97.82 0.04 93.83 0.00 43.67 5.54 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.811396257
88.10 0.91 97.80 0.15 92.44 0.35 96.80 0.00 88.46 0.00 97.82 0.00 93.93 0.10 49.44 5.77 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3053202456
88.94 0.84 97.80 0.00 92.44 0.00 96.80 0.00 88.46 0.00 97.82 0.00 93.93 0.00 55.32 5.88 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.308724556
89.58 0.65 97.85 0.06 92.44 0.00 96.80 0.00 88.46 0.00 97.86 0.04 93.93 0.00 59.74 4.42 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.517956087
90.15 0.57 97.93 0.07 93.17 0.73 97.72 0.91 88.46 0.00 98.04 0.18 95.28 1.35 60.47 0.73 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1003023454
90.59 0.44 97.98 0.06 93.45 0.28 98.17 0.46 89.10 0.64 98.15 0.11 95.76 0.48 61.53 1.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2742431725
90.99 0.39 98.12 0.13 93.73 0.28 98.17 0.00 89.10 0.00 98.23 0.07 95.86 0.10 63.72 2.18 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1767029174
91.33 0.34 98.23 0.11 94.31 0.58 98.17 0.00 89.74 0.64 98.41 0.18 96.72 0.87 63.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2877202892
91.67 0.34 98.28 0.06 94.99 0.68 98.17 0.00 89.74 0.00 98.48 0.07 97.40 0.67 64.61 0.90 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4044453341
91.98 0.31 98.28 0.00 94.99 0.00 98.17 0.00 89.74 0.00 98.48 0.00 97.40 0.00 66.80 2.18 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.4152212342
92.27 0.29 98.28 0.00 95.04 0.05 99.77 1.60 89.74 0.00 98.48 0.00 97.50 0.10 67.08 0.28 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1310407163
92.54 0.27 98.28 0.00 95.04 0.00 99.77 0.00 89.74 0.00 98.48 0.00 97.50 0.00 68.98 1.90 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2679177954
92.79 0.25 98.40 0.11 95.15 0.10 99.77 0.00 89.74 0.00 98.48 0.00 97.50 0.00 70.49 1.51 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3119128973
93.02 0.23 98.41 0.02 95.25 0.10 99.77 0.00 89.74 0.00 98.52 0.04 97.50 0.00 71.95 1.46 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3465953286
93.21 0.19 98.47 0.06 95.68 0.43 99.77 0.00 89.74 0.00 98.63 0.11 98.17 0.67 72.00 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2725914734
93.39 0.18 98.49 0.02 95.68 0.00 99.77 0.00 89.74 0.00 98.63 0.00 98.17 0.00 73.24 1.23 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4124322654
93.56 0.17 98.49 0.00 96.79 1.11 99.77 0.00 89.74 0.00 98.63 0.00 98.17 0.00 73.35 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2059132434
93.73 0.17 98.53 0.04 97.17 0.38 99.77 0.00 90.38 0.64 98.67 0.04 98.27 0.10 73.35 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1910095480
93.89 0.15 98.53 0.00 97.17 0.00 99.77 0.00 90.38 0.00 98.67 0.00 98.27 0.00 74.41 1.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.716391019
94.03 0.14 98.58 0.06 97.24 0.08 99.77 0.00 91.03 0.64 98.74 0.07 98.36 0.10 74.47 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.637818074
94.16 0.14 98.58 0.00 97.24 0.00 99.77 0.00 91.03 0.00 98.74 0.00 98.36 0.00 75.42 0.95 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.1293539049
94.30 0.14 98.58 0.00 97.24 0.00 99.77 0.00 91.03 0.00 98.74 0.00 98.36 0.00 76.37 0.95 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.1826127800
94.43 0.13 98.62 0.04 97.27 0.03 99.77 0.00 91.67 0.64 98.78 0.04 98.46 0.10 76.43 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3997853273
94.55 0.12 98.62 0.00 97.27 0.00 99.77 0.00 91.67 0.00 98.78 0.00 98.46 0.00 77.27 0.84 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.231196299
94.67 0.12 98.66 0.04 97.29 0.03 99.77 0.00 92.31 0.64 98.82 0.04 98.55 0.10 77.27 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.803987032
94.77 0.10 98.66 0.00 97.29 0.00 99.77 0.00 92.31 0.00 98.82 0.00 98.55 0.00 78.00 0.73 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.279388407
94.86 0.09 98.69 0.04 97.29 0.00 99.77 0.00 92.31 0.00 98.82 0.00 98.55 0.00 78.61 0.62 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3074178618
94.94 0.07 98.69 0.00 97.29 0.00 99.77 0.00 92.31 0.00 98.82 0.00 98.55 0.00 79.12 0.50 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2881006862
95.01 0.07 98.79 0.09 97.40 0.10 100.00 0.23 92.31 0.00 98.89 0.07 98.55 0.00 79.12 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3158188485
95.07 0.06 98.82 0.04 97.40 0.00 100.00 0.00 92.31 0.00 98.89 0.00 98.55 0.00 79.51 0.39 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2687250022
95.13 0.06 98.82 0.00 97.42 0.03 100.00 0.00 92.31 0.00 98.89 0.00 98.65 0.10 79.79 0.28 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.252441735
95.18 0.05 98.90 0.07 97.47 0.05 100.00 0.00 92.31 0.00 99.04 0.15 98.75 0.10 79.79 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1128955344
95.23 0.05 98.94 0.04 97.62 0.15 100.00 0.00 92.31 0.00 99.11 0.07 98.84 0.10 79.79 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1330983906
95.28 0.05 98.94 0.00 97.62 0.00 100.00 0.00 92.31 0.00 99.11 0.00 98.84 0.00 80.12 0.34 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.413989170
95.32 0.04 98.94 0.00 97.62 0.00 100.00 0.00 92.31 0.00 99.11 0.00 98.84 0.00 80.40 0.28 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1566733690
95.35 0.04 99.01 0.07 97.65 0.03 100.00 0.00 92.31 0.00 99.26 0.15 98.84 0.00 80.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1870998956
95.39 0.03 99.01 0.00 97.65 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 80.63 0.22 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3821763724
95.42 0.03 99.01 0.00 97.65 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 80.85 0.22 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1643687651
95.45 0.03 99.01 0.00 97.67 0.03 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.02 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.937670876
95.47 0.02 99.01 0.00 97.67 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.19 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.191010611
95.49 0.02 99.01 0.00 97.67 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.35 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3469765855
95.52 0.02 99.01 0.00 97.67 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.52 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.1925148252
95.54 0.02 99.01 0.00 97.67 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.69 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2110482641
95.57 0.02 99.01 0.00 97.67 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.86 0.17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.193390536
95.58 0.02 99.01 0.00 97.70 0.03 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 81.97 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.24976456
95.60 0.02 99.01 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.08 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1269491288
95.62 0.02 99.01 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.19 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1664974873
95.63 0.02 99.01 0.00 97.70 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.31 0.11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1257860278
95.65 0.01 99.03 0.02 97.72 0.03 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.36 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1881438890
95.66 0.01 99.03 0.00 97.80 0.08 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.36 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1814464724
95.67 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.42 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2467012302
95.67 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.47 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.1627925891
95.68 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.53 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.4020062702
95.69 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.59 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1203296119
95.70 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.64 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.49454487
95.71 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.70 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3484719322
95.71 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.75 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3845215783
95.72 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.81 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.937595169
95.73 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.87 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.922576376
95.74 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.92 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1525678053
95.75 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 82.98 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1962589623
95.75 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 83.03 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3253757067
95.76 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 83.09 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.308197936
95.77 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 83.15 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2936246180
95.78 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 83.20 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2753646997
95.79 0.01 99.03 0.00 97.80 0.00 100.00 0.00 92.31 0.00 99.26 0.00 98.84 0.00 83.26 0.06 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.687350353
95.79 0.01 99.05 0.02 97.80 0.00 100.00 0.00 92.31 0.00 99.30 0.04 98.84 0.00 83.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.876297588
95.80 0.01 99.07 0.02 97.80 0.00 100.00 0.00 92.31 0.00 99.33 0.04 98.84 0.00 83.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2644216617
95.81 0.01 99.07 0.00 97.83 0.03 100.00 0.00 92.31 0.00 99.33 0.00 98.84 0.00 83.26 0.00 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2118374616

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.1772544586
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2450307977
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2686690420
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2495049587
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2556257600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3223311735
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.785125044
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1058899243
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.587836298
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1957865821
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1519653038
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1018806942
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.497335517
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2651712385
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1641970998
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2652893382
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2486346648
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1854094003
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2301031673
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.563413452
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1539841812
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.368186943
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.253968882
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3595953665
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.640185295
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2838762695
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.4206674875
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2883006729
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.835886821
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3903535917
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.237177844
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3708922068
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2968093002
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3612593144
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3985912018
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.49429630
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2421309301
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2254612184
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2428826554
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.794100011
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3094133710
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1463557103
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.947414527
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2972103941
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2730120037
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2858672830
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2691213659
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2369625196
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.4282459190
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3352593555
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2061041041
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2727884892
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3769215761
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3379339077
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1996380489
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2003379271
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.246060550
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3030600992
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3579479660
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2756222122
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1695023140
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2870686504
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3110459420
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2421393584
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2615220022
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2570425574
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3292833127
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.867131096
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1477261547
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2009785298
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1274374729
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1959834477
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.56614117
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4104962217
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3165667411
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1202193323
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.377101775
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1559246313
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2367459396
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2310132626
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2537059134
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.3146820241
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3483931084
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3852282427
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1337211694
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4219846877
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1174925505
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3155411806
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3030965060
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3554125686
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1604432362
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3199432124
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3864761025
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.4133985793
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2231670378
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.808500449
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1450414108
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.3253008724
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.945447604
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.639496953
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.1647235153
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2713438898
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1020732249
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3337156077
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.3470330817
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.89734263
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1579543440
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1077681751
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2922526729
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.59012312
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1889634065
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.4204318549
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862303462
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.506386724
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.985231274
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.1178874921
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.210439908
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3665576247
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2186967542
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.2607998783
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3320119701
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4010851641
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.2893607014
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.244343979
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2367076355
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1612885495
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2189691870
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2394743812
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1531253507
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1071104438
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.2877816204
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2007109485
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3505307147
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2164894530
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4021817991
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.4143539030
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1854748248
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1752284349
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.199389204
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3499070461
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1092362333
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1000213880
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2014949145
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2379589924
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2278478482
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.4012447555
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3920863504
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.285845786
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.282435980
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.925520495
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.4187122384
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2602533568
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2974419621
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.39039097
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3641514726
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.301997273
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.1691141953
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3139603298
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4157163160
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1169873179
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2489974867
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2451645094
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4247524903
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.312989667
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2381385183
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4226894673
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2355617661
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3523536135
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3569012289
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1061701128
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.471796798
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2511416595
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4055146716
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3612089799
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.602925808
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3451980052
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1418327075
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4233079836
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.709313606
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1009360112
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.41455712
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.2988331099
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2833003555
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3129007705
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2906838329
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4020815531
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.119460728
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3898765951
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1851484528
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3676148914
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.777795024
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2462415020
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2036968168
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.92183814
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2245917501
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1544105030
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3002955011
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4241750903
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1339479745
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2189938701
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3579331670
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3480269921
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3675843473
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3321574694
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2806597710
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1704364522
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2631797262
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2215864513
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2436488679
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.3126064741
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.786885445
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2680804577
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2869304918
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2432518159
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.538611484
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4201638844
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.2806267740
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.829748819
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2554622516
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3971601279
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1958226069
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3565170346
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1085922344
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1090013124
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3959091704
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1014359833
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2139073616
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.249293978
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1890935942
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.44274389
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.14581188
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.657875904
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1191893410
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3000813928
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.1847047466
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2710007748
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1928437741
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.897003434
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.404255518
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1056934578
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.833421565
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3132732852
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.225800656
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1926353490
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3056574877
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3765627068
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2425520990
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.1927827749
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1325522029
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2156033769
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.1892355231
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1534729203
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.4102911310
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1164471676
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1386954670
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3589572235
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3761552439
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1408790370
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2418331110
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.2283653766
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.854422258
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2373510072
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3957753256
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1662400496
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.3343957744
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1964109142
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.4127134048
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.4202084545
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.663943539
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.105272800
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.547902647
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3499857056
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.241775590
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.4239924925
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2504952346
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1524583541
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.728069419
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3825397800
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.4258582467
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1964687804
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1244290960
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1573883918
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3813604600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.4102864670
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1198090196
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.868666264
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3366744426
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3632183663
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2673391319
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.265007583
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3381770496
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2517257490
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.725435694
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2817238908
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.544842534
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2802635516
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.4048349130
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3787180042
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.2883992700
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3940026059
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.43974344
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1902444404
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.302489732
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1407639741
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1386169016
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2082248655
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2209769274
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3544797356
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3339148363
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3681005931
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.548899728
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2817482692
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.2792338179
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4099812748
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.208707258
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2932952198
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4285328068
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.3313681651
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1406715928
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.4075573776
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1122492215
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.70568170
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.1673663384
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.141848115
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.2454587053
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1571214400
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.1808303039
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2663908286
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2119360112
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3748991566
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.1077736748
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.2891146733
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.575954859
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1791291675
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3540132965
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.561326225
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1485091637
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2599565136
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1917407871
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1102219817
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2167441337
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1862721130
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1421191743
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3393270608
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3628876914
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3294383609
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2326223268
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.847006300
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.436883067
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2802184527
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3563238343
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2245208612
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2300336534
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3619402206
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.27124716
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.342951041
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1423755602
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.62990159
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.4229936436
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1274730385
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.522696816
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.305427545
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.566377548
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.614386938
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2622246297
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.3046639222
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3572960784
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1390177997
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1642585305
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.683405359
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3556108864
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3212739468
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1315133490
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.1252236773
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1073566197
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1106279117
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2256779405
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1008945153
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2673781878
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.4107032865
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1853238780
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.611310890
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3960994621
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1616765597
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.432607939
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2645949719
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3220340615
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2475833521
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1980746453
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.3992480799
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.96378315
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2392768168
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3636179049
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2104919300
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3671606862
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3128794909
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2008236792
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2793577244
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3281010859
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4154458937
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.2975083763
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3341297577
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.291552054
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.2774952666
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3785034847
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1294108817
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2244068124
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2883020227
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.678508560
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3712708386
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2777999879
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.688436751
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.658780288
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.765465957
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3927805808
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.941966073
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2274585653
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3052994540
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.400855918
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2184702798
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.250021870
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.523428496
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2274674606
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2660106414
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2465891566
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2488689711
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3477562580
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3710610505
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.3958564144
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2364182996
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2286664338
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.3241050891
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3876639968
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.3823829165
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.821282800
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.918831389
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.3658764129
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.450007320
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3530853521
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1503693501
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3260418529
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1820988262
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.1951108866
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3311026847
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3663325521
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.970558994
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1725549330
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1033399229
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.928753084
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.873029256
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4265995772
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2870902177
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.993375983
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.584827729
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1654407794
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.253277506
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2747374425
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1748709473
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3614223186
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.580844599
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.454319866
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2208449148
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.2380004898
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3296357845
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.514341323
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1323575302
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.710145392
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.3689134466
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3427424113
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.3418319796
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2476164549
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3827083808
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3135726136
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.801328351
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.919415914
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3968788679
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1243031268
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1467192795
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.935945600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.745538420
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2782128650
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1793554892
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2497925274
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1099922595
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2760443998
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.546812295
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4017740074
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.3910071145
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1871888412
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2890186098
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1373276469
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.3155219819
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.628806278
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.193073035
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.73239297
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2519762039
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3594129181
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.617237994
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3704772392
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.3702282672
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1717696338
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2666512079
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3843096321
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.564818078
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.608651968
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1450533813
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.105383700
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1738252977
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3469861920
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4063124139
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.807309014
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2315576886
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.1434794747
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2263399291
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.4012995774
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2756075941
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1866928021
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.121718904
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2720042147
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.4145735213
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2758489166
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.883236482
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1998471592
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.563583824
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.3160491010
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2110708600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2285319640
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.1722900479
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.4019864517
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2708154115
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.225554697
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1249135337
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2833551777
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2461833348
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3789842909
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3853278047
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3476452893
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4009652468
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3601871610
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3815372128
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1609562055
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3884523751
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2702431244
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.345460158
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.4013384767
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2919299705
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2527305865
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2508813692
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2897609692
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2687525891
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.3154637485
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1532561715
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3917286747
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4030107858
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.3648491197
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.4070390794
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.1213260559
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.1910918381
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1840024984
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.573114343
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2557294505
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1040065115
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3053962600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3105832121
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.1345817023
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2330947642
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3092063731
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.4174013251
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2560598295
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3709639229
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2324763079
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2558275261
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2781669539
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2979650095
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.4236471633
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1440852555
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.3315862380
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1751318800
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2694324099
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3112313359
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1072128858
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.1264132430
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1009334019
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.74060204
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2842829249
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.3324932135
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.4237943212
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2028984325
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.433376261
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.819867519
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1007536932
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3840222452
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.189274903
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2066495979
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3930372468
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3957443313
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.811366104
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2002957508
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4227572867
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3357006016
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2758553102
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3080056741
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1374738718
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3201454014
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4138496104
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3569809685
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1866432806
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3040906710
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1287984445
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4245647991
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.665891615
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3399346317
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1408305084
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2579888037
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2553411374
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.1475780926
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3260956573
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3131350016
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2842176533
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3118938463
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.28422248
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.426852907
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.2996614773
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2448559328
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1483304385
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2334199784
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1212554411
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.1492098030
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.2029463169
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.2569435209
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3118320995
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.884206414
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.3957870820
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1051530906
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.904633488
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3548812393
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1436464463
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2598984050
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1156366257
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1321349634
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2635701152
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1628815656
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1587096960
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1788520495
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1266894356
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.4208954832
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1907027802
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.94679374
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2301164395
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.592192774
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.3572758998
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2274330381
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1213483750
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.4222702824
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.1832569311
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2071616851
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3333732060
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1186821194
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1415913762
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1553624661
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.489959527
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.2247277844
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.2453387782
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.509181729
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1588935860
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.4257089818
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3966524584
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3629633611
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.343275759
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.3556439563
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2968609064
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.1904925899
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.960578149
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.4229070813
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2202870078
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3550384039
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1227656781
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2018062999
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1171923242
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.1091296433
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2270780984
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.520399291
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1888000973
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2008491293
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.147057541
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3621906041
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3259352287
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2114271223
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.344302600
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3399552591
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.511465277
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1679150102
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2741148063
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.339680564
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.586107991
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.1592531960
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.299122904
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2007237255
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.778772468
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1963232441
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1872431459
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.284382180
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.4201154552
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2339563943
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1164731149
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.3752521250
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3369830279
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2059359722
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2905232848
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1470077983
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2592224107
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1073364110
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.2854851684
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3206426955
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3488458889
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.822190440
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.3597781385
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2787922836
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2559220665
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.934652660
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3216401178
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2414221592
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.924494698
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1898666726
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.161950736
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.29415539
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4012225097
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3775140932
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3229929094
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3274678693
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2190799994
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2094261435
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1621331708
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.211548124
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.4077649028
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.602795580
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2340168964
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.894685456
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.401099075
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.266458762
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3545484527
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.500471686
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.2347445287
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3919663782
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.2877664306
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1821116993
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3778519387
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3015338502
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3631321017
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.899174618
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.629825859
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.4233493569
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1107994128
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1964670569
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3555367105
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3208931788
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3264375964
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.654449979
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2725030904
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1413341272
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2781964861
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1215902938
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2947277089
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.428983039
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.837016979
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2588685932
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3017669286
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1804583289
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.275139326
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3690630066
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1347379666
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1708617718
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3706482898
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2676443556
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3764453833
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3137116493
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1992395451
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2411100420
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1731348796
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4031553480
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.710730215
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3261518331
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2370405985
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2616979739
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2953460087
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1565764169
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3144033868
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.737837365
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.3089756227
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.976586834
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.613261101
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.223837851
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.133615334
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3248160954
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2604138133
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4038167181
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4031700876
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1302943490
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1329810970
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.696120601
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3424852798
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1253144916
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3904820090
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2060763598
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2589168960
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.840716523
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2912966786
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1652015642
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.3222390861
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2004618363
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1920112212
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3304213402
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2581909379
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1351224023
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2855654949
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.112045304
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3841171
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.954472165
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.814742550
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.446232062
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3340077970
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2565050267
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1375038448
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3866020834
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.754199177
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2372500254
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.683765747
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.975895569
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2557636698
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2281758766
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1959760302
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.197404527
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2302243005
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1104440133
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.682213523
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.6002397
/workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.397358745



Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2451645094 Sep 11 04:57:41 AM UTC 24 Sep 11 04:57:45 AM UTC 24 2544818672 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2786818663 Sep 11 04:57:43 AM UTC 24 Sep 11 04:57:46 AM UTC 24 2554259805 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2489974867 Sep 11 04:57:41 AM UTC 24 Sep 11 04:57:46 AM UTC 24 2427780010 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.4226894673 Sep 11 04:57:43 AM UTC 24 Sep 11 04:57:47 AM UTC 24 2253509053 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2355617661 Sep 11 04:57:39 AM UTC 24 Sep 11 04:57:48 AM UTC 24 2114316133 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.312989667 Sep 11 04:57:46 AM UTC 24 Sep 11 04:57:52 AM UTC 24 3808951392 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.2381385183 Sep 11 04:57:39 AM UTC 24 Sep 11 04:57:54 AM UTC 24 2461854169 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3523536135 Sep 11 04:57:46 AM UTC 24 Sep 11 04:57:56 AM UTC 24 8773504902 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4157163160 Sep 11 04:57:46 AM UTC 24 Sep 11 04:57:57 AM UTC 24 3352087255 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.3158188485 Sep 11 04:57:55 AM UTC 24 Sep 11 04:57:58 AM UTC 24 2044479999 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1870998956 Sep 11 04:57:47 AM UTC 24 Sep 11 04:57:59 AM UTC 24 2595728477 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2467012302 Sep 11 04:57:45 AM UTC 24 Sep 11 04:57:59 AM UTC 24 2612591585 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1003023454 Sep 11 04:57:51 AM UTC 24 Sep 11 04:58:00 AM UTC 24 17496102402 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.3813791682 Sep 11 04:57:51 AM UTC 24 Sep 11 04:58:00 AM UTC 24 9302677289 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4055146716 Sep 11 04:57:58 AM UTC 24 Sep 11 04:58:01 AM UTC 24 2592842449 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4233079836 Sep 11 04:57:59 AM UTC 24 Sep 11 04:58:03 AM UTC 24 2101391175 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.41455712 Sep 11 04:57:57 AM UTC 24 Sep 11 04:58:06 AM UTC 24 2114562671 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3129007705 Sep 11 04:58:02 AM UTC 24 Sep 11 04:58:08 AM UTC 24 17281115578 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3451980052 Sep 11 04:58:00 AM UTC 24 Sep 11 04:58:08 AM UTC 24 2608504110 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.709313606 Sep 11 04:58:00 AM UTC 24 Sep 11 04:58:08 AM UTC 24 2515339447 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1061701128 Sep 11 04:58:01 AM UTC 24 Sep 11 04:58:08 AM UTC 24 3552968671 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.1418327075 Sep 11 04:57:57 AM UTC 24 Sep 11 04:58:09 AM UTC 24 2460722795 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2511416595 Sep 11 04:57:58 AM UTC 24 Sep 11 04:58:10 AM UTC 24 2160726694 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3612089799 Sep 11 04:58:01 AM UTC 24 Sep 11 04:58:13 AM UTC 24 3638638097 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3681005931 Sep 11 04:58:11 AM UTC 24 Sep 11 04:58:14 AM UTC 24 2496073940 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.3569012289 Sep 11 04:58:10 AM UTC 24 Sep 11 04:58:15 AM UTC 24 2032284963 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.1386169016 Sep 11 04:58:12 AM UTC 24 Sep 11 04:58:15 AM UTC 24 2216820864 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.2833003555 Sep 11 04:58:09 AM UTC 24 Sep 11 04:58:17 AM UTC 24 7027355622 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2758553102 Sep 11 04:58:40 AM UTC 24 Sep 11 04:58:48 AM UTC 24 2516810035 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2082248655 Sep 11 04:58:12 AM UTC 24 Sep 11 04:58:17 AM UTC 24 2289196874 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.2792338179 Sep 11 04:58:10 AM UTC 24 Sep 11 04:58:17 AM UTC 24 2114961135 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2679177954 Sep 11 04:58:15 AM UTC 24 Sep 11 04:58:20 AM UTC 24 2528415338 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1407639741 Sep 11 04:58:18 AM UTC 24 Sep 11 04:58:22 AM UTC 24 3994985255 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.548899728 Sep 11 04:58:14 AM UTC 24 Sep 11 04:58:22 AM UTC 24 2128559222 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.208707258 Sep 11 04:58:18 AM UTC 24 Sep 11 04:58:22 AM UTC 24 9911601976 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.3339148363 Sep 11 04:58:15 AM UTC 24 Sep 11 04:58:25 AM UTC 24 2612241844 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.252292424 Sep 11 04:57:48 AM UTC 24 Sep 11 04:58:25 AM UTC 24 35387319021 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.302489732 Sep 11 04:58:23 AM UTC 24 Sep 11 04:58:27 AM UTC 24 2023864286 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2747374425 Sep 11 04:58:23 AM UTC 24 Sep 11 04:58:27 AM UTC 24 2126049187 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.602925808 Sep 11 04:58:06 AM UTC 24 Sep 11 04:58:29 AM UTC 24 6004004740 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2870902177 Sep 11 04:58:27 AM UTC 24 Sep 11 04:58:30 AM UTC 24 2654053940 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.928753084 Sep 11 04:58:25 AM UTC 24 Sep 11 04:58:30 AM UTC 24 2308221521 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2644216617 Sep 11 04:58:21 AM UTC 24 Sep 11 04:58:31 AM UTC 24 3420508322 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.993375983 Sep 11 04:58:23 AM UTC 24 Sep 11 04:58:32 AM UTC 24 2472472290 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.584827729 Sep 11 04:58:25 AM UTC 24 Sep 11 04:58:33 AM UTC 24 2077979941 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1725549330 Sep 11 04:58:29 AM UTC 24 Sep 11 04:58:33 AM UTC 24 3375884993 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1033399229 Sep 11 04:58:23 AM UTC 24 Sep 11 04:58:35 AM UTC 24 2232950526 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3544797356 Sep 11 04:58:15 AM UTC 24 Sep 11 04:58:35 AM UTC 24 3524125724 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.3614223186 Sep 11 04:58:30 AM UTC 24 Sep 11 04:58:38 AM UTC 24 5024644960 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1110028096 Sep 11 04:58:09 AM UTC 24 Sep 11 04:58:38 AM UTC 24 37206320768 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4247524903 Sep 11 04:57:48 AM UTC 24 Sep 11 04:58:38 AM UTC 24 66199806642 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.970558994 Sep 11 04:58:34 AM UTC 24 Sep 11 04:58:39 AM UTC 24 2039981771 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.4265995772 Sep 11 04:58:29 AM UTC 24 Sep 11 04:58:39 AM UTC 24 2521946999 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1654407794 Sep 11 04:58:26 AM UTC 24 Sep 11 04:58:41 AM UTC 24 2510111680 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4099812748 Sep 11 04:58:22 AM UTC 24 Sep 11 04:58:41 AM UTC 24 5560762848 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2066495979 Sep 11 04:58:38 AM UTC 24 Sep 11 04:58:42 AM UTC 24 2533940113 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2002957508 Sep 11 04:58:40 AM UTC 24 Sep 11 04:58:43 AM UTC 24 2646304312 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2603203008 Sep 11 04:58:32 AM UTC 24 Sep 11 04:58:44 AM UTC 24 63783153230 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.4227572867 Sep 11 04:58:36 AM UTC 24 Sep 11 04:58:44 AM UTC 24 2467289615 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3357006016 Sep 11 04:58:40 AM UTC 24 Sep 11 04:58:44 AM UTC 24 2067981702 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2877202892 Sep 11 04:58:31 AM UTC 24 Sep 11 04:58:45 AM UTC 24 3920211567 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1748709473 Sep 11 04:58:33 AM UTC 24 Sep 11 04:58:47 AM UTC 24 9627869534 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.1374738718 Sep 11 04:58:35 AM UTC 24 Sep 11 04:58:48 AM UTC 24 2114195458 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.637818074 Sep 11 04:58:22 AM UTC 24 Sep 11 04:58:48 AM UTC 24 9442283249 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3957443313 Sep 11 04:58:42 AM UTC 24 Sep 11 04:58:49 AM UTC 24 3332754641 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.1007536932 Sep 11 04:58:42 AM UTC 24 Sep 11 04:58:54 AM UTC 24 3900279347 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.1310407163 Sep 11 04:57:53 AM UTC 24 Sep 11 04:58:50 AM UTC 24 42022130347 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.189274903 Sep 11 04:58:38 AM UTC 24 Sep 11 04:58:52 AM UTC 24 2412253920 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.819867519 Sep 11 04:58:47 AM UTC 24 Sep 11 04:58:52 AM UTC 24 2024891993 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.2817482692 Sep 11 04:58:23 AM UTC 24 Sep 11 04:58:52 AM UTC 24 42172186597 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.500471686 Sep 11 04:58:50 AM UTC 24 Sep 11 04:58:53 AM UTC 24 2725083380 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.2877664306 Sep 11 04:58:48 AM UTC 24 Sep 11 04:58:53 AM UTC 24 2119709554 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.4138496104 Sep 11 04:58:45 AM UTC 24 Sep 11 04:58:53 AM UTC 24 8824138163 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2881006862 Sep 11 04:58:50 AM UTC 24 Sep 11 04:58:54 AM UTC 24 2531956515 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3778519387 Sep 11 04:58:51 AM UTC 24 Sep 11 04:58:54 AM UTC 24 2971370163 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3545484527 Sep 11 04:58:52 AM UTC 24 Sep 11 04:58:56 AM UTC 24 3973378298 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.2906838329 Sep 11 04:59:30 AM UTC 24 Sep 11 04:59:37 AM UTC 24 2013581957 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3321574694 Sep 11 04:59:30 AM UTC 24 Sep 11 04:59:37 AM UTC 24 2117003368 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.266458762 Sep 11 04:58:51 AM UTC 24 Sep 11 04:58:56 AM UTC 24 4317162413 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.811366104 Sep 11 04:58:44 AM UTC 24 Sep 11 04:58:58 AM UTC 24 3271122580 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3919663782 Sep 11 04:58:49 AM UTC 24 Sep 11 04:58:58 AM UTC 24 2140349812 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.401099075 Sep 11 04:58:54 AM UTC 24 Sep 11 04:58:59 AM UTC 24 2019160380 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.428983039 Sep 11 04:58:56 AM UTC 24 Sep 11 04:59:00 AM UTC 24 2100652863 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.3201454014 Sep 11 04:58:45 AM UTC 24 Sep 11 04:59:00 AM UTC 24 9210986754 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2947277089 Sep 11 04:58:55 AM UTC 24 Sep 11 04:59:00 AM UTC 24 2481246720 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.2347445287 Sep 11 04:58:48 AM UTC 24 Sep 11 04:59:01 AM UTC 24 2459336189 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.2588685932 Sep 11 04:58:54 AM UTC 24 Sep 11 04:59:03 AM UTC 24 2110738954 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.654449979 Sep 11 04:58:57 AM UTC 24 Sep 11 04:59:03 AM UTC 24 3445306625 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.275139326 Sep 11 04:58:59 AM UTC 24 Sep 11 04:59:04 AM UTC 24 9246818451 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3264375964 Sep 11 04:59:01 AM UTC 24 Sep 11 04:59:05 AM UTC 24 2024639265 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1565764169 Sep 11 04:59:02 AM UTC 24 Sep 11 04:59:06 AM UTC 24 2498721520 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.837016979 Sep 11 04:58:56 AM UTC 24 Sep 11 04:59:06 AM UTC 24 2512283086 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.3089756227 Sep 11 04:59:02 AM UTC 24 Sep 11 04:59:07 AM UTC 24 2134811882 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3465953286 Sep 11 04:58:51 AM UTC 24 Sep 11 04:59:07 AM UTC 24 3782750567 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1413341272 Sep 11 04:58:57 AM UTC 24 Sep 11 04:59:07 AM UTC 24 2851443195 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.3144033868 Sep 11 04:59:03 AM UTC 24 Sep 11 04:59:08 AM UTC 24 2044804700 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1215902938 Sep 11 04:58:56 AM UTC 24 Sep 11 04:59:09 AM UTC 24 2611405271 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2953460087 Sep 11 04:59:05 AM UTC 24 Sep 11 04:59:09 AM UTC 24 2633326096 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1821116993 Sep 11 04:58:53 AM UTC 24 Sep 11 04:59:13 AM UTC 24 8071416195 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2781964861 Sep 11 04:59:00 AM UTC 24 Sep 11 04:59:13 AM UTC 24 3665282492 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.737837365 Sep 11 04:59:05 AM UTC 24 Sep 11 04:59:14 AM UTC 24 2509973314 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.2616979739 Sep 11 04:59:08 AM UTC 24 Sep 11 04:59:14 AM UTC 24 3553009748 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.1731348796 Sep 11 04:59:09 AM UTC 24 Sep 11 04:59:14 AM UTC 24 2024386920 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2370405985 Sep 11 04:59:06 AM UTC 24 Sep 11 04:59:15 AM UTC 24 2720107170 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.840716523 Sep 11 04:59:10 AM UTC 24 Sep 11 04:59:15 AM UTC 24 2474077596 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.3222390861 Sep 11 04:59:10 AM UTC 24 Sep 11 04:59:15 AM UTC 24 2123407513 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.613261101 Sep 11 04:59:07 AM UTC 24 Sep 11 04:59:17 AM UTC 24 3827056900 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3340077970 Sep 11 04:59:22 AM UTC 24 Sep 11 04:59:36 AM UTC 24 3215211402 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.92183814 Sep 11 04:59:29 AM UTC 24 Sep 11 04:59:37 AM UTC 24 14196839474 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.2110482641 Sep 11 04:58:53 AM UTC 24 Sep 11 04:59:18 AM UTC 24 9129000424 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2060763598 Sep 11 04:59:16 AM UTC 24 Sep 11 04:59:19 AM UTC 24 2981552716 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1652015642 Sep 11 04:59:14 AM UTC 24 Sep 11 04:59:19 AM UTC 24 2522816010 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.2912966786 Sep 11 04:59:13 AM UTC 24 Sep 11 04:59:19 AM UTC 24 2254740769 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3017669286 Sep 11 04:59:01 AM UTC 24 Sep 11 04:59:20 AM UTC 24 8740369650 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.976586834 Sep 11 04:59:09 AM UTC 24 Sep 11 04:59:20 AM UTC 24 12999187388 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1804583289 Sep 11 04:59:01 AM UTC 24 Sep 11 04:59:21 AM UTC 24 6364986362 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3304213402 Sep 11 04:59:15 AM UTC 24 Sep 11 04:59:23 AM UTC 24 8127840824 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.623605765 Sep 11 04:58:09 AM UTC 24 Sep 11 04:59:23 AM UTC 24 113356598637 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2557636698 Sep 11 04:59:18 AM UTC 24 Sep 11 04:59:23 AM UTC 24 2133565411 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1329810970 Sep 11 04:59:18 AM UTC 24 Sep 11 04:59:24 AM UTC 24 2017188824 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1253144916 Sep 11 04:59:16 AM UTC 24 Sep 11 04:59:24 AM UTC 24 26033358815 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3904820090 Sep 11 04:59:15 AM UTC 24 Sep 11 04:59:24 AM UTC 24 4352160799 ps
T245 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.683765747 Sep 11 04:59:19 AM UTC 24 Sep 11 04:59:25 AM UTC 24 2057131993 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4031553480 Sep 11 04:59:07 AM UTC 24 Sep 11 04:59:25 AM UTC 24 3442900045 ps
T246 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.2372500254 Sep 11 04:59:19 AM UTC 24 Sep 11 04:59:25 AM UTC 24 2462172067 ps
T247 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.754199177 Sep 11 04:59:21 AM UTC 24 Sep 11 04:59:25 AM UTC 24 2639501089 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2589168960 Sep 11 04:59:14 AM UTC 24 Sep 11 04:59:26 AM UTC 24 2614379151 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.696120601 Sep 11 04:59:15 AM UTC 24 Sep 11 04:59:28 AM UTC 24 3211878098 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3080056741 Sep 11 04:58:45 AM UTC 24 Sep 11 04:59:28 AM UTC 24 42126481780 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1375038448 Sep 11 04:59:22 AM UTC 24 Sep 11 04:59:28 AM UTC 24 4340755389 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3866020834 Sep 11 04:59:24 AM UTC 24 Sep 11 04:59:28 AM UTC 24 4931287651 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.197404527 Sep 11 04:59:22 AM UTC 24 Sep 11 04:59:28 AM UTC 24 5543023870 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.2036968168 Sep 11 04:59:25 AM UTC 24 Sep 11 04:59:29 AM UTC 24 2139615231 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3676148914 Sep 11 04:59:27 AM UTC 24 Sep 11 04:59:29 AM UTC 24 2789346176 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2004618363 Sep 11 04:59:18 AM UTC 24 Sep 11 04:59:29 AM UTC 24 6736178639 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1920112212 Sep 11 04:59:16 AM UTC 24 Sep 11 04:59:29 AM UTC 24 3900831437 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3424852798 Sep 11 04:59:15 AM UTC 24 Sep 11 04:59:31 AM UTC 24 59142984454 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.975895569 Sep 11 04:59:21 AM UTC 24 Sep 11 04:59:31 AM UTC 24 2515136329 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.2281758766 Sep 11 04:59:25 AM UTC 24 Sep 11 04:59:32 AM UTC 24 12518535766 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.446232062 Sep 11 04:59:25 AM UTC 24 Sep 11 04:59:32 AM UTC 24 2019401401 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.2462415020 Sep 11 04:59:27 AM UTC 24 Sep 11 04:59:34 AM UTC 24 2207747558 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2245917501 Sep 11 04:59:29 AM UTC 24 Sep 11 04:59:35 AM UTC 24 2860405413 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.3579331670 Sep 11 04:59:30 AM UTC 24 Sep 11 04:59:35 AM UTC 24 2466969757 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3930372468 Sep 11 04:58:44 AM UTC 24 Sep 11 04:59:35 AM UTC 24 86003627659 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.1293539049 Sep 11 04:59:27 AM UTC 24 Sep 11 04:59:37 AM UTC 24 2508831706 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.517956087 Sep 11 04:58:52 AM UTC 24 Sep 11 04:59:37 AM UTC 24 59507118606 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.777795024 Sep 11 04:59:25 AM UTC 24 Sep 11 04:59:37 AM UTC 24 2482457777 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1959760302 Sep 11 04:59:25 AM UTC 24 Sep 11 04:59:40 AM UTC 24 4118980527 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.3480269921 Sep 11 04:59:31 AM UTC 24 Sep 11 04:59:40 AM UTC 24 2029261700 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1851484528 Sep 11 04:59:29 AM UTC 24 Sep 11 04:59:40 AM UTC 24 3296424724 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2869304918 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:40 AM UTC 24 2129972768 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.1339479745 Sep 11 04:59:36 AM UTC 24 Sep 11 04:59:40 AM UTC 24 2769268791 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1544105030 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:41 AM UTC 24 2025297622 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.3126064741 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:41 AM UTC 24 2477678354 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.786885445 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:41 AM UTC 24 2264447079 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.547902647 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:10 AM UTC 24 2256854807 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3002955011 Sep 11 04:59:33 AM UTC 24 Sep 11 04:59:41 AM UTC 24 3756469675 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2189938701 Sep 11 04:59:32 AM UTC 24 Sep 11 04:59:42 AM UTC 24 2611034904 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.3675843473 Sep 11 04:59:31 AM UTC 24 Sep 11 04:59:42 AM UTC 24 2510423261 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.253277506 Sep 11 04:58:33 AM UTC 24 Sep 11 04:59:43 AM UTC 24 22009388779 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1910095480 Sep 11 04:59:35 AM UTC 24 Sep 11 04:59:44 AM UTC 24 5352624706 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.4201638844 Sep 11 04:59:41 AM UTC 24 Sep 11 04:59:44 AM UTC 24 8547637704 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2725030904 Sep 11 04:59:00 AM UTC 24 Sep 11 04:59:44 AM UTC 24 56232106547 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.876297588 Sep 11 04:59:41 AM UTC 24 Sep 11 04:59:44 AM UTC 24 2424357166 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.1014359833 Sep 11 04:59:42 AM UTC 24 Sep 11 04:59:45 AM UTC 24 2132569118 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.2680804577 Sep 11 04:59:38 AM UTC 24 Sep 11 04:59:46 AM UTC 24 2510185684 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3898765951 Sep 11 04:59:28 AM UTC 24 Sep 11 04:59:46 AM UTC 24 4264599901 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1085922344 Sep 11 04:59:42 AM UTC 24 Sep 11 04:59:47 AM UTC 24 2497083160 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2806597710 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:48 AM UTC 24 11418160067 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3959091704 Sep 11 04:59:43 AM UTC 24 Sep 11 04:59:48 AM UTC 24 2523987031 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2436488679 Sep 11 04:59:38 AM UTC 24 Sep 11 04:59:48 AM UTC 24 2608437043 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2215864513 Sep 11 04:59:41 AM UTC 24 Sep 11 04:59:49 AM UTC 24 3079719263 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2631797262 Sep 11 04:59:41 AM UTC 24 Sep 11 04:59:49 AM UTC 24 3727552450 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1704364522 Sep 11 04:59:42 AM UTC 24 Sep 11 04:59:49 AM UTC 24 2016291294 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3565170346 Sep 11 04:59:44 AM UTC 24 Sep 11 04:59:50 AM UTC 24 2629558753 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2209769274 Sep 11 04:58:21 AM UTC 24 Sep 11 04:59:50 AM UTC 24 25334175325 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.1090013124 Sep 11 04:59:43 AM UTC 24 Sep 11 04:59:50 AM UTC 24 2089719425 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3971601279 Sep 11 04:59:45 AM UTC 24 Sep 11 04:59:51 AM UTC 24 4705437219 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.2806267740 Sep 11 04:59:47 AM UTC 24 Sep 11 04:59:51 AM UTC 24 2035862559 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.1928437741 Sep 11 04:59:47 AM UTC 24 Sep 11 04:59:51 AM UTC 24 2127517668 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.3000813928 Sep 11 04:59:48 AM UTC 24 Sep 11 04:59:52 AM UTC 24 2486679356 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3484719322 Sep 11 04:58:19 AM UTC 24 Sep 11 04:59:53 AM UTC 24 112576559146 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.3840222452 Sep 11 04:58:43 AM UTC 24 Sep 11 04:59:55 AM UTC 24 160785628400 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.44274389 Sep 11 04:59:52 AM UTC 24 Sep 11 04:59:55 AM UTC 24 2038937345 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2139073616 Sep 11 04:59:47 AM UTC 24 Sep 11 04:59:55 AM UTC 24 6282073185 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.657875904 Sep 11 04:59:51 AM UTC 24 Sep 11 04:59:56 AM UTC 24 4415741051 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.2710007748 Sep 11 04:59:49 AM UTC 24 Sep 11 04:59:56 AM UTC 24 2509512453 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3132732852 Sep 11 04:59:56 AM UTC 24 Sep 11 05:00:11 AM UTC 24 4159447559 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.2432518159 Sep 11 04:59:42 AM UTC 24 Sep 11 04:59:57 AM UTC 24 12556427992 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.241775590 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:11 AM UTC 24 2118761365 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3056574877 Sep 11 04:59:54 AM UTC 24 Sep 11 04:59:58 AM UTC 24 2482326884 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.1847047466 Sep 11 04:59:48 AM UTC 24 Sep 11 04:59:58 AM UTC 24 2121420317 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2742431725 Sep 11 04:59:37 AM UTC 24 Sep 11 04:59:58 AM UTC 24 31959712891 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.538611484 Sep 11 04:59:42 AM UTC 24 Sep 11 04:59:58 AM UTC 24 4369967847 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1890935942 Sep 11 04:59:46 AM UTC 24 Sep 11 04:59:58 AM UTC 24 347828847592 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1958226069 Sep 11 04:59:46 AM UTC 24 Sep 11 04:59:58 AM UTC 24 4240896913 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1169873179 Sep 11 04:57:47 AM UTC 24 Sep 11 04:59:59 AM UTC 24 49044717439 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1881438890 Sep 11 04:58:59 AM UTC 24 Sep 11 04:59:59 AM UTC 24 17565513856 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1191893410 Sep 11 04:59:49 AM UTC 24 Sep 11 04:59:59 AM UTC 24 2612177767 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.14581188 Sep 11 04:59:51 AM UTC 24 Sep 11 04:59:59 AM UTC 24 3100781879 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.833421565 Sep 11 04:59:57 AM UTC 24 Sep 11 05:00:00 AM UTC 24 3257415527 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.1926353490 Sep 11 04:59:56 AM UTC 24 Sep 11 05:00:01 AM UTC 24 2613261291 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1056934578 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:01 AM UTC 24 2096435148 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.1927827749 Sep 11 04:59:53 AM UTC 24 Sep 11 05:00:02 AM UTC 24 2110773986 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3765627068 Sep 11 04:59:55 AM UTC 24 Sep 11 05:00:02 AM UTC 24 2043524776 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2156033769 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:02 AM UTC 24 4945331154 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3469765855 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:02 AM UTC 24 8425001617 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.4020815531 Sep 11 04:59:29 AM UTC 24 Sep 11 05:00:03 AM UTC 24 18596441544 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.2283653766 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:03 AM UTC 24 2118085358 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1408790370 Sep 11 05:00:00 AM UTC 24 Sep 11 05:00:03 AM UTC 24 2071185980 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3761552439 Sep 11 05:00:00 AM UTC 24 Sep 11 05:00:04 AM UTC 24 2472335743 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.249293978 Sep 11 04:59:46 AM UTC 24 Sep 11 05:00:05 AM UTC 24 4839896518 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2425520990 Sep 11 04:59:56 AM UTC 24 Sep 11 05:00:06 AM UTC 24 2509193782 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.225800656 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:07 AM UTC 24 3006909387 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.119460728 Sep 11 04:59:29 AM UTC 24 Sep 11 05:00:07 AM UTC 24 26587545497 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1325522029 Sep 11 04:59:59 AM UTC 24 Sep 11 05:00:07 AM UTC 24 2308236182 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1386954670 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:08 AM UTC 24 3695230680 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.1892355231 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:10 AM UTC 24 2037954196 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.404255518 Sep 11 04:59:52 AM UTC 24 Sep 11 05:00:10 AM UTC 24 19205721893 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.4127134048 Sep 11 05:00:07 AM UTC 24 Sep 11 05:00:11 AM UTC 24 3929333139 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.663943539 Sep 11 05:00:07 AM UTC 24 Sep 11 05:00:11 AM UTC 24 2632823016 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1524583541 Sep 11 05:00:08 AM UTC 24 Sep 11 05:00:13 AM UTC 24 5234069416 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2418331110 Sep 11 05:00:00 AM UTC 24 Sep 11 05:00:13 AM UTC 24 2512781433 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1662400496 Sep 11 05:00:08 AM UTC 24 Sep 11 05:00:13 AM UTC 24 3766396366 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.105272800 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:13 AM UTC 24 2487602757 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3261518331 Sep 11 04:59:08 AM UTC 24 Sep 11 05:00:14 AM UTC 24 24829596187 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.1198090196 Sep 11 05:00:12 AM UTC 24 Sep 11 05:00:15 AM UTC 24 2159435218 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3589572235 Sep 11 05:00:00 AM UTC 24 Sep 11 05:00:15 AM UTC 24 2614516133 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.4202084545 Sep 11 05:00:11 AM UTC 24 Sep 11 05:00:15 AM UTC 24 4604217509 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2373510072 Sep 11 05:00:02 AM UTC 24 Sep 11 05:00:16 AM UTC 24 3225888656 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1573883918 Sep 11 05:00:12 AM UTC 24 Sep 11 05:00:17 AM UTC 24 2486886408 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3499857056 Sep 11 05:00:07 AM UTC 24 Sep 11 05:00:17 AM UTC 24 2510105610 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1244290960 Sep 11 05:00:14 AM UTC 24 Sep 11 05:00:17 AM UTC 24 2654627487 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3813604600 Sep 11 05:00:13 AM UTC 24 Sep 11 05:00:18 AM UTC 24 2094723427 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3632183663 Sep 11 05:00:15 AM UTC 24 Sep 11 05:00:18 AM UTC 24 9746580886 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1534729203 Sep 11 05:00:01 AM UTC 24 Sep 11 05:00:19 AM UTC 24 3436158672 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1164471676 Sep 11 05:00:00 AM UTC 24 Sep 11 05:00:19 AM UTC 24 4178644646 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.4258582467 Sep 11 05:00:14 AM UTC 24 Sep 11 05:00:19 AM UTC 24 2772486206 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.4102864670 Sep 11 05:00:13 AM UTC 24 Sep 11 05:00:20 AM UTC 24 2514478268 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.829748819 Sep 11 04:59:45 AM UTC 24 Sep 11 05:00:20 AM UTC 24 45203034907 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.4048349130 Sep 11 05:00:18 AM UTC 24 Sep 11 05:00:21 AM UTC 24 2144615471 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.710730215 Sep 11 04:59:08 AM UTC 24 Sep 11 05:00:21 AM UTC 24 51868306212 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1964687804 Sep 11 05:00:17 AM UTC 24 Sep 11 05:00:21 AM UTC 24 2882925751 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.897003434 Sep 11 04:59:52 AM UTC 24 Sep 11 05:00:22 AM UTC 24 13732403760 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3825397800 Sep 11 05:00:14 AM UTC 24 Sep 11 05:00:22 AM UTC 24 3171763002 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3957753256 Sep 11 05:00:12 AM UTC 24 Sep 11 05:00:22 AM UTC 24 2011622235 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.2883992700 Sep 11 05:00:17 AM UTC 24 Sep 11 05:00:23 AM UTC 24 2126370268 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.544842534 Sep 11 05:00:19 AM UTC 24 Sep 11 05:00:23 AM UTC 24 2636098279 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.854422258 Sep 11 05:00:06 AM UTC 24 Sep 11 05:00:23 AM UTC 24 5227953396 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_10/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1009360112 Sep 11 04:58:09 AM UTC 24 Sep 11 05:00:23 AM UTC 24 42009614020 ps