Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.72 99.37 95.20 100.00 100.00 97.75 100.00


Total modules in report: 40
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
prim_sync_reqack 87.50 100.00 50.00 100.00 100.00
  tlul_rsp_intg_gen 91.67 83.33 100.00
  prim_reg_cdc_arb 92.91 96.00 93.02 82.61 100.00
  prim_subreg_arb 95.83 87.50 100.00 100.00
sysrst_ctrl_combo 96.15 100.00 92.31
  prim_reg_cdc 97.30 100.00 89.20 100.00 100.00
  sysrst_ctrl_detect 98.35 100.00 96.30 100.00 95.45 100.00
sysrst_ctrl_reg_top 98.60 100.00 94.41 100.00 100.00
tlul_adapter_reg 98.98 100.00 95.92 100.00 100.00
sysrst_ctrl 99.02 100.00 96.08 100.00 100.00
sysrst_ctrl_comboact 99.19 100.00 97.56 100.00
sysrst_ctrl_csr_assert_fpv 100.00 100.00
tlul_data_integ_dec 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
sysrst_ctrl_ulp 100.00 100.00 100.00
prim_alert_sender 100.00 100.00
sysrst_ctrl_intr 100.00 100.00 100.00 100.00
sysrst_ctrl_keyintr 100.00 100.00
tlul_assert 100.00 100.00 100.00 100.00
prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
prim_intr_hw 100.00 100.00 100.00 100.00 100.00
prim_pulse_sync 100.00 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
sysrst_ctrl_pin 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
sysrst_ctrl_autoblock 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
prim_generic_flop_2sync
prim_flop
prim_flop_2sync
tb