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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 28 68 70.83 28
Automatically Generated Cross Bins 96 28 68 70.83 28
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] [auto[0]] * [auto[0]] [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[0]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[0]] [auto[1]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 54 1 T40 1 T41 1 T111 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T91 1 T114 1 T116 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 44 1 T31 2 T41 1 T121 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 21 1 T155 1 T42 2 T115 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 50 1 T31 1 T40 1 T86 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 26 1 T91 2 T42 1 T114 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 41 1 T31 1 T91 1 T121 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 18 1 T91 2 T112 1 T229 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 44 1 T37 1 T41 1 T229 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 15 1 T91 1 T155 1 T114 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 24 1 T121 1 T154 1 T38 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 30 1 T155 1 T42 1 T229 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 38 1 T41 1 T154 2 T39 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 25 1 T91 1 T155 1 T116 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 43 1 T37 1 T41 1 T229 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 35 1 T114 1 T118 1 T119 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 47 1 T111 2 T113 2 T116 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 17 1 T155 1 T115 1 T235 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 34 1 T86 1 T38 1 T39 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 26 1 T91 1 T229 2 T114 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 41 1 T37 2 T121 1 T155 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 29 1 T155 2 T112 2 T116 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 29 1 T37 4 T40 2 T41 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 7 1 T116 1 T322 1 T327 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 36 1 T41 2 T121 2 T111 7
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 15 1 T91 1 T155 3 T112 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 20 1 T37 2 T228 1 T43 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 18 1 T91 1 T42 1 T229 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 33 1 T121 1 T39 1 T258 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 19 1 T155 1 T42 1 T118 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 55 1 T37 3 T40 1 T41 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 52 1 T37 2 T228 9 T112 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 50 1 T31 1 T40 1 T52 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 14 1 T114 1 T235 2 T322 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 38 1 T31 2 T40 3 T154 3
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 27 1 T155 1 T42 2 T112 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 41 1 T31 1 T40 1 T52 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 20 1 T42 2 T112 1 T115 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 62 1 T31 9 T40 1 T86 2
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 15 1 T91 1 T112 2 T115 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 40 1 T40 2 T52 1 T86 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 18 1 T42 1 T114 1 T115 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 47 1 T41 1 T121 1 T38 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 28 1 T91 1 T155 2 T42 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 37 1 T41 1 T38 1 T39 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 25 1 T91 1 T155 1 T42 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 63 1 T40 4 T121 2 T154 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 40 1 T112 1 T229 6 T114 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 48 1 T37 1 T40 1 T52 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 24 1 T91 1 T115 1 T322 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 47 1 T41 1 T39 2 T232 6
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 25 1 T155 1 T42 1 T112 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 42 1 T52 6 T41 1 T121 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 44 1 T91 2 T42 3 T112 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 33 1 T37 1 T40 1 T41 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 72 1 T37 7 T86 7 T42 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 47 1 T40 1 T52 4 T154 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 38 1 T91 1 T155 1 T112 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 51 1 T39 1 T232 3 T336 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 78 1 T91 2 T86 2 T155 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 51 1 T121 1 T336 1 T233 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 52 1 T155 1 T115 1 T322 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 178 1 T41 11 T121 1 T154 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 71 1 T91 2 T112 1 T114 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 1 1 T229 1 - - - -
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1 1 T328 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T339 1 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 17 1 T235 1 T323 1 T237 4


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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