SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 75.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
sysrst_ctrl_combo_precondition_det_cg2 | 33.33 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg3 | 66.67 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_combo_precondition_det_cg1 | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
33.33 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 2 | 1 | 33.33 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 2 | 1 | 33.33 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
66.67 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 1 | 2 | 66.67 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 1 | 2 | 66.67 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 3 | 0 | 3 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 2 | 1 | 33.33 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
max_range | 0 | 1 | 1 | |
mid_range | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
min_range | 413 | 1 | T34 | 1 | T35 | 7 | T36 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 1 | 2 | 66.67 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
mid_range | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 7 | 1 | T96 | 1 | T417 | 6 | - | - | ||||
min_range | 406 | 1 | T34 | 1 | T35 | 7 | T36 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 17 | 1 | T418 | 7 | T419 | 1 | T397 | 4 | ||||
mid_range | 5 | 1 | T420 | 5 | - | - | - | - | ||||
min_range | 391 | 1 | T34 | 1 | T35 | 7 | T36 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 3 | 0 | 3 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
max_range | 7 | 1 | T292 | 1 | T304 | 4 | T421 | 1 | ||||
mid_range | 8 | 1 | T293 | 4 | T422 | 1 | T393 | 3 | ||||
min_range | 398 | 1 | T34 | 1 | T35 | 7 | T36 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |