Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2042

1

T34

24

T36

18

T37

9

auto[1]

613

1

T36

6

T37

7

T44

7

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2048

1

T34

24

T36

23

T37

4

auto[1]

607

1

T36

1

T37

12

T44

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2078

1

T34

24

T36

24

T37

9

auto[1]

577

1

T37

7

T44

12

T43

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2165

1

T34

18

T36

23

T37

16

auto[1]

490

1

T34

6

T36

1

T44

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T34

18

T36

23

T37

16

auto[1]

253

1

T34

6

T36

1

T59

11

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2412

1

T34

24

T36

24

T37

16

auto[1]

243

1

T47

3

T141

4

T293

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2432

1

T34

24

T36

22

T37

16

auto[1]

223

1

T36

2

T59

10

T94

6

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2372

1

T34

24

T36

24

T37

16

auto[1]

283

1

T59

6

T94

6

T95

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2469

1

T34

24

T36

18

T37

16

auto[1]

186

1

T36

6

T95

2

T292

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1976

1

T34

24

T36

23

T37

7

auto[1]

679

1

T36

1

T37

9

T44

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

799

1

T37

7

T44

15

T43

14

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

78

1

T59

8

T132

8

T295

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T36

1

T384

3

T385

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T386

1

T374

3

T291

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

106

1

T59

4

T290

3

T387

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T388

1

T389

2

T390

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T47

5

T142

3

T293

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T294

2

T386

1

T391

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T36

1

T59

7

T58

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T36

1

T392

4

T393

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13

1

T147

7

T394

1

T391

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T142

3

T395

1

T396

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T94

6

T362

4

T387

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T295

1

T131

7

T397

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T95

2

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

70

1

T47

3

T294

5

T398

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

42

1

T295

15

T384

1

T372

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

28

1

T399

2

T395

1

T372

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T293

2

T290

2

T388

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

24

1

T399

3

T400

4

T362

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T401

7

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T294

2

T131

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T402

4

T370

2

T374

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T132

2

T372

3

T131

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

7

1

T304

3

T403

1

T390

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T141

4

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T397

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

124

1

T36

1

T47

5

T303

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

157

1

T36

1

T360

8

T295

20

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

66

1

T59

7

T141

4

T303

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

85

1

T293

2

T306

11

T365

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T304

3

T399

2

T372

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T46

2

T305

3

T298

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T43

5

T296

3

T305

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

131

1

T44

8

T59

4

T142

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

71

1

T37

4

T45

8

T296

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T302

10

T143

4

T361

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T361

4

T290

3

T300

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T356

4

T369

7

T363

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T296

2

T359

1

T150

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

25

1

T47

3

T357

1

T359

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T130

4

T357

1

T148

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

113

1

T59

8

T94

6

T95

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T37

3

T143

5

T297

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T58

3

T305

5

T132

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

48

1

T43

4

T145

1

T362

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

51

1

T36

1

T359

4

T404

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

28

1

T44

3

T298

5

T358

8

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T43

4

T46

1

T358

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T309

1

T307

1

T405

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

22

1

T361

6

T290

4

T385

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T45

6

T356

2

T295

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

29

1

T302

5

T356

6

T297

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T44

2

T45

2

T297

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T360

3

T306

2

T399

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T44

2

T43

1

T357

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T404

2

T406

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T302

2

T356

1

T184

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded