Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689

1

T15

8

T28

14

T81

10

auto[1]

721

1

T15

12

T28

6

T81

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

329

1

T15

5

T28

4

T81

4

from_0to1

328

1

T15

5

T28

4

T81

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T15

9

T28

6

T81

10

auto[1]

703

1

T15

11

T28

14

T81

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

714

1

T15

10

T28

10

T81

11

auto[1]

696

1

T15

10

T28

10

T81

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T81

2

T68

2

T139

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T15

1

T28

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T28

1

T12

2

T140

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T28

1

T89

1

T12

2

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T81

1

T89

2

T68

2

auto[0]

from_0to1

auto[0]

auto[1]

35

1

T28

1

T68

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T15

1

T28

1

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T15

1

T28

1

T213

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T15

1

T68

1

T12

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T15

2

T28

1

T213

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T15

1

T89

1

T68

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T81

2

T140

2

T289

2

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T81

2

T213

1

T289

3

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T15

2

T12

1

T140

1

auto[1]

from_0to1

auto[1]

auto[0]

50

1

T28

1

T81

1

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T15

1

T81

1

T89

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708

1

T15

8

T28

8

T81

10

auto[1]

702

1

T15

12

T28

12

T81

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

320

1

T15

5

T28

5

T81

5

from_0to1

321

1

T15

5

T28

4

T81

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684

1

T15

9

T28

7

T81

6

auto[1]

726

1

T15

11

T28

13

T81

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

688

1

T15

10

T28

5

T81

10

auto[1]

722

1

T15

10

T28

15

T81

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T15

1

T68

2

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T15

1

T81

1

T68

1

auto[0]

from_1to0

auto[1]

auto[0]

39

1

T12

2

T213

1

T139

1

auto[0]

from_1to0

auto[1]

auto[1]

40

1

T28

2

T139

1

T289

2

auto[0]

from_0to1

auto[0]

auto[0]

55

1

T81

2

T12

3

T213

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T15

2

T68

1

T12

2

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T15

2

T81

1

T89

1

auto[0]

from_0to1

auto[1]

auto[1]

46

1

T28

1

T81

1

T12

2

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T81

1

T89

1

T68

2

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T12

4

T431

1

T181

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T15

1

T28

1

T81

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T15

2

T28

2

T81

2

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T28

1

T89

1

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T28

1

T81

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T15

1

T89

1

T68

2

auto[1]

from_0to1

auto[1]

auto[1]

31

1

T28

1

T68

1

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719

1

T15

13

T28

13

T81

10

auto[1]

691

1

T15

7

T28

7

T81

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

337

1

T15

5

T28

6

T81

4

from_0to1

333

1

T15

5

T28

5

T81

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722

1

T15

10

T28

9

T81

10

auto[1]

688

1

T15

10

T28

11

T81

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710

1

T15

12

T28

10

T81

9

auto[1]

700

1

T15

8

T28

10

T81

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T15

1

T81

1

T89

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T81

1

T12

1

T139

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T15

1

T28

2

T89

1

auto[0]

from_1to0

auto[1]

auto[1]

36

1

T15

1

T28

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T15

2

T28

2

T89

1

auto[0]

from_0to1

auto[0]

auto[1]

46

1

T81

1

T89

1

T68

2

auto[0]

from_0to1

auto[1]

auto[0]

41

1

T15

1

T28

1

T81

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T28

1

T81

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T81

1

T89

2

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T15

1

T28

1

T12

2

auto[1]

from_1to0

auto[1]

auto[0]

51

1

T15

1

T28

1

T81

1

auto[1]

from_1to0

auto[1]

auto[1]

31

1

T28

1

T89

1

T68

2

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T15

1

T89

1

T12

2

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T89

1

T68

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T15

1

T89

1

T68

2

auto[1]

from_0to1

auto[1]

auto[1]

43

1

T28

1

T81

2

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T15

12

T28

9

T81

8

auto[1]

735

1

T15

8

T28

11

T81

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

346

1

T15

6

T28

4

T81

6

from_0to1

347

1

T15

5

T28

5

T81

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

685

1

T15

10

T28

14

T81

13

auto[1]

725

1

T15

10

T28

6

T81

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

730

1

T15

9

T28

10

T81

10

auto[1]

680

1

T15

11

T28

10

T81

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T15

1

T28

1

T81

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T15

2

T28

2

T81

3

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T15

1

T89

1

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T15

2

T89

1

T68

2

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T15

1

T89

1

T139

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T15

1

T28

1

T68

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T28

1

T89

1

T68

1

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T81

1

T89

2

T213

1

auto[1]

from_1to0

auto[0]

auto[0]

54

1

T28

1

T81

2

T89

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T68

1

T12

1

T139

2

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T89

1

T12

1

T139

2

auto[1]

from_1to0

auto[1]

auto[1]

32

1

T12

1

T289

1

T282

2

auto[1]

from_0to1

auto[0]

auto[0]

52

1

T28

2

T81

1

T89

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T28

1

T89

2

T139

1

auto[1]

from_0to1

auto[1]

auto[0]

45

1

T15

1

T81

1

T89

1

auto[1]

from_0to1

auto[1]

auto[1]

50

1

T15

2

T81

3

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691

1

T15

9

T28

13

T81

15

auto[1]

719

1

T15

11

T28

7

T81

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

340

1

T15

7

T28

5

T81

4

from_0to1

343

1

T15

8

T28

6

T81

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674

1

T15

8

T28

7

T81

10

auto[1]

736

1

T15

12

T28

13

T81

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

717

1

T15

9

T28

11

T81

12

auto[1]

693

1

T15

11

T28

9

T81

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T15

1

T28

1

T81

2

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T15

1

T12

2

T213

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T15

1

T89

2

T12

1

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T15

2

T28

3

T81

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T81

2

T68

1

T12

3

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T15

1

T81

1

T89

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T28

2

T68

1

T12

4

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T28

1

T81

1

T89

2

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T28

1

T68

2

T282

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T89

2

T12

2

T282

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T15

1

T68

1

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T15

1

T81

1

T89

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T15

2

T89

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T15

1

T28

1

T68

1

auto[1]

from_0to1

auto[1]

auto[0]

49

1

T15

2

T28

2

T68

1

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T15

2

T89

1

T68

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712

1

T15

13

T28

9

T81

8

auto[1]

698

1

T15

7

T28

11

T81

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

358

1

T15

6

T28

4

T81

5

from_0to1

344

1

T15

5

T28

5

T81

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

719

1

T15

12

T28

13

T81

7

auto[1]

691

1

T15

8

T28

7

T81

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

695

1

T15

7

T28

4

T81

11

auto[1]

715

1

T15

13

T28

16

T81

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T15

1

T28

1

T81

1

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T15

4

T28

1

T89

2

auto[0]

from_1to0

auto[1]

auto[0]

47

1

T12

1

T139

2

T289

1

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T68

1

T12

5

T140

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T81

1

T68

1

T12

2

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T15

1

T28

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T15

1

T28

1

T81

1

auto[0]

from_0to1

auto[1]

auto[1]

32

1

T15

1

T68

2

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T81

1

T68

1

T12

2

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T28

2

T81

1

T68

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T81

1

T68

3

T139

1

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T15

1

T81

1

T89

1

auto[1]

from_0to1

auto[0]

auto[0]

45

1

T68

1

T12

3

T213

1

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T15

1

T28

2

T12

2

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T81

2

T68

2

T12

3

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T15

1

T28

1

T81

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

696

1

T15

12

T28

14

T81

13

auto[1]

714

1

T15

8

T28

6

T81

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

337

1

T15

3

T28

5

T81

5

from_0to1

341

1

T15

4

T28

5

T81

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

744

1

T15

13

T28

11

T81

8

auto[1]

666

1

T15

7

T28

9

T81

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T15

14

T28

13

T81

10

auto[1]

707

1

T15

6

T28

7

T81

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T81

1

T68

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

44

1

T15

1

T28

1

T81

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T15

1

T81

2

T68

1

auto[0]

from_1to0

auto[1]

auto[1]

31

1

T28

1

T89

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T68

1

T12

2

T213

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T15

3

T28

1

T81

3

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T28

1

T68

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

38

1

T28

1

T89

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T28

1

T12

5

T139

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T89

1

T12

1

T289

1

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T28

1

T68

1

T213

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T15

1

T28

1

T81

1

auto[1]

from_0to1

auto[0]

auto[0]

48

1

T28

2

T89

1

T213

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T89

1

T12

1

T139

1

auto[1]

from_0to1

auto[1]

auto[0]

38

1

T15

1

T68

1

T12

5

auto[1]

from_0to1

auto[1]

auto[1]

47

1

T81

1

T68

1

T139

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

684

1

T15

8

T28

13

T81

13

auto[1]

726

1

T15

12

T28

7

T81

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

332

1

T15

7

T28

6

T81

5

from_0to1

328

1

T15

7

T28

7

T81

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708

1

T15

11

T28

9

T81

11

auto[1]

702

1

T15

9

T28

11

T81

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732

1

T15

9

T28

13

T81

11

auto[1]

678

1

T15

11

T28

7

T81

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T15

1

T28

3

T81

2

auto[0]

from_1to0

auto[0]

auto[1]

31

1

T15

1

T140

1

T282

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T28

1

T68

1

T12

2

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T89

1

T68

1

T12

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T15

2

T28

1

T81

1

auto[0]

from_0to1

auto[0]

auto[1]

33

1

T15

1

T81

1

T89

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T28

3

T81

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T28

1

T81

1

T68

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T15

1

T12

3

T139

1

auto[1]

from_1to0

auto[0]

auto[1]

41

1

T15

1

T81

1

T213

1

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T15

1

T28

1

T81

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T15

2

T28

1

T81

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T15

1

T89

2

T68

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T28

1

T68

1

T213

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T28

1

T81

1

T12

2

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T15

3

T89

1

T12

1