Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

112521

1

T4

21

T6

4

T23

23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	135325	1			T4	22		T5	2		T6	3
values[0x0]	61369	1			T4	13		T6	4		T1	4
values[0x1]	62707	1			T4	9		T6	4		T1	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

140557

1

T4

22

T6

6

T23

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1831	1			T1	11		T29	4		T12	6
valid_sources[0x01]	1192	1			T82	3		T89	1		T12	308
valid_sources[0x02]	846	1			T20	1		T89	1		T13	1
valid_sources[0x03]	955	1			T21	1		T8	3		T213	5
valid_sources[0x04]	1250	1			T28	4		T81	1		T213	6
valid_sources[0x05]	910	1			T81	3		T213	1		T214	4
valid_sources[0x06]	1009	1			T20	1		T89	1		T213	1
valid_sources[0x07]	772	1			T82	4		T318	1		T213	1
valid_sources[0x08]	714	1			T28	3		T89	1		T90	1
valid_sources[0x09]	736	1			T22	1		T28	3		T89	1
valid_sources[0x0a]	1430	1			T16	9		T82	2		T89	2
valid_sources[0x0b]	1698	1			T31	17		T82	1		T89	1
valid_sources[0x0c]	732	1			T89	3		T77	1		T213	1
valid_sources[0x0d]	863	1			T20	1		T82	1		T90	1
valid_sources[0x0e]	1586	1			T89	1		T8	4		T60	1
valid_sources[0x0f]	807	1			T82	4		T68	4		T75	1
valid_sources[0x10]	835	1			T18	1		T213	2		T214	3
valid_sources[0x11]	845	1			T82	1		T68	1		T213	3
valid_sources[0x12]	774	1			T8	4		T213	2		T289	2
valid_sources[0x13]	1168	1			T28	1		T82	1		T89	3
valid_sources[0x14]	904	1			T20	1		T28	2		T82	2
valid_sources[0x15]	1033	1			T22	1		T8	3		T12	29
valid_sources[0x16]	787	1			T67	3		T75	2		T213	3
valid_sources[0x17]	932	1			T12	40		T213	1		T214	4
valid_sources[0x18]	912	1			T81	2		T8	2		T68	8
valid_sources[0x19]	1149	1			T14	1		T82	3		T213	4
valid_sources[0x1a]	739	1			T82	2		T60	1		T213	4
valid_sources[0x1b]	905	1			T213	2		T140	4		T289	3
valid_sources[0x1c]	1259	1			T81	2		T30	9		T213	3
valid_sources[0x1d]	847	1			T20	1		T82	1		T90	2
valid_sources[0x1e]	723	1			T19	1		T213	2		T289	2
valid_sources[0x1f]	2197	1			T82	2		T89	1		T90	1
valid_sources[0x20]	1539	1			T15	6		T18	1		T82	1
valid_sources[0x21]	765	1			T22	2		T28	1		T30	2
valid_sources[0x22]	925	1			T60	1		T213	1		T214	5
valid_sources[0x23]	796	1			T18	1		T20	1		T81	2
valid_sources[0x24]	805	1			T6	2		T81	2		T89	1
valid_sources[0x25]	824	1			T28	6		T82	1		T89	1
valid_sources[0x26]	919	1			T68	4		T213	1		T289	2
valid_sources[0x27]	901	1			T15	37		T20	1		T22	3
valid_sources[0x28]	752	1			T82	1		T67	1		T68	2
valid_sources[0x29]	1169	1			T22	5		T28	5		T67	2
valid_sources[0x2a]	1090	1			T8	2		T213	6		T214	1
valid_sources[0x2b]	781	1			T22	5		T89	1		T90	1
valid_sources[0x2c]	1449	1			T18	1		T81	4		T82	1
valid_sources[0x2d]	894	1			T20	1		T22	1		T82	1
valid_sources[0x2e]	681	1			T89	1		T213	1		T214	4
valid_sources[0x2f]	960	1			T22	2		T82	3		T213	3
valid_sources[0x30]	730	1			T20	1		T21	1		T89	2
valid_sources[0x31]	850	1			T22	1		T82	1		T8	3
valid_sources[0x32]	724	1			T213	2		T289	3		T282	1
valid_sources[0x33]	1507	1			T213	3		T139	190		T140	10
valid_sources[0x34]	883	1			T91	1		T68	1		T213	1
valid_sources[0x35]	1174	1			T81	5		T35	5		T282	1
valid_sources[0x36]	850	1			T81	2		T90	2		T10	2
valid_sources[0x37]	1304	1			T8	3		T213	1		T289	1
valid_sources[0x38]	874	1			T30	2		T82	2		T89	3
valid_sources[0x39]	1197	1			T20	1		T28	1		T81	7
valid_sources[0x3a]	878	1			T28	1		T82	5		T213	3
valid_sources[0x3b]	916	1			T6	3		T91	1		T90	2
valid_sources[0x3c]	1601	1			T29	9		T82	3		T89	1
valid_sources[0x3d]	747	1			T81	13		T89	1		T60	1
valid_sources[0x3e]	1621	1			T82	1		T34	782		T213	5
valid_sources[0x3f]	767	1			T20	1		T89	1		T10	2
valid_sources[0x40]	833	1			T20	1		T82	2		T91	1
valid_sources[0x41]	793	1			T20	1		T82	7		T68	5
valid_sources[0x42]	1086	1			T80	2		T81	7		T90	1
valid_sources[0x43]	1166	1			T28	1		T81	1		T82	2
valid_sources[0x44]	1007	1			T28	4		T68	1		T289	2
valid_sources[0x45]	1184	1			T90	1		T213	2		T35	5
valid_sources[0x46]	914	1			T28	7		T82	1		T68	11
valid_sources[0x47]	1353	1			T20	1		T22	2		T29	1
valid_sources[0x48]	985	1			T22	1		T81	2		T213	1
valid_sources[0x49]	835	1			T35	6		T48	1		T289	2
valid_sources[0x4a]	1048	1			T22	2		T90	4		T8	2
valid_sources[0x4b]	759	1			T89	1		T90	1		T213	1
valid_sources[0x4c]	886	1			T67	1		T68	3		T12	7
valid_sources[0x4d]	825	1			T4	44		T81	9		T82	2
valid_sources[0x4e]	913	1			T20	1		T81	2		T89	1
valid_sources[0x4f]	872	1			T20	1		T28	6		T89	3
valid_sources[0x50]	865	1			T12	146		T213	1		T289	1
valid_sources[0x51]	657	1			T18	1		T20	1		T81	1
valid_sources[0x52]	744	1			T20	1		T89	1		T90	2
valid_sources[0x53]	910	1			T80	1		T89	1		T8	12
valid_sources[0x54]	954	1			T89	1		T68	3		T213	4
valid_sources[0x55]	802	1			T81	2		T82	1		T67	1
valid_sources[0x56]	845	1			T89	3		T213	1		T289	2
valid_sources[0x57]	649	1			T81	7		T68	1		T213	1
valid_sources[0x58]	827	1			T21	2		T29	1		T89	1
valid_sources[0x59]	821	1			T82	2		T89	1		T10	1
valid_sources[0x5a]	952	1			T20	1		T82	3		T289	2
valid_sources[0x5b]	922	1			T5	2		T3	15		T82	1
valid_sources[0x5c]	1023	1			T22	5		T213	7		T289	1
valid_sources[0x5d]	764	1			T21	1		T29	2		T213	3
valid_sources[0x5e]	1198	1			T82	2		T89	1		T213	5
valid_sources[0x5f]	843	1			T67	1		T213	1		T289	1
valid_sources[0x60]	802	1			T89	1		T213	1		T61	1
valid_sources[0x61]	818	1			T18	1		T22	5		T81	2
valid_sources[0x62]	860	1			T22	2		T28	1		T213	4
valid_sources[0x63]	1811	1			T8	2		T67	1		T60	1
valid_sources[0x64]	879	1			T30	8		T8	1		T213	2
valid_sources[0x65]	985	1			T23	52		T82	1		T89	1
valid_sources[0x66]	938	1			T9	1		T289	3		T282	5
valid_sources[0x67]	1258	1			T67	1		T12	20		T213	1
valid_sources[0x68]	812	1			T28	6		T67	1		T213	2
valid_sources[0x69]	902	1			T82	4		T90	1		T289	3
valid_sources[0x6a]	896	1			T67	1		T68	1		T289	2
valid_sources[0x6b]	723	1			T20	2		T21	1		T81	3
valid_sources[0x6c]	1004	1			T28	2		T82	1		T89	1
valid_sources[0x6d]	1011	1			T15	55		T28	2		T90	1
valid_sources[0x6e]	915	1			T20	2		T60	1		T213	2
valid_sources[0x6f]	833	1			T68	1		T12	20		T213	7
valid_sources[0x70]	954	1			T28	2		T81	8		T82	1
valid_sources[0x71]	917	1			T65	5		T68	4		T213	2
valid_sources[0x72]	1030	1			T28	3		T82	1		T67	2
valid_sources[0x73]	901	1			T82	1		T89	2		T213	1
valid_sources[0x74]	909	1			T18	1		T21	1		T89	1
valid_sources[0x75]	866	1			T18	2		T20	1		T9	1
valid_sources[0x76]	847	1			T20	1		T8	1		T213	1
valid_sources[0x77]	937	1			T213	1		T35	1		T289	2
valid_sources[0x78]	812	1			T213	5		T289	2		T284	2
valid_sources[0x79]	896	1			T60	1		T213	2		T289	2
valid_sources[0x7a]	943	1			T82	2		T213	4		T61	1
valid_sources[0x7b]	803	1			T20	1		T29	2		T82	3
valid_sources[0x7c]	823	1			T22	1		T28	3		T89	1
valid_sources[0x7d]	752	1			T20	1		T82	5		T89	1
valid_sources[0x7e]	976	1			T18	1		T77	1		T8	1
valid_sources[0x7f]	824	1			T18	1		T22	1		T28	2
valid_sources[0x80]	996	1			T89	1		T68	2		T213	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

60670

1

T4

10

T6

1

T23

23

values[0x0]

all_enables

biggest_size

30171

1

T4

8

T6

1

T1

2

values[0x1]

all_enables

biggest_size

21680

1

T4

3

T6

2

T1

1