Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.55	93.48	95.45		100.00	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.55	93.48	95.45		100.00	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	95.65	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	95.65	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.70	97.83	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	93.48	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T12 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T12 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T12 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T12 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T12 T35 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T12 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T12 T35 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T12 T35 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T12 T35 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T12 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T12 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T12 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T35 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T12 T56 
191        1/1                      state_d = StableSt;
           Tests:       T3 T12 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T12 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T12 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T12 T56 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T12 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T57 T69 T133 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T12 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T35
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T12,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T56
0	1	Not Covered
1	0	Covered	T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T56
0	1	Covered	T57,T133,T201
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T56
1	-	Covered	T57,T133,T201

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T35
DetectSt	168	Covered	T3,T12,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T35
DebounceSt->IdleSt	163	Covered	T233
DetectSt->IdleSt	186	Covered	T35
DetectSt->StableSt	191	Covered	T3,T12,T56
IdleSt->DebounceSt	148	Covered	T3,T12,T35
StableSt->IdleSt	206	Covered	T12,T57,T69

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T12,T35
0	1	Covered	T3,T12,T35
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T35
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T57,T69,T133
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	50	0	0
CntIncr_A	7811606	56408	0	0
CntNoWrap_A	7811606	7354566	0	0
DetectStDropOut_A	7811606	0	0	0
DetectedOut_A	7811606	127295	0	0
DetectedPulseOut_A	7811606	24	0	0
DisabledIdleSt_A	7811606	7020128	0	0
DisabledNoDetection_A	7811606	7022035	0	0
EnterDebounceSt_A	7811606	26	0	0
EnterDetectSt_A	7811606	25	0	0
EnterStableSt_A	7811606	24	0	0
PulseIsPulse_A	7811606	24	0	0
StayInStableSt	7811606	127257	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	50	0	0
T3	779	2	0	0
T9	506	0	0	0
T12	0	2	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	2	0	0
T49	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T69	0	2	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	4	0	0
T201	0	2	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	56408	0	0
T3	779	88	0	0
T9	506	0	0	0
T12	0	97	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	15	0	0
T49	0	71	0	0
T56	0	13	0	0
T57	0	22	0	0
T69	0	27	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	142	0	0
T201	0	85	0	0
T230	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354566	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	127295	0	0
T3	779	39	0	0
T9	506	0	0	0
T12	0	355	0	0
T30	497	0	0	0
T33	470	0	0	0
T49	0	181	0	0
T56	0	39	0	0
T57	0	54	0	0
T69	0	13	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	203	0	0
T201	0	41	0	0
T204	0	259	0	0
T230	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	24	0	0
T3	779	1	0	0
T9	506	0	0	0
T12	0	1	0	0
T30	497	0	0	0
T33	470	0	0	0
T49	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T204	0	1	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7020128	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7022035	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	26	0	0
T3	779	1	0	0
T9	506	0	0	0
T12	0	1	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	25	0	0
T3	779	1	0	0
T9	506	0	0	0
T12	0	1	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	24	0	0
T3	779	1	0	0
T9	506	0	0	0
T12	0	1	0	0
T30	497	0	0	0
T33	470	0	0	0
T49	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T204	0	1	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	24	0	0
T3	779	1	0	0
T9	506	0	0	0
T12	0	1	0	0
T30	497	0	0	0
T33	470	0	0	0
T49	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T204	0	1	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	127257	0	0
T3	779	37	0	0
T9	506	0	0	0
T12	0	353	0	0
T30	497	0	0	0
T33	470	0	0	0
T49	0	179	0	0
T56	0	37	0	0
T57	0	53	0	0
T69	0	12	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	200	0	0
T201	0	40	0	0
T204	0	257	0	0
T230	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	9	0	0
T43	19871	0	0	0
T57	645	1	0	0
T59	7140	0	0	0
T98	105435	0	0	0
T133	0	1	0	0
T201	0	1	0	0
T212	0	1	0	0
T220	0	1	0	0
T234	0	1	0	0
T235	0	1	0	0
T236	0	2	0	0
T237	420	0	0	0
T238	577	0	0	0
T239	492	0	0	0
T240	402	0	0	0
T241	1847	0	0	0
T242	409	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T7 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T7 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T7 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T7 T35 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T7 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T7 T35 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T7 T35 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T35 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T201 T233 T135 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T35 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T35 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T35 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T56 T99 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T56 T99 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T7 T54 
191        1/1                      state_d = StableSt;
           Tests:       T3 T7 T54 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T7 T54 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T7 T54 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T7 T54 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T7 T54 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T51 T230 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T7 T54 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T4,T5,T23
1	1	Covered	T3,T7,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T54
0	1	Covered	T56,T99,T243
1	0	Covered	T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T54
0	1	Covered	T3,T51,T230
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T54
1	-	Covered	T3,T51,T230

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T35
DetectSt	168	Covered	T3,T7,T35
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T35
DebounceSt->IdleSt	163	Covered	T201,T233,T135
DetectSt->IdleSt	186	Covered	T35,T56,T99
DetectSt->StableSt	191	Covered	T3,T7,T54
IdleSt->DebounceSt	148	Covered	T3,T7,T35
StableSt->IdleSt	206	Covered	T3,T51,T230

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T35
0	1	Covered	T3,T7,T35
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T35
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T201,T233,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T56,T99
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T51,T230
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	116	0	0
CntIncr_A	7811606	227996	0	0
CntNoWrap_A	7811606	7354500	0	0
DetectStDropOut_A	7811606	3	0	0
DetectedOut_A	7811606	68053	0	0
DetectedPulseOut_A	7811606	52	0	0
DisabledIdleSt_A	7811606	6657954	0	0
DisabledNoDetection_A	7811606	6659850	0	0
EnterDebounceSt_A	7811606	60	0	0
EnterDetectSt_A	7811606	56	0	0
EnterStableSt_A	7811606	52	0	0
PulseIsPulse_A	7811606	52	0	0
StayInStableSt	7811606	67976	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7811606	1819	0	0
gen_low_level_sva.LowLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	116	0	0
T3	779	2	0	0
T7	0	2	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	2	0	0
T51	0	4	0	0
T54	0	2	0	0
T56	0	2	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T99	0	2	0	0
T228	0	2	0	0
T229	0	2	0	0
T230	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	227996	0	0
T3	779	88	0	0
T7	0	91	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	15	0	0
T51	0	146	0	0
T54	0	13	0	0
T56	0	13	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T99	0	87	0	0
T228	0	76	0	0
T229	0	58	0	0
T230	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354500	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	3	0	0
T44	25098	0	0	0
T56	476	1	0	0
T99	0	1	0	0
T181	502	0	0	0
T243	0	1	0	0
T244	421	0	0	0
T245	962	0	0	0
T246	524	0	0	0
T247	433	0	0	0
T248	506	0	0	0
T249	642	0	0	0
T250	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	68053	0	0
T3	779	153	0	0
T7	0	57	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	299	0	0
T54	0	69	0	0
T69	0	14	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	213	0	0
T201	0	399	0	0
T228	0	76	0	0
T229	0	101	0	0
T230	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	52	0	0
T3	779	1	0	0
T7	0	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	2	0	0
T54	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6657954	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6659850	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	60	0	0
T3	779	1	0	0
T7	0	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T99	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	56	0	0
T3	779	1	0	0
T7	0	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T35	0	1	0	0
T51	0	2	0	0
T54	0	1	0	0
T56	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T99	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	52	0	0
T3	779	1	0	0
T7	0	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	2	0	0
T54	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	52	0	0
T3	779	1	0	0
T7	0	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	2	0	0
T54	0	1	0	0
T69	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T201	0	1	0	0
T228	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	67976	0	0
T3	779	152	0	0
T7	0	55	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	296	0	0
T54	0	67	0	0
T69	0	13	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	211	0	0
T201	0	397	0	0
T228	0	74	0	0
T229	0	99	0	0
T230	0	74	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1819	0	0
T1	488	0	0	0
T4	496	5	0	0
T5	424	2	0	0
T6	455	0	0	0
T14	792	4	0	0
T15	502	6	0	0
T16	777	0	0	0
T17	429	2	0	0
T18	407	0	0	0
T20	0	6	0	0
T22	0	6	0	0
T23	455	8	0	0
T29	0	5	0	0
T65	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	26	0	0
T3	779	1	0	0
T9	506	0	0	0
T30	497	0	0	0
T33	470	0	0	0
T51	0	1	0	0
T80	409	0	0	0
T81	502	0	0	0
T82	1405	0	0	0
T83	439	0	0	0
T89	510	0	0	0
T91	404	0	0	0
T133	0	2	0	0
T200	0	1	0	0
T202	0	1	0	0
T212	0	1	0	0
T230	0	1	0	0
T251	0	1	0	0
T252	0	1	0	0
T253	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T12 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T12 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T12 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T12 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T12 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T12 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T12 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T12 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T48 T55 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T7 T48 T212 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T48 T55 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T48 T55 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T48 T55 
186        1/1                    state_d = IdleSt;
           Tests:       T53 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T53 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T48 T55 
191        1/1                      state_d = StableSt;
           Tests:       T12 T48 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T48 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T48 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T48 T55 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T48 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T53 T69 T254 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T48 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T48,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T4,T5,T23
1	1	Covered	T7,T12,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T48,T55
0	1	Covered	T53
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T48,T55
0	1	Covered	T53,T254,T232
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T48,T55
1	-	Covered	T53,T254,T232

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T12,T35
DetectSt	168	Covered	T12,T48,T55
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T48,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T48,T55
DebounceSt->IdleSt	163	Covered	T7,T35,T48
DetectSt->IdleSt	186	Covered	T53
DetectSt->StableSt	191	Covered	T12,T48,T55
IdleSt->DebounceSt	148	Covered	T7,T12,T35
StableSt->IdleSt	206	Covered	T12,T53,T69

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T12,T35
0	1	Covered	T7,T12,T35
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T48,T55
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T12,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T35
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T48,T55
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T48,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T12,T35
DetectSt	-	-	-	-	1	-	-	Covered	T53
DetectSt	-	-	-	-	0	1	-	Covered	T12,T48,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T69,T254
StableSt	-	-	-	-	-	-	0	Covered	T12,T48,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	71	0	0
CntIncr_A	7811606	178808	0	0
CntNoWrap_A	7811606	7354545	0	0
DetectStDropOut_A	7811606	1	0	0
DetectedOut_A	7811606	68201	0	0
DetectedPulseOut_A	7811606	32	0	0
DisabledIdleSt_A	7811606	6667626	0	0
DisabledNoDetection_A	7811606	6669533	0	0
EnterDebounceSt_A	7811606	38	0	0
EnterDetectSt_A	7811606	33	0	0
EnterStableSt_A	7811606	32	0	0
PulseIsPulse_A	7811606	32	0	0
StayInStableSt	7811606	68150	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	71	0	0
T7	592	1	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T12	0	2	0	0
T34	6682	0	0	0
T35	0	1	0	0
T48	0	3	0	0
T53	0	4	0	0
T55	0	2	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	2	0	0
T74	439	0	0	0
T75	526	0	0	0
T133	0	2	0	0
T202	0	2	0	0
T243	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	178808	0	0
T7	592	91	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T12	0	77	0	0
T34	6682	0	0	0
T35	0	14	0	0
T48	0	40	0	0
T53	0	86	0	0
T55	0	35	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	27	0	0
T74	439	0	0	0
T75	526	0	0	0
T133	0	71	0	0
T202	0	43	0	0
T243	0	57	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354545	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1	0	0
T53	669	1	0	0
T56	476	0	0	0
T178	522	0	0	0
T179	403	0	0	0
T180	491	0	0	0
T181	502	0	0	0
T244	421	0	0	0
T245	962	0	0	0
T246	524	0	0	0
T247	433	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	68201	0	0
T12	8691	45	0	0
T13	772	0	0	0
T48	0	71	0	0
T50	702	0	0	0
T53	0	1	0	0
T55	0	60	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	14	0	0
T92	461	0	0	0
T133	0	632	0	0
T202	0	202	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	42	0	0
T251	0	181	0	0
T255	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	32	0	0
T12	8691	1	0	0
T13	772	0	0	0
T48	0	1	0	0
T50	702	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T133	0	1	0	0
T202	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	1	0	0
T251	0	1	0	0
T255	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6667626	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6669533	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	38	0	0
T7	592	1	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T12	0	1	0	0
T34	6682	0	0	0
T35	0	1	0	0
T48	0	2	0	0
T53	0	2	0	0
T55	0	1	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	1	0	0
T74	439	0	0	0
T75	526	0	0	0
T133	0	1	0	0
T202	0	1	0	0
T243	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	33	0	0
T12	8691	1	0	0
T13	772	0	0	0
T48	0	1	0	0
T50	702	0	0	0
T53	0	2	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T133	0	1	0	0
T202	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	1	0	0
T251	0	1	0	0
T255	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	32	0	0
T12	8691	1	0	0
T13	772	0	0	0
T48	0	1	0	0
T50	702	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T133	0	1	0	0
T202	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	1	0	0
T251	0	1	0	0
T255	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	32	0	0
T12	8691	1	0	0
T13	772	0	0	0
T48	0	1	0	0
T50	702	0	0	0
T53	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T133	0	1	0	0
T202	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	1	0	0
T251	0	1	0	0
T255	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	68150	0	0
T12	8691	43	0	0
T13	772	0	0	0
T48	0	69	0	0
T50	702	0	0	0
T55	0	58	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	13	0	0
T92	461	0	0	0
T133	0	630	0	0
T202	0	200	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T243	0	40	0	0
T251	0	179	0	0
T254	0	40	0	0
T255	0	57	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	12	0	0
T53	669	1	0	0
T56	476	0	0	0
T178	522	0	0	0
T179	403	0	0	0
T180	491	0	0	0
T181	502	0	0	0
T218	0	2	0	0
T227	0	1	0	0
T232	0	1	0	0
T235	0	2	0	0
T244	421	0	0	0
T245	962	0	0	0
T246	524	0	0	0
T247	433	0	0	0
T253	0	1	0	0
T254	0	1	0	0
T256	0	1	0	0
T257	0	1	0	0
T258	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T35 T52 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T35 T52 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T35 T52 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T35 T52 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T35 T52 
163        1/1                    state_d = IdleSt;
           Tests:       T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T35 T52 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T52 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T52 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T52 T53 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T52 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T52 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T52 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T52 T53 
191        1/1                      state_d = StableSt;
           Tests:       T12 T52 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T52 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T52 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T52 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T52 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T12 T52 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T52 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T35,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T35,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T50,T35
1	0	Covered	T4,T5,T23
1	1	Covered	T12,T35,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T52,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T52,T53
0	1	Covered	T12,T52,T53
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T52,T53
1	-	Covered	T12,T52,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T35,T52
DetectSt	168	Covered	T12,T52,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T52,T53
DebounceSt->IdleSt	163	Covered	T35
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T52,T53
IdleSt->DebounceSt	148	Covered	T12,T35,T52
StableSt->IdleSt	206	Covered	T12,T52,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T35,T52
0	1	Covered	T12,T35,T52
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T52,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T35,T52
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T52,T53
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T35,T52
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T52,T53
StableSt	-	-	-	-	-	-	0	Covered	T12,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	57	0	0
CntIncr_A	7811606	117096	0	0
CntNoWrap_A	7811606	7354559	0	0
DetectStDropOut_A	7811606	0	0	0
DetectedOut_A	7811606	278370	0	0
DetectedPulseOut_A	7811606	28	0	0
DisabledIdleSt_A	7811606	6563473	0	0
DisabledNoDetection_A	7811606	6565380	0	0
EnterDebounceSt_A	7811606	29	0	0
EnterDetectSt_A	7811606	28	0	0
EnterStableSt_A	7811606	28	0	0
PulseIsPulse_A	7811606	28	0	0
StayInStableSt	7811606	278327	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7811606	5482	0	0
gen_low_level_sva.LowLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	57	0	0
T12	8691	2	0	0
T13	772	0	0	0
T35	0	1	0	0
T50	702	0	0	0
T52	0	2	0	0
T53	0	4	0	0
T56	0	2	0	0
T57	0	4	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	2	0	0
T92	461	0	0	0
T212	0	2	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	2	0	0
T254	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	117096	0	0
T12	8691	97	0	0
T13	772	0	0	0
T35	0	14	0	0
T50	702	0	0	0
T52	0	98	0	0
T53	0	86	0	0
T56	0	13	0	0
T57	0	44	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	27	0	0
T92	461	0	0	0
T212	0	54854	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	37	0	0
T254	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354559	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	278370	0	0
T12	8691	67	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	70	0	0
T53	0	83	0	0
T56	0	39	0	0
T57	0	83	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	15	0	0
T92	461	0	0	0
T212	0	235032	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	79	0	0
T232	0	41	0	0
T254	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	28	0	0
T12	8691	1	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T212	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	1	0	0
T232	0	1	0	0
T254	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6563473	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6565380	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	29	0	0
T12	8691	1	0	0
T13	772	0	0	0
T35	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T212	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	1	0	0
T254	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	28	0	0
T12	8691	1	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T212	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	1	0	0
T232	0	1	0	0
T254	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	28	0	0
T12	8691	1	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T212	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	1	0	0
T232	0	1	0	0
T254	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	28	0	0
T12	8691	1	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T212	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	1	0	0
T232	0	1	0	0
T254	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	278327	0	0
T12	8691	66	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	69	0	0
T53	0	80	0	0
T56	0	37	0	0
T57	0	80	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	14	0	0
T92	461	0	0	0
T212	0	235030	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T231	0	78	0	0
T232	0	39	0	0
T254	0	125	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	5482	0	0
T1	488	0	0	0
T4	496	9	0	0
T5	424	1	0	0
T6	455	0	0	0
T14	792	0	0	0
T15	502	4	0	0
T16	777	0	0	0
T17	429	4	0	0
T18	407	0	0	0
T20	0	5	0	0
T22	0	7	0	0
T23	455	6	0	0
T28	0	15	0	0
T29	0	8	0	0
T81	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	12	0	0
T12	8691	1	0	0
T13	772	0	0	0
T50	702	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T92	461	0	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T218	0	1	0	0
T220	0	1	0	0
T231	0	1	0	0
T235	0	1	0	0
T253	0	1	0	0
T259	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T12 T35 T55 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T12 T35 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T12 T35 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T12 T35 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T12 T35 T55 
163        1/1                    state_d = IdleSt;
           Tests:       T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T12 T35 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T55 T54 
167        1/1                    if (trigger_active) begin
           Tests:       T12 T55 T54 
168        1/1                      state_d = DetectSt;
           Tests:       T12 T55 T54 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T12 T55 T54 
182        1/1                  cnt_en = 1'b1;
           Tests:       T12 T55 T54 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T12 T55 T54 
186        1/1                    state_d = IdleSt;
           Tests:       T229 T232 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T229 T232 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T12 T55 T54 
191        1/1                      state_d = StableSt;
           Tests:       T12 T55 T54 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T12 T55 T54 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T12 T55 T54 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T12 T55 T54 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T12 T55 T54 
206        1/1                    state_d = IdleSt;
           Tests:       T54 T52 T69 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T12 T55 T54 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T35,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T35,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T55,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T35,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T12,T35,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T55,T54
0	1	Covered	T229,T232
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T55,T54
0	1	Covered	T54,T52,T201
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T55,T54
1	-	Covered	T54,T52,T201

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T35,T55
DetectSt	168	Covered	T12,T55,T54
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T55,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T55,T54
DebounceSt->IdleSt	163	Covered	T35
DetectSt->IdleSt	186	Covered	T229,T232
DetectSt->StableSt	191	Covered	T12,T55,T54
IdleSt->DebounceSt	148	Covered	T12,T35,T55
StableSt->IdleSt	206	Covered	T12,T54,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T35,T55
0	1	Covered	T12,T35,T55
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T55,T54
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T35,T55
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T55,T54
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T35,T55
DetectSt	-	-	-	-	1	-	-	Covered	T229,T232
DetectSt	-	-	-	-	0	1	-	Covered	T12,T55,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T54,T52,T69
StableSt	-	-	-	-	-	-	0	Covered	T12,T55,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	91	0	0
CntIncr_A	7811606	154434	0	0
CntNoWrap_A	7811606	7354525	0	0
DetectStDropOut_A	7811606	2	0	0
DetectedOut_A	7811606	196595	0	0
DetectedPulseOut_A	7811606	43	0	0
DisabledIdleSt_A	7811606	6882221	0	0
DisabledNoDetection_A	7811606	6884126	0	0
EnterDebounceSt_A	7811606	46	0	0
EnterDetectSt_A	7811606	45	0	0
EnterStableSt_A	7811606	43	0	0
PulseIsPulse_A	7811606	43	0	0
StayInStableSt	7811606	196533	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	91	0	0
T12	8691	4	0	0
T13	772	0	0	0
T35	0	1	0	0
T49	0	2	0	0
T50	702	0	0	0
T52	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	2	0	0
T92	461	0	0	0
T99	0	2	0	0
T189	0	2	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T229	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	154434	0	0
T12	8691	174	0	0
T13	772	0	0	0
T35	0	15	0	0
T49	0	71	0	0
T50	702	0	0	0
T52	0	98	0	0
T54	0	13	0	0
T55	0	35	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	27	0	0
T92	461	0	0	0
T99	0	87	0	0
T189	0	61	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T229	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354525	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	2	0	0
T229	568	1	0	0
T232	0	1	0	0
T260	584	0	0	0
T261	495	0	0	0
T262	436	0	0	0
T263	502	0	0	0
T264	723	0	0	0
T265	716	0	0	0
T266	490	0	0	0
T267	527	0	0	0
T268	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	196595	0	0
T12	8691	260	0	0
T13	772	0	0	0
T49	0	42	0	0
T50	702	0	0	0
T52	0	43	0	0
T54	0	8	0	0
T55	0	59	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	13	0	0
T92	461	0	0	0
T99	0	46	0	0
T170	0	38	0	0
T189	0	89	0	0
T201	0	85	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	43	0	0
T12	8691	2	0	0
T13	772	0	0	0
T49	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T99	0	1	0	0
T170	0	1	0	0
T189	0	1	0	0
T201	0	2	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6882221	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6884126	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	46	0	0
T12	8691	2	0	0
T13	772	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T99	0	1	0	0
T189	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T229	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	45	0	0
T12	8691	2	0	0
T13	772	0	0	0
T49	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T99	0	1	0	0
T170	0	1	0	0
T189	0	1	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0
T229	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	43	0	0
T12	8691	2	0	0
T13	772	0	0	0
T49	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T99	0	1	0	0
T170	0	1	0	0
T189	0	1	0	0
T201	0	2	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	43	0	0
T12	8691	2	0	0
T13	772	0	0	0
T49	0	1	0	0
T50	702	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	1	0	0
T92	461	0	0	0
T99	0	1	0	0
T170	0	1	0	0
T189	0	1	0	0
T201	0	2	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	196533	0	0
T12	8691	256	0	0
T13	772	0	0	0
T49	0	40	0	0
T50	702	0	0	0
T52	0	42	0	0
T54	0	7	0	0
T55	0	57	0	0
T60	655	0	0	0
T61	832	0	0	0
T69	0	12	0	0
T92	461	0	0	0
T99	0	44	0	0
T170	0	36	0	0
T189	0	87	0	0
T201	0	82	0	0
T213	2976	0	0	0
T214	1444	0	0	0
T215	648	0	0	0
T216	412	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	23	0	0
T52	0	1	0	0
T54	2624	1	0	0
T62	649	0	0	0
T63	639	0	0	0
T86	498	0	0	0
T200	0	1	0	0
T201	0	1	0	0
T204	0	1	0	0
T231	0	1	0	0
T232	0	1	0	0
T254	0	1	0	0
T269	0	1	0	0
T270	0	1	0	0
T271	422	0	0	0
T272	4402	0	0	0
T273	402	0	0	0
T274	407	0	0	0
T275	406	0	0	0
T276	817	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T50 T35 T52 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T50 T35 T52 
149        1/1                    cnt_en = 1'b1;
           Tests:       T50 T35 T52 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T50 T35 T52 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T50 T35 T52 
163        1/1                    state_d = IdleSt;
           Tests:       T35 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 
165        1/1                  end else if (cnt_done) begin
           Tests:       T50 T35 T52 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T50 T52 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T50 T52 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T50 T52 T53 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T50 T52 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T50 T52 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T50 T52 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T50 T52 T53 
191        1/1                      state_d = StableSt;
           Tests:       T50 T52 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T50 T52 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T50 T52 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T50 T52 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T50 T52 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T50 T53 T51 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T50 T52 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T35,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T35,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T50,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T50,T35
1	0	Covered	T4,T6,T23
1	1	Covered	T50,T35,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T50,T52,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T50,T52,T53
0	1	Covered	T50,T53,T51
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T50,T52,T53
1	-	Covered	T50,T53,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T50,T35,T52
DetectSt	168	Covered	T50,T52,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T50,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T50,T52,T53
DebounceSt->IdleSt	163	Covered	T35,T203
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T50,T52,T53
IdleSt->DebounceSt	148	Covered	T50,T35,T52
StableSt->IdleSt	206	Covered	T50,T53,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T50,T35,T52
0	1	Covered	T50,T35,T52
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T50,T52,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T50,T35,T52
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35
DebounceSt	-	0	1	1	-	-	-	Covered	T50,T52,T53
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T50,T35,T52
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T50,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T50,T53,T51
StableSt	-	-	-	-	-	-	0	Covered	T50,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	45	0	0
CntIncr_A	7811606	110859	0	0
CntNoWrap_A	7811606	7354571	0	0
DetectStDropOut_A	7811606	0	0	0
DetectedOut_A	7811606	1188	0	0
DetectedPulseOut_A	7811606	22	0	0
DisabledIdleSt_A	7811606	7021615	0	0
DisabledNoDetection_A	7811606	7023526	0	0
EnterDebounceSt_A	7811606	24	0	0
EnterDetectSt_A	7811606	22	0	0
EnterStableSt_A	7811606	22	0	0
PulseIsPulse_A	7811606	22	0	0
StayInStableSt	7811606	1154	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7811606	5201	0	0
gen_low_level_sva.LowLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	45	0	0
T35	5877	1	0	0
T50	702	2	0	0
T51	0	4	0	0
T52	0	2	0	0
T53	0	2	0	0
T61	832	0	0	0
T69	0	2	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	4	0	0
T216	412	0	0	0
T229	0	2	0	0
T230	0	2	0	0
T255	0	2	0	0
T277	434	0	0	0
T278	427	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	110859	0	0
T35	5877	15	0	0
T50	702	44	0	0
T51	0	146	0	0
T52	0	98	0	0
T53	0	43	0	0
T61	832	0	0	0
T69	0	27	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	109708	0	0
T216	412	0	0	0
T229	0	58	0	0
T230	0	94	0	0
T255	0	21	0	0
T277	434	0	0	0
T278	427	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7354571	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1188	0	0
T35	5877	0	0	0
T50	702	88	0	0
T51	0	85	0	0
T52	0	208	0	0
T53	0	2	0	0
T61	832	0	0	0
T69	0	14	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	83	0	0
T216	412	0	0	0
T229	0	42	0	0
T230	0	38	0	0
T232	0	84	0	0
T255	0	46	0	0
T277	434	0	0	0
T278	427	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	22	0	0
T35	5877	0	0	0
T50	702	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	1	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	2	0	0
T216	412	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T232	0	2	0	0
T255	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7021615	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7023526	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	24	0	0
T35	5877	1	0	0
T50	702	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	1	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	2	0	0
T216	412	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T255	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	22	0	0
T35	5877	0	0	0
T50	702	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	1	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	2	0	0
T216	412	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T232	0	2	0	0
T255	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	22	0	0
T35	5877	0	0	0
T50	702	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	1	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	2	0	0
T216	412	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T232	0	2	0	0
T255	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	22	0	0
T35	5877	0	0	0
T50	702	1	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	1	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	2	0	0
T216	412	0	0	0
T229	0	1	0	0
T230	0	1	0	0
T232	0	2	0	0
T255	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1154	0	0
T35	5877	0	0	0
T50	702	87	0	0
T51	0	82	0	0
T52	0	206	0	0
T53	0	1	0	0
T61	832	0	0	0
T69	0	13	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T212	0	80	0	0
T216	412	0	0	0
T229	0	40	0	0
T230	0	36	0	0
T232	0	81	0	0
T255	0	44	0	0
T277	434	0	0	0
T278	427	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	5201	0	0
T1	488	1	0	0
T4	496	6	0	0
T5	424	0	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	4	0	0
T16	777	0	0	0
T17	429	1	0	0
T18	407	0	0	0
T19	0	1	0	0
T20	0	6	0	0
T21	0	1	0	0
T22	0	6	0	0
T23	455	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	9	0	0
T35	5877	0	0	0
T50	702	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T61	832	0	0	0
T84	503	0	0	0
T93	472	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T200	0	1	0	0
T212	0	1	0	0
T216	412	0	0	0
T219	0	1	0	0
T232	0	1	0	0
T235	0	1	0	0
T253	0	1	0	0
T277	434	0	0	0
T278	427	0	0	0