Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T2 T33 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T6 T2 T33 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T6 T2 T33 
129        1/1              cnt_en = 1'b0;
           Tests:       T6 T2 T33 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T6 T2 T33 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T6 T2 T33 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T6 T2 T33 
139                     
140        1/1              unique case (state_q)
           Tests:       T6 T2 T33 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T6 T2 T33 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T2 T33 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T2 T33 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T2 T33 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T2 T33 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T2 T33 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T2 T33 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T2 T33 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T2 T33 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T69 T129 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T2 T33 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T2 T33 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T2 T33 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T96 T69 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T96 T69 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T2 T33 
191        1/1                      state_d = StableSt;
           Tests:       T6 T2 T33 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T2 T33 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T2 T33 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T2 T33 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T2 T33 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T2 T33 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T2,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T36,T59
1	1	Covered	T6,T2,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T33
0	1	Covered	T35,T96,T69
1	0	Covered	T35,T69,T58

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T2,T33
0	1	Covered	T34,T35,T36
1	0	Covered	T290,T291

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T2,T33
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T2,T33
DetectSt	168	Covered	T6,T2,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T2,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T2,T33
DebounceSt->IdleSt	163	Covered	T35,T69,T129
DetectSt->IdleSt	186	Covered	T35,T96,T69
DetectSt->StableSt	191	Covered	T6,T2,T33
IdleSt->DebounceSt	148	Covered	T6,T2,T33
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T2,T33
0	1	Covered	T6,T2,T33
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T2,T33
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T2,T33
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T2,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T69,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T2,T33
DetectSt	-	-	-	-	1	-	-	Covered	T35,T96,T69
DetectSt	-	-	-	-	0	1	-	Covered	T6,T2,T33
DetectSt	-	-	-	-	0	0	-	Covered	T6,T2,T33
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T2,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	2988	0	0
CntIncr_A	7811606	100674	0	0
CntNoWrap_A	7811606	7351628	0	0
DetectStDropOut_A	7811606	446	0	0
DetectedOut_A	7811606	74566	0	0
DetectedPulseOut_A	7811606	828	0	0
DisabledIdleSt_A	7811606	6875903	0	0
DisabledNoDetection_A	7811606	6877643	0	0
EnterDebounceSt_A	7811606	1501	0	0
EnterDetectSt_A	7811606	1487	0	0
EnterStableSt_A	7811606	828	0	0
PulseIsPulse_A	7811606	828	0	0
StayInStableSt	7811606	73631	0	0
gen_high_event_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	715	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	2988	0	0
T1	488	0	0	0
T2	0	2	0	0
T6	455	2	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	2	0	0
T34	0	56	0	0
T35	0	16	0	0
T36	0	20	0	0
T59	0	46	0	0
T92	0	2	0	0
T93	0	2	0	0
T94	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	100674	0	0
T1	488	0	0	0
T2	0	21	0	0
T6	455	21	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	21	0	0
T34	0	1232	0	0
T35	0	204	0	0
T36	0	970	0	0
T59	0	1104	0	0
T92	0	21	0	0
T93	0	21	0	0
T94	0	208	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7351628	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	52	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	446	0	0
T35	5877	1	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T96	0	8	0	0
T97	0	28	0	0
T100	8418	0	0	0
T132	0	17	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	17	0	0
T142	0	13	0	0
T144	0	26	0	0
T146	0	21	0	0
T147	0	15	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	74566	0	0
T1	488	0	0	0
T2	0	82	0	0
T6	455	29	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	44	0	0
T34	0	1587	0	0
T35	0	286	0	0
T36	0	310	0	0
T59	0	1506	0	0
T92	0	36	0	0
T93	0	46	0	0
T94	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	828	0	0
T1	488	0	0	0
T2	0	1	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	28	0	0
T35	0	5	0	0
T36	0	10	0	0
T59	0	23	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6875903	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	4	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6877643	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	4	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1501	0	0
T1	488	0	0	0
T2	0	1	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	28	0	0
T35	0	9	0	0
T36	0	10	0	0
T59	0	23	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1487	0	0
T1	488	0	0	0
T2	0	1	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	28	0	0
T35	0	7	0	0
T36	0	10	0	0
T59	0	23	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	828	0	0
T1	488	0	0	0
T2	0	1	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	28	0	0
T35	0	5	0	0
T36	0	10	0	0
T59	0	23	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	828	0	0
T1	488	0	0	0
T2	0	1	0	0
T6	455	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	28	0	0
T35	0	5	0	0
T36	0	10	0	0
T59	0	23	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	73631	0	0
T1	488	0	0	0
T2	0	80	0	0
T6	455	27	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T23	455	0	0	0
T33	0	42	0	0
T34	0	1559	0	0
T35	0	281	0	0
T36	0	300	0	0
T59	0	1483	0	0
T92	0	34	0	0
T93	0	44	0	0
T94	0	97	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	715	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	28	0	0
T35	0	5	0	0
T36	0	10	0	0
T47	0	14	0	0
T59	0	23	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	5	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	4	0	0
T95	0	3	0	0
T292	0	25	0	0
T293	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T6 T1 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T1 T19 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T1 T19 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T1 T19 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T1 T19 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T1 T19 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T1 T19 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T1 T19 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T1 T19 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T2 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T6 T19 T21 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T2 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T2 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T2 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T69 T130 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 T130 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T2 T9 
191        1/1                      state_d = StableSt;
           Tests:       T1 T2 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T2 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T2 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T2 T9 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T2 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T2 T9 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T2 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T19

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T19
1	0	Covered	T28,T82,T34
1	1	Covered	T6,T1,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T130,T143,T145
1	0	Covered	T35,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T9
0	1	Covered	T1,T2,T9
1	0	Covered	T35,T69,T131

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T9
1	-	Covered	T1,T2,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T1,T19
DetectSt	168	Covered	T1,T2,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T2,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T9
DebounceSt->IdleSt	163	Covered	T6,T19,T21
DetectSt->IdleSt	186	Covered	T35,T69,T130
DetectSt->StableSt	191	Covered	T1,T2,T9
IdleSt->DebounceSt	148	Covered	T6,T1,T19
StableSt->IdleSt	206	Covered	T1,T2,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T1,T19
0	1	Covered	T6,T1,T19
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T9
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T1,T19
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T19,T21
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T1,T19
DetectSt	-	-	-	-	1	-	-	Covered	T35,T69,T130
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	834	0	0
CntIncr_A	7811606	44147	0	0
CntNoWrap_A	7811606	7353782	0	0
DetectStDropOut_A	7811606	51	0	0
DetectedOut_A	7811606	14614	0	0
DetectedPulseOut_A	7811606	338	0	0
DisabledIdleSt_A	7811606	7009358	0	0
DisabledNoDetection_A	7811606	7010654	0	0
EnterDebounceSt_A	7811606	441	0	0
EnterDetectSt_A	7811606	393	0	0
EnterStableSt_A	7811606	338	0	0
PulseIsPulse_A	7811606	338	0	0
StayInStableSt	7811606	14238	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	834	0	0
T1	488	2	0	0
T2	0	2	0	0
T6	455	1	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	1	0	0
T20	522	0	0	0
T21	0	1	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	44147	0	0
T1	488	25	0	0
T2	0	25	0	0
T6	455	20	0	0
T9	0	25	0	0
T10	0	25	0	0
T12	0	20	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	20	0	0
T20	522	0	0	0
T21	0	20	0	0
T23	455	0	0	0
T33	0	20	0	0
T34	0	225	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7353782	0	0
T1	488	85	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	53	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	51	0	0
T130	15155	6	0	0
T143	0	4	0	0
T145	0	6	0	0
T148	0	7	0	0
T149	0	3	0	0
T150	0	11	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T158	497	0	0	0
T159	535	0	0	0
T160	1029	0	0	0
T161	668	0	0	0
T162	505	0	0	0
T163	653	0	0	0
T164	456	0	0	0
T165	701	0	0	0
T166	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	14614	0	0
T1	488	3	0	0
T2	0	3	0	0
T9	0	3	0	0
T10	0	3	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	461	0	0
T35	0	110	0	0
T37	0	556	0	0
T43	0	253	0	0
T44	0	252	0	0
T167	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	338	0	0
T1	488	1	0	0
T2	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T37	0	6	0	0
T43	0	4	0	0
T44	0	8	0	0
T167	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7009358	0	0
T1	488	4	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	26	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7010654	0	0
T1	488	4	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	26	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	441	0	0
T1	488	1	0	0
T2	0	1	0	0
T6	455	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	1	0	0
T20	522	0	0	0
T21	0	1	0	0
T23	455	0	0	0
T33	0	1	0	0
T34	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	393	0	0
T1	488	1	0	0
T2	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	5	0	0
T35	0	3	0	0
T37	0	6	0	0
T43	0	4	0	0
T44	0	8	0	0
T167	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	338	0	0
T1	488	1	0	0
T2	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T37	0	6	0	0
T43	0	4	0	0
T44	0	8	0	0
T167	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	338	0	0
T1	488	1	0	0
T2	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	5	0	0
T35	0	1	0	0
T37	0	6	0	0
T43	0	4	0	0
T44	0	8	0	0
T167	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	14238	0	0
T1	488	2	0	0
T2	0	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	456	0	0
T35	0	109	0	0
T37	0	550	0	0
T43	0	249	0	0
T44	0	244	0	0
T167	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	297	0	0
T1	488	1	0	0
T2	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	792	0	0	0
T15	502	0	0	0
T16	777	0	0	0
T17	429	0	0	0
T18	407	0	0	0
T19	439	0	0	0
T20	522	0	0	0
T21	445	0	0	0
T22	525	0	0	0
T34	0	5	0	0
T37	0	6	0	0
T43	0	4	0	0
T44	0	8	0	0
T59	0	8	0	0
T167	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T69 T129 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T95 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T95 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T95
1	0	Covered	T34,T35,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T59
0	1	Covered	T35,T36,T59
1	0	Covered	T69,T132

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T59
1	-	Covered	T35,T36,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T35,T69,T129
DetectSt->IdleSt	186	Covered	T34,T35,T95
DetectSt->StableSt	191	Covered	T35,T36,T59
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T69,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T95
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T59
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T59
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	3252	0	0
CntIncr_A	7811606	112007	0	0
CntNoWrap_A	7811606	7351364	0	0
DetectStDropOut_A	7811606	534	0	0
DetectedOut_A	7811606	73651	0	0
DetectedPulseOut_A	7811606	792	0	0
DisabledIdleSt_A	7811606	6876672	0	0
DisabledNoDetection_A	7811606	6878414	0	0
EnterDebounceSt_A	7811606	1637	0	0
EnterDetectSt_A	7811606	1616	0	0
EnterStableSt_A	7811606	792	0	0
PulseIsPulse_A	7811606	792	0	0
StayInStableSt	7811606	72754	0	0
gen_high_event_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	680	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	3252	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	50	0	0
T35	0	16	0	0
T36	0	50	0	0
T58	0	42	0	0
T59	0	52	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	17	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	28	0	0
T95	0	20	0	0
T96	0	48	0	0
T97	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	112007	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	1410	0	0
T35	0	351	0	0
T36	0	2175	0	0
T58	0	1155	0	0
T59	0	1040	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	695	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	980	0	0
T95	0	479	0	0
T96	0	1626	0	0
T97	0	681	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7351364	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	534	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	12	0	0
T35	0	1	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	1	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T95	0	7	0	0
T96	0	24	0	0
T97	0	13	0	0
T141	0	10	0	0
T142	0	5	0	0
T144	0	24	0	0
T293	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	73651	0	0
T35	5877	259	0	0
T36	0	1131	0	0
T58	0	2096	0	0
T59	0	781	0	0
T69	0	409	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	1333	0	0
T100	8418	0	0	0
T132	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	2327	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T294	0	468	0	0
T295	0	827	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	792	0	0
T35	5877	5	0	0
T36	0	25	0	0
T58	0	21	0	0
T59	0	26	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	14	0	0
T100	8418	0	0	0
T132	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	14	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T294	0	5	0	0
T295	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6876672	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6878414	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1637	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	25	0	0
T35	0	9	0	0
T36	0	25	0	0
T58	0	21	0	0
T59	0	26	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	10	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	14	0	0
T95	0	10	0	0
T96	0	24	0	0
T97	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1616	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	25	0	0
T35	0	7	0	0
T36	0	25	0	0
T58	0	21	0	0
T59	0	26	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	7	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	14	0	0
T95	0	10	0	0
T96	0	24	0	0
T97	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	792	0	0
T35	5877	5	0	0
T36	0	25	0	0
T58	0	21	0	0
T59	0	26	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	14	0	0
T100	8418	0	0	0
T132	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	14	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T294	0	5	0	0
T295	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	792	0	0
T35	5877	5	0	0
T36	0	25	0	0
T58	0	21	0	0
T59	0	26	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	14	0	0
T100	8418	0	0	0
T132	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	14	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T294	0	5	0	0
T295	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	72754	0	0
T35	5877	254	0	0
T36	0	1105	0	0
T58	0	2072	0	0
T59	0	755	0	0
T69	0	404	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	1319	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	2306	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T290	0	1290	0	0
T294	0	461	0	0
T295	0	814	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	680	0	0
T35	5877	5	0	0
T36	0	24	0	0
T58	0	18	0	0
T59	0	26	0	0
T69	0	4	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	14	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T147	0	7	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T290	0	27	0	0
T294	0	3	0	0
T295	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T36 T37 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T36 T37 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T36 T37 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T36 T37 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T36 T37 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T36 T37 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T37 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T36 T37 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T36 T37 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T296 T297 T298 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T36 T37 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T36 T37 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T36 T37 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T69 T130 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 T130 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T36 T37 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T37 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T37 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T37 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T37 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T37 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T37 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T37 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T28,T82,T34
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T130,T46,T145
1	0	Covered	T35,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T36,T37,T44
1	0	Covered	T35,T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T36,T37,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T35,T69,T296
DetectSt->IdleSt	186	Covered	T35,T69,T130
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T35,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T296,T297,T298
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T35,T69,T130
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Covered	T35,T36,T37
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	772	0	0
CntIncr_A	7811606	41214	0	0
CntNoWrap_A	7811606	7353844	0	0
DetectStDropOut_A	7811606	39	0	0
DetectedOut_A	7811606	14777	0	0
DetectedPulseOut_A	7811606	323	0	0
DisabledIdleSt_A	7811606	7005949	0	0
DisabledNoDetection_A	7811606	7007276	0	0
EnterDebounceSt_A	7811606	406	0	0
EnterDetectSt_A	7811606	366	0	0
EnterStableSt_A	7811606	323	0	0
PulseIsPulse_A	7811606	323	0	0
StayInStableSt	7811606	14397	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	262	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	772	0	0
T35	5877	8	0	0
T36	0	2	0	0
T37	0	8	0	0
T43	0	10	0	0
T44	0	4	0	0
T45	0	4	0	0
T58	0	6	0	0
T69	0	8	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	12	0	0
T100	8418	0	0	0
T130	0	14	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	41214	0	0
T35	5877	79	0	0
T36	0	72	0	0
T37	0	940	0	0
T43	0	615	0	0
T44	0	290	0	0
T45	0	204	0	0
T58	0	147	0	0
T69	0	262	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	402	0	0
T100	8418	0	0	0
T130	0	620	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7353844	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	39	0	0
T46	0	1	0	0
T130	15155	7	0	0
T145	0	1	0	0
T149	0	5	0	0
T152	0	6	0	0
T158	497	0	0	0
T159	535	0	0	0
T160	1029	0	0	0
T161	668	0	0	0
T162	505	0	0	0
T163	653	0	0	0
T164	456	0	0	0
T165	701	0	0	0
T166	403	0	0	0
T184	0	11	0	0
T299	0	3	0	0
T300	0	4	0	0
T301	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	14777	0	0
T35	5877	111	0	0
T36	0	82	0	0
T37	0	18	0	0
T43	0	400	0	0
T44	0	50	0	0
T45	0	166	0	0
T58	0	247	0	0
T69	0	80	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	282	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	323	0	0
T35	5877	1	0	0
T36	0	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	0	3	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	6	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7005949	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7007276	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	406	0	0
T35	5877	5	0	0
T36	0	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	0	3	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	6	0	0
T100	8418	0	0	0
T130	0	7	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	366	0	0
T35	5877	3	0	0
T36	0	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	0	3	0	0
T69	0	3	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	6	0	0
T100	8418	0	0	0
T130	0	7	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	323	0	0
T35	5877	1	0	0
T36	0	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	0	3	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	6	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	323	0	0
T35	5877	1	0	0
T36	0	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T58	0	3	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	6	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	14397	0	0
T35	5877	110	0	0
T36	0	81	0	0
T37	0	14	0	0
T43	0	395	0	0
T44	0	48	0	0
T45	0	164	0	0
T58	0	244	0	0
T69	0	79	0	0
T78	946	0	0	0
T93	472	0	0	0
T94	0	276	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	262	0	0
T36	12023	1	0	0
T37	0	4	0	0
T43	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T52	915	0	0	0
T58	0	3	0	0
T64	706	0	0	0
T87	488	0	0	0
T88	498	0	0	0
T94	0	6	0	0
T195	4420	0	0	0
T196	1131	0	0	0
T197	441	0	0	0
T198	1022	0	0	0
T199	2219	0	0	0
T296	0	2	0	0
T302	0	2	0	0
T303	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T69 T129 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T94 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T94 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T94
1	0	Covered	T34,T35,T94

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T59
0	1	Covered	T35,T36,T59
1	0	Covered	T35

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T59
1	-	Covered	T35,T36,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T35,T69,T129
DetectSt->IdleSt	186	Covered	T34,T35,T94
DetectSt->StableSt	191	Covered	T35,T36,T59
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T69,T129
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T94
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T59
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T59
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	3099	0	0
CntIncr_A	7811606	101274	0	0
CntNoWrap_A	7811606	7351517	0	0
DetectStDropOut_A	7811606	365	0	0
DetectedOut_A	7811606	96206	0	0
DetectedPulseOut_A	7811606	974	0	0
DisabledIdleSt_A	7811606	6856352	0	0
DisabledNoDetection_A	7811606	6858050	0	0
EnterDebounceSt_A	7811606	1564	0	0
EnterDetectSt_A	7811606	1536	0	0
EnterStableSt_A	7811606	974	0	0
PulseIsPulse_A	7811606	974	0	0
StayInStableSt	7811606	95083	0	0
gen_high_event_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	823	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	3099	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	50	0	0
T35	0	16	0	0
T36	0	18	0	0
T58	0	48	0	0
T59	0	48	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	16	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	52	0	0
T95	0	38	0	0
T96	0	22	0	0
T97	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	101274	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	1410	0	0
T35	0	330	0	0
T36	0	549	0	0
T58	0	1622	0	0
T59	0	1536	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	587	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	1969	0	0
T95	0	912	0	0
T96	0	744	0	0
T97	0	365	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7351517	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	365	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	12	0	0
T35	0	1	0	0
T47	0	4	0	0
T58	0	13	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	1	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	12	0	0
T95	0	16	0	0
T96	0	11	0	0
T97	0	7	0	0
T144	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	96206	0	0
T35	5877	323	0	0
T36	0	786	0	0
T59	0	959	0	0
T69	0	416	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	819	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	2120	0	0
T142	0	1151	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	829	0	0
T293	0	1261	0	0
T304	0	1205	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	974	0	0
T35	5877	5	0	0
T36	0	9	0	0
T59	0	24	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	5	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	8	0	0
T142	0	5	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	10	0	0
T293	0	10	0	0
T304	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6856352	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6858050	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1564	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	25	0	0
T35	0	9	0	0
T36	0	9	0	0
T58	0	24	0	0
T59	0	24	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	9	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	26	0	0
T95	0	19	0	0
T96	0	11	0	0
T97	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	1536	0	0
T8	1715	0	0	0
T10	484	0	0	0
T11	1088	0	0	0
T34	6682	25	0	0
T35	0	7	0	0
T36	0	9	0	0
T58	0	24	0	0
T59	0	24	0	0
T66	423	0	0	0
T67	492	0	0	0
T68	505	0	0	0
T69	0	7	0	0
T74	439	0	0	0
T75	526	0	0	0
T76	403	0	0	0
T94	0	26	0	0
T95	0	19	0	0
T96	0	11	0	0
T97	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	974	0	0
T35	5877	5	0	0
T36	0	9	0	0
T59	0	24	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	5	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	8	0	0
T142	0	5	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	10	0	0
T293	0	10	0	0
T304	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	974	0	0
T35	5877	5	0	0
T36	0	9	0	0
T59	0	24	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	5	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	8	0	0
T142	0	5	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	10	0	0
T293	0	10	0	0
T304	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	95083	0	0
T35	5877	318	0	0
T36	0	776	0	0
T59	0	935	0	0
T69	0	411	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	812	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	2108	0	0
T142	0	1143	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	819	0	0
T293	0	1251	0	0
T304	0	1194	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	823	0	0
T35	5877	4	0	0
T36	0	8	0	0
T59	0	24	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T132	0	3	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	4	0	0
T142	0	2	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	10	0	0
T293	0	10	0	0
T304	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T36 T37 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T1 T19 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T1 T19 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T37 T44 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T37 T44 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T37 T44 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T37 T44 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T69 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T37 T44 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T37 T44 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T37 T44 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T37 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T296 T302 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T37 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T37 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T37 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T69 T130 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T69 T130 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T37 T44 
191        1/1                      state_d = StableSt;
           Tests:       T35 T37 T44 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T37 T44 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T37 T44 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T37 T44 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T37 T44 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T37 T44 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T37 T44 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T37,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T37,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T37,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T28,T82,T34
1	1	Covered	T35,T37,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T37,T44
0	1	Covered	T35,T130,T296
1	0	Covered	T35,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T37,T44
0	1	Covered	T35,T37,T44
1	0	Covered	T69

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T37,T44
1	-	Covered	T35,T37,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T37,T44
DetectSt	168	Covered	T35,T37,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T37,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T37,T44
DebounceSt->IdleSt	163	Covered	T35,T69,T46
DetectSt->IdleSt	186	Covered	T35,T69,T130
DetectSt->StableSt	191	Covered	T35,T37,T44
IdleSt->DebounceSt	148	Covered	T35,T37,T44
StableSt->IdleSt	206	Covered	T35,T37,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T37,T44
0	1	Covered	T35,T37,T44
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T37,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T37,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T69
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T37,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T296,T302
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T37,T44
DetectSt	-	-	-	-	1	-	-	Covered	T35,T69,T130
DetectSt	-	-	-	-	0	1	-	Covered	T35,T37,T44
DetectSt	-	-	-	-	0	0	-	Covered	T35,T37,T44
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T44
StableSt	-	-	-	-	-	-	0	Covered	T35,T37,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7811606	843	0	0
CntIncr_A	7811606	47697	0	0
CntNoWrap_A	7811606	7353773	0	0
DetectStDropOut_A	7811606	30	0	0
DetectedOut_A	7811606	18582	0	0
DetectedPulseOut_A	7811606	365	0	0
DisabledIdleSt_A	7811606	6989148	0	0
DisabledNoDetection_A	7811606	6990445	0	0
EnterDebounceSt_A	7811606	445	0	0
EnterDetectSt_A	7811606	398	0	0
EnterStableSt_A	7811606	365	0	0
PulseIsPulse_A	7811606	365	0	0
StayInStableSt	7811606	18189	0	0
gen_high_level_sva.HighLevelEvent_A	7811606	7356558	0	0
gen_not_sticky_sva.StableStDropOut_A	7811606	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	843	0	0
T35	5877	8	0	0
T37	0	6	0	0
T43	0	8	0	0
T44	0	6	0	0
T45	0	16	0	0
T46	0	5	0	0
T59	0	4	0	0
T69	0	8	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T130	0	8	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	47697	0	0
T35	5877	138	0	0
T37	0	555	0	0
T43	0	444	0	0
T44	0	378	0	0
T45	0	1088	0	0
T46	0	131	0	0
T59	0	106	0	0
T69	0	273	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T130	0	353	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	68	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7353773	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	30	0	0
T35	5877	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T130	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T150	0	3	0	0
T151	0	4	0	0
T154	0	5	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T296	0	2	0	0
T298	0	3	0	0
T305	0	2	0	0
T306	0	4	0	0
T307	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	18582	0	0
T35	5877	111	0	0
T37	0	163	0	0
T43	0	368	0	0
T44	0	132	0	0
T45	0	398	0	0
T46	0	20	0	0
T59	0	166	0	0
T69	0	78	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	214	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	74	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	365	0	0
T35	5877	1	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	2	0	0
T59	0	2	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	4	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6989148	0	0
T1	488	87	0	0
T4	496	95	0	0
T5	424	23	0	0
T6	455	54	0	0
T14	792	391	0	0
T15	502	101	0	0
T16	777	376	0	0
T17	429	28	0	0
T18	407	6	0	0
T23	455	54	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	6990445	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	445	0	0
T35	5877	5	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	3	0	0
T59	0	2	0	0
T69	0	5	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T130	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	398	0	0
T35	5877	3	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	2	0	0
T59	0	2	0	0
T69	0	3	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T130	0	4	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	365	0	0
T35	5877	1	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	2	0	0
T59	0	2	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	4	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	365	0	0
T35	5877	1	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	2	0	0
T59	0	2	0	0
T69	0	1	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	4	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	18189	0	0
T35	5877	110	0	0
T37	0	160	0	0
T43	0	364	0	0
T44	0	129	0	0
T45	0	390	0	0
T46	0	18	0	0
T59	0	164	0	0
T69	0	77	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T141	0	206	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	7356558	0	0
T1	488	88	0	0
T4	496	96	0	0
T5	424	24	0	0
T6	455	55	0	0
T14	792	392	0	0
T15	502	102	0	0
T16	777	377	0	0
T17	429	29	0	0
T18	407	7	0	0
T23	455	55	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7811606	336	0	0
T35	5877	1	0	0
T37	0	3	0	0
T43	0	4	0	0
T44	0	3	0	0
T45	0	8	0	0
T46	0	2	0	0
T59	0	2	0	0
T78	946	0	0	0
T93	472	0	0	0
T100	8418	0	0	0
T138	572	0	0	0
T139	1947	0	0	0
T140	502	0	0	0
T142	0	3	0	0
T155	522	0	0	0
T156	432	0	0	0
T157	445	0	0	0
T292	0	2	0	0
T302	0	13	0	0