Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1226727766	10959	0	0
auto_block_debounce_ctl_rd_A	1226727766	1827	0	0
auto_block_out_ctl_rd_A	1226727766	2137	0	0
com_det_ctl_0_rd_A	1226727766	3836	0	0
com_det_ctl_1_rd_A	1226727766	3751	0	0
com_det_ctl_2_rd_A	1226727766	3837	0	0
com_det_ctl_3_rd_A	1226727766	4056	0	0
com_out_ctl_0_rd_A	1226727766	4104	0	0
com_out_ctl_1_rd_A	1226727766	4273	0	0
com_out_ctl_2_rd_A	1226727766	3948	0	0
com_out_ctl_3_rd_A	1226727766	4210	0	0
com_pre_det_ctl_0_rd_A	1226727766	1552	0	0
com_pre_det_ctl_1_rd_A	1226727766	1500	0	0
com_pre_det_ctl_2_rd_A	1226727766	1454	0	0
com_pre_det_ctl_3_rd_A	1226727766	1518	0	0
com_pre_sel_ctl_0_rd_A	1226727766	4356	0	0
com_pre_sel_ctl_1_rd_A	1226727766	4248	0	0
com_pre_sel_ctl_2_rd_A	1226727766	4363	0	0
com_pre_sel_ctl_3_rd_A	1226727766	4416	0	0
com_sel_ctl_0_rd_A	1226727766	4329	0	0
com_sel_ctl_1_rd_A	1226727766	4430	0	0
com_sel_ctl_2_rd_A	1226727766	4211	0	0
com_sel_ctl_3_rd_A	1226727766	4344	0	0
ec_rst_ctl_rd_A	1226727766	2347	0	0
intr_enable_rd_A	1226727766	2079	0	0
key_intr_ctl_rd_A	1226727766	3242	0	0
key_intr_debounce_ctl_rd_A	1226727766	1527	0	0
key_invert_ctl_rd_A	1226727766	3879	0	0
pin_allowed_ctl_rd_A	1226727766	4595	0	0
pin_out_ctl_rd_A	1226727766	3249	0	0
pin_out_value_rd_A	1226727766	3245	0	0
regwen_rd_A	1226727766	1739	0	0
ulp_ac_debounce_ctl_rd_A	1226727766	1605	0	0
ulp_ctl_rd_A	1226727766	1612	0	0
ulp_lid_debounce_ctl_rd_A	1226727766	1687	0	0
ulp_pwrb_debounce_ctl_rd_A	1226727766	1491	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	10959	0	0
T7	23678	0	0	0
T12	0	8	0	0
T33	47086	0	0	0
T34	735021	0	0	0
T77	51384	0	0	0
T82	337286	12	0	0
T83	54981	0	0	0
T89	28057	0	0	0
T90	130994	0	0	0
T91	98953	0	0	0
T139	0	4	0	0
T196	0	10	0	0
T199	0	1	0	0
T213	0	8	0	0
T289	0	24	0	0
T315	0	6	0	0
T316	0	7	0	0
T317	0	3	0	0
T318	194323	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1827	0	0
T12	0	22	0	0
T16	194595	5	0	0
T17	32200	0	0	0
T18	50958	0	0	0
T19	211306	0	0	0
T20	261056	0	0	0
T21	111144	0	0	0
T22	63048	0	0	0
T28	175637	0	0	0
T29	113251	0	0	0
T32	0	9	0	0
T61	0	4	0	0
T65	35463	0	0	0
T169	0	20	0	0
T199	0	23	0	0
T213	0	41	0	0
T316	0	43	0	0
T317	0	24	0	0
T319	0	9	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	2137	0	0
T12	0	31	0	0
T16	194595	2	0	0
T17	32200	0	0	0
T18	50958	0	0	0
T19	211306	0	0	0
T20	261056	0	0	0
T21	111144	0	0	0
T22	63048	0	0	0
T28	175637	0	0	0
T29	113251	0	0	0
T32	0	11	0	0
T61	0	3	0	0
T65	35463	0	0	0
T169	0	8	0	0
T199	0	12	0	0
T213	0	41	0	0
T316	0	36	0	0
T317	0	24	0	0
T319	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3836	0	0
T12	410714	20	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	39	0	0
T199	0	14	0	0
T213	357101	50	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	72	0	0
T316	0	29	0	0
T317	0	34	0	0
T320	0	32	0	0
T321	0	19	0	0
T322	0	17	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3751	0	0
T12	410714	50	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	53	0	0
T199	0	20	0	0
T213	357101	31	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	79	0	0
T316	0	22	0	0
T317	0	14	0	0
T320	0	41	0	0
T321	0	31	0	0
T322	0	16	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3837	0	0
T12	410714	23	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	81	0	0
T199	0	3	0	0
T213	357101	43	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	54	0	0
T316	0	30	0	0
T317	0	26	0	0
T320	0	54	0	0
T321	0	15	0	0
T322	0	37	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4056	0	0
T12	410714	33	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	70	0	0
T199	0	28	0	0
T213	357101	32	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	78	0	0
T316	0	37	0	0
T317	0	22	0	0
T320	0	62	0	0
T321	0	21	0	0
T322	0	19	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4104	0	0
T12	410714	29	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	59	0	0
T199	0	23	0	0
T213	357101	30	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	74	0	0
T316	0	11	0	0
T317	0	11	0	0
T320	0	33	0	0
T321	0	13	0	0
T322	0	25	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4273	0	0
T12	410714	37	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	73	0	0
T199	0	17	0	0
T213	357101	40	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	77	0	0
T316	0	30	0	0
T317	0	19	0	0
T320	0	38	0	0
T321	0	31	0	0
T322	0	4	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3948	0	0
T12	410714	28	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	66	0	0
T199	0	7	0	0
T213	357101	61	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	70	0	0
T316	0	17	0	0
T317	0	19	0	0
T320	0	31	0	0
T321	0	12	0	0
T322	0	19	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4210	0	0
T12	410714	34	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	57	0	0
T199	0	17	0	0
T213	357101	37	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	71	0	0
T316	0	28	0	0
T317	0	11	0	0
T320	0	48	0	0
T321	0	24	0	0
T322	0	14	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1552	0	0
T12	410714	39	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	18	0	0
T213	357101	26	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	18	0	0
T316	0	27	0	0
T317	0	25	0	0
T320	0	61	0	0
T321	0	15	0	0
T322	0	38	0	0
T323	0	27	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1500	0	0
T12	410714	44	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	35	0	0
T213	357101	31	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	27	0	0
T316	0	23	0	0
T317	0	23	0	0
T320	0	22	0	0
T321	0	23	0	0
T322	0	17	0	0
T323	0	18	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1454	0	0
T12	410714	16	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	23	0	0
T213	357101	38	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	29	0	0
T316	0	23	0	0
T317	0	26	0	0
T320	0	39	0	0
T321	0	24	0	0
T322	0	15	0	0
T323	0	13	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1518	0	0
T12	410714	31	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	13	0	0
T213	357101	52	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	35	0	0
T316	0	43	0	0
T317	0	17	0	0
T320	0	36	0	0
T321	0	3	0	0
T322	0	37	0	0
T323	0	12	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4356	0	0
T12	410714	26	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	50	0	0
T199	0	26	0	0
T213	357101	56	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	68	0	0
T316	0	22	0	0
T317	0	30	0	0
T320	0	43	0	0
T321	0	20	0	0
T322	0	17	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4248	0	0
T12	410714	26	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	80	0	0
T199	0	13	0	0
T213	357101	27	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	73	0	0
T316	0	36	0	0
T317	0	23	0	0
T320	0	37	0	0
T321	0	15	0	0
T322	0	21	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4363	0	0
T12	410714	38	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	77	0	0
T199	0	12	0	0
T213	357101	38	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	83	0	0
T316	0	33	0	0
T317	0	29	0	0
T320	0	54	0	0
T321	0	13	0	0
T322	0	10	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4416	0	0
T12	410714	12	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	65	0	0
T199	0	24	0	0
T213	357101	32	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	73	0	0
T316	0	27	0	0
T317	0	14	0	0
T320	0	51	0	0
T321	0	18	0	0
T322	0	19	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4329	0	0
T12	410714	34	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	87	0	0
T199	0	23	0	0
T213	357101	24	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	79	0	0
T316	0	30	0	0
T317	0	22	0	0
T320	0	46	0	0
T321	0	13	0	0
T322	0	17	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4430	0	0
T12	410714	42	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	81	0	0
T199	0	25	0	0
T213	357101	39	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	79	0	0
T316	0	18	0	0
T317	0	19	0	0
T320	0	35	0	0
T321	0	19	0	0
T322	0	22	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4211	0	0
T12	410714	32	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	69	0	0
T199	0	19	0	0
T213	357101	38	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	80	0	0
T316	0	6	0	0
T317	0	10	0	0
T320	0	51	0	0
T321	0	35	0	0
T322	0	10	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4344	0	0
T12	410714	33	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T142	0	75	0	0
T199	0	16	0	0
T213	357101	42	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T296	0	65	0	0
T316	0	30	0	0
T317	0	32	0	0
T320	0	27	0	0
T321	0	10	0	0
T322	0	13	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	2347	0	0
T12	410714	24	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T96	0	6	0	0
T198	0	2	0	0
T199	0	13	0	0
T213	357101	63	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T238	0	3	0	0
T245	0	1	0	0
T316	0	24	0	0
T317	0	11	0	0
T324	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	2079	0	0
T12	410714	22	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	26	0	0
T213	357101	52	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T316	0	27	0	0
T317	0	25	0	0
T320	0	37	0	0
T321	0	29	0	0
T322	0	31	0	0
T323	0	27	0	0
T325	0	27	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3242	0	0
T3	374218	7	0	0
T9	15197	0	0	0
T12	0	43	0	0
T30	62131	0	0	0
T33	47086	0	0	0
T57	0	1	0	0
T80	196791	0	0	0
T81	118182	0	0	0
T82	337286	0	0	0
T83	54981	0	0	0
T89	28057	0	0	0
T91	98953	0	0	0
T199	0	27	0	0
T213	0	44	0	0
T230	0	2	0	0
T231	0	8	0	0
T316	0	10	0	0
T317	0	15	0	0
T320	0	38	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1527	0	0
T12	410714	33	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	16	0	0
T213	357101	60	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	17	0	0
T316	0	27	0	0
T317	0	23	0	0
T320	0	45	0	0
T321	0	15	0	0
T322	0	28	0	0
T323	0	14	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3879	0	0
T11	219320	0	0	0
T12	410714	13	0	0
T32	373680	0	0	0
T60	180167	0	0	0
T67	108335	31	0	0
T68	50482	0	0	0
T74	131848	0	0	0
T75	63172	0	0	0
T76	197645	0	0	0
T87	0	36	0	0
T88	0	57	0	0
T167	0	66	0	0
T199	0	17	0	0
T213	357101	41	0	0
T316	0	31	0	0
T317	0	24	0	0
T326	0	48	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	4595	0	0
T12	410714	195	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T181	0	64	0	0
T199	0	13	0	0
T213	357101	87	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T263	0	71	0	0
T316	0	20	0	0
T317	0	14	0	0
T327	0	83	0	0
T328	0	62	0	0
T329	0	43	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3249	0	0
T12	410714	138	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T181	0	68	0	0
T199	0	30	0	0
T213	357101	65	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T263	0	72	0	0
T316	0	18	0	0
T317	0	23	0	0
T327	0	81	0	0
T328	0	44	0	0
T329	0	82	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	3245	0	0
T12	410714	173	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T181	0	75	0	0
T199	0	8	0	0
T213	357101	77	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T263	0	65	0	0
T316	0	16	0	0
T317	0	19	0	0
T327	0	42	0	0
T328	0	85	0	0
T329	0	59	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1739	0	0
T12	410714	42	0	0
T13	58331	0	0	0
T50	71616	0	0	0
T60	180167	0	0	0
T61	99893	0	0	0
T92	221720	0	0	0
T199	0	26	0	0
T213	357101	42	0	0
T214	693400	0	0	0
T215	71402	0	0	0
T216	24746	0	0	0
T233	0	27	0	0
T316	0	26	0	0
T317	0	21	0	0
T320	0	23	0	0
T321	0	18	0	0
T322	0	19	0	0
T323	0	24	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1605	0	0
T8	132162	8	0	0
T10	55652	0	0	0
T11	219320	13	0	0
T12	0	30	0	0
T13	0	3	0	0
T32	373680	0	0	0
T66	105753	0	0	0
T67	108335	0	0	0
T68	50482	0	0	0
T72	0	12	0	0
T74	131848	0	0	0
T75	63172	0	0	0
T76	197645	0	0	0
T79	0	12	0	0
T199	0	17	0	0
T213	0	35	0	0
T316	0	27	0	0
T330	0	15	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1612	0	0
T8	132162	6	0	0
T10	55652	0	0	0
T11	219320	2	0	0
T12	0	18	0	0
T13	0	6	0	0
T32	373680	0	0	0
T66	105753	0	0	0
T67	108335	0	0	0
T68	50482	0	0	0
T72	0	7	0	0
T74	131848	0	0	0
T75	63172	0	0	0
T76	197645	0	0	0
T79	0	17	0	0
T199	0	21	0	0
T213	0	51	0	0
T316	0	18	0	0
T330	0	11	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1687	0	0
T8	132162	2	0	0
T10	55652	0	0	0
T11	219320	8	0	0
T12	0	24	0	0
T13	0	6	0	0
T32	373680	0	0	0
T66	105753	0	0	0
T67	108335	0	0	0
T68	50482	0	0	0
T72	0	10	0	0
T74	131848	0	0	0
T75	63172	0	0	0
T76	197645	0	0	0
T79	0	5	0	0
T199	0	23	0	0
T213	0	41	0	0
T316	0	28	0	0
T330	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1226727766	1491	0	0
T8	132162	2	0	0
T10	55652	0	0	0
T11	219320	7	0	0
T12	0	21	0	0
T13	0	5	0	0
T32	373680	0	0	0
T66	105753	0	0	0
T67	108335	0	0	0
T68	50482	0	0	0
T72	0	4	0	0
T74	131848	0	0	0
T75	63172	0	0	0
T76	197645	0	0	0
T79	0	8	0	0
T199	0	10	0	0
T213	0	43	0	0
T316	0	16	0	0
T330	0	1	0	0