Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.19 100.00 97.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_sysrst_ctrl_combo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00

33 logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse; 34 1/1 assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i; Tests: T1 T2 T9  35 1/1 assign combo_ec_rst_pulse = cfg_ec_rst_en_i & combo_det_pulse_i; Tests: T6 T1 T19  36 1/1 assign combo_ot_pulse = cfg_rst_req_en_i & combo_det_pulse_i; Tests: T1 T2 T9  37 1/1 assign combo_intr_pulse_o = cfg_intr_en_i & combo_det_pulse_i; Tests: T6 T1 T19  38 39 //ec_rst_l_i high->low detection 40 logic ec_rst_l_det_pulse, ec_rst_l_det_q; 41 1/1 assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q; Tests: T4 T5 T6  42 43 //////////////////////////////////// 44 // Bat / OT reset pulse latching // 45 //////////////////////////////////// 46 47 logic bat_disable_q, bat_disable_d; 48 1/1 assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse; Tests: T44 T43 T58  49 1/1 assign bat_disable_o = bat_disable_q; Tests: T44 T43 T58  50 51 logic rst_req_q, rst_req_d; 52 1/1 assign rst_req_d = rst_req_q | combo_ot_pulse; Tests: T36 T44 T43  53 1/1 assign rst_req_o = rst_req_q; Tests: T36 T44 T43  54 55 //////////////////// 56 // EC reset logic // 57 //////////////////// 58 59 // OT reset will also reset EC 60 logic timer_expired; 61 logic ec_rst_l_q, ec_rst_l_d; 62 1/1 assign ec_rst_l_o = ec_rst_l_q; Tests: T6 T1 T14  63 1/1 assign ec_rst_l_d = (combo_ec_rst_pulse || Tests: T4 T5 T6  64 ec_rst_l_det_pulse) ? 1'b0 : 65 (timer_expired) ? 1'b1 : ec_rst_l_q; 66 67 68 // Reset stretching counter 69 logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q; 70 1/1 assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q); Tests: T4 T5 T6  71 1/1 assign timer_cnt_d = (timer_expired) ? '0 : Tests: T4 T5 T6  72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; 73 74 /////////////// 75 // Registers // 76 /////////////// 77 78 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 79 1/1 if (!rst_ni) begin Tests: T4 T5 T6  80 1/1 bat_disable_q <= 1'b0; Tests: T4 T5 T6  81 1/1 ec_rst_l_det_q <= 1'b1; // active low signal Tests: T4 T5 T6  82 1/1 rst_req_q <= 1'b0; Tests: T4 T5 T6  83 1/1 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted Tests: T4 T5 T6  84 1/1 timer_cnt_q <= '0; Tests: T4 T5 T6  85 end else begin 86 1/1 bat_disable_q <= bat_disable_d; Tests: T4 T5 T6  87 1/1 ec_rst_l_det_q <= ec_rst_l_i; Tests: T4 T5 T6  88 1/1 rst_req_q <= rst_req_d; Tests: T4 T5 T6  89 1/1 ec_rst_l_q <= ec_rst_l_d; Tests: T4 T5 T6  90 1/1 timer_cnt_q <= timer_cnt_d; Tests: T4 T5 T6 

Cond Coverage for Module : sysrst_ctrl_comboact
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T9
10CoveredT34,T36,T44
11CoveredT44,T43,T58

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT34,T36,T37
10CoveredT6,T1,T19
11CoveredT1,T2,T9

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T9
10CoveredT36,T44,T43
11CoveredT36,T44,T43

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT34,T35,T37
10CoveredT6,T1,T19
11CoveredT1,T2,T9

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T43,T58
10CoveredT44,T43,T58

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T44,T43
10CoveredT36,T44,T43

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T9

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT6,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

Branch Coverage for Module : sysrst_ctrl_comboact
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00


63 assign ec_rst_l_d = (combo_ec_rst_pulse || 64 ec_rst_l_det_pulse) ? 1'b0 : -1- ==> 65 (timer_expired) ? 1'b1 : ec_rst_l_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T6,T1,T14
0 0 Covered T4,T5,T6


71 assign timer_cnt_d = (timer_expired) ? '0 : -1- ==> 72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T14
0 1 Covered T4,T5,T6
0 0 Covered T6,T1,T14


79 if (!rst_ni) begin -1- 80 bat_disable_q <= 1'b0; ==> 81 ec_rst_l_det_q <= 1'b1; // active low signal 82 rst_req_q <= 1'b0; 83 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted 84 timer_cnt_q <= '0; 85 end else begin 86 bat_disable_q <= bat_disable_d; ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00

33 logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse; 34 1/1 assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i; Tests: T1 T2 T9  35 1/1 assign combo_ec_rst_pulse = cfg_ec_rst_en_i & combo_det_pulse_i; Tests: T6 T1 T19  36 1/1 assign combo_ot_pulse = cfg_rst_req_en_i & combo_det_pulse_i; Tests: T1 T2 T9  37 1/1 assign combo_intr_pulse_o = cfg_intr_en_i & combo_det_pulse_i; Tests: T6 T1 T19  38 39 //ec_rst_l_i high->low detection 40 logic ec_rst_l_det_pulse, ec_rst_l_det_q; 41 1/1 assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q; Tests: T4 T5 T6  42 43 //////////////////////////////////// 44 // Bat / OT reset pulse latching // 45 //////////////////////////////////// 46 47 logic bat_disable_q, bat_disable_d; 48 1/1 assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse; Tests: T43 T47 T296  49 1/1 assign bat_disable_o = bat_disable_q; Tests: T43 T47 T296  50 51 logic rst_req_q, rst_req_d; 52 1/1 assign rst_req_d = rst_req_q | combo_ot_pulse; Tests: T44 T45 T47  53 1/1 assign rst_req_o = rst_req_q; Tests: T44 T45 T47  54 55 //////////////////// 56 // EC reset logic // 57 //////////////////// 58 59 // OT reset will also reset EC 60 logic timer_expired; 61 logic ec_rst_l_q, ec_rst_l_d; 62 1/1 assign ec_rst_l_o = ec_rst_l_q; Tests: T6 T1 T14  63 1/1 assign ec_rst_l_d = (combo_ec_rst_pulse || Tests: T4 T5 T6  64 ec_rst_l_det_pulse) ? 1'b0 : 65 (timer_expired) ? 1'b1 : ec_rst_l_q; 66 67 68 // Reset stretching counter 69 logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q; 70 1/1 assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q); Tests: T4 T5 T6  71 1/1 assign timer_cnt_d = (timer_expired) ? '0 : Tests: T4 T5 T6  72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; 73 74 /////////////// 75 // Registers // 76 /////////////// 77 78 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 79 1/1 if (!rst_ni) begin Tests: T4 T5 T6  80 1/1 bat_disable_q <= 1'b0; Tests: T4 T5 T6  81 1/1 ec_rst_l_det_q <= 1'b1; // active low signal Tests: T4 T5 T6  82 1/1 rst_req_q <= 1'b0; Tests: T4 T5 T6  83 1/1 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted Tests: T4 T5 T6  84 1/1 timer_cnt_q <= '0; Tests: T4 T5 T6  85 end else begin 86 1/1 bat_disable_q <= bat_disable_d; Tests: T4 T5 T6  87 1/1 ec_rst_l_det_q <= ec_rst_l_i; Tests: T4 T5 T6  88 1/1 rst_req_q <= rst_req_d; Tests: T4 T5 T6  89 1/1 ec_rst_l_q <= ec_rst_l_d; Tests: T4 T5 T6  90 1/1 timer_cnt_q <= timer_cnt_d; Tests: T4 T5 T6 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T9
10CoveredT43,T94,T58
11CoveredT43,T47,T296

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT34,T37,T44
10CoveredT6,T1,T19
11CoveredT1,T2,T9

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T9
10CoveredT36,T44,T58
11CoveredT44,T45,T47

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT34,T35,T37
10CoveredT6,T1,T19
11CoveredT1,T2,T9

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT43,T47,T296
10CoveredT43,T47,T296

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T45,T47
10CoveredT44,T45,T47

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT1,T2,T9

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT6,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00


63 assign ec_rst_l_d = (combo_ec_rst_pulse || 64 ec_rst_l_det_pulse) ? 1'b0 : -1- ==> 65 (timer_expired) ? 1'b1 : ec_rst_l_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T6,T1,T14
0 0 Covered T4,T5,T6


71 assign timer_cnt_d = (timer_expired) ? '0 : -1- ==> 72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T14
0 1 Covered T4,T5,T6
0 0 Covered T6,T1,T14


79 if (!rst_ni) begin -1- 80 bat_disable_q <= 1'b0; ==> 81 ec_rst_l_det_q <= 1'b1; // active low signal 82 rst_req_q <= 1'b0; 83 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted 84 timer_cnt_q <= '0; 85 end else begin 86 bat_disable_q <= bat_disable_d; ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00

33 logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse; 34 1/1 assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i; Tests: T35 T36 T37  35 1/1 assign combo_ec_rst_pulse = cfg_ec_rst_en_i & combo_det_pulse_i; Tests: T35 T36 T37  36 1/1 assign combo_ot_pulse = cfg_rst_req_en_i & combo_det_pulse_i; Tests: T35 T36 T37  37 1/1 assign combo_intr_pulse_o = cfg_intr_en_i & combo_det_pulse_i; Tests: T34 T35 T36  38 39 //ec_rst_l_i high->low detection 40 logic ec_rst_l_det_pulse, ec_rst_l_det_q; 41 1/1 assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q; Tests: T4 T5 T6  42 43 //////////////////////////////////// 44 // Bat / OT reset pulse latching // 45 //////////////////////////////////// 46 47 logic bat_disable_q, bat_disable_d; 48 1/1 assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse; Tests: T44 T43 T58  49 1/1 assign bat_disable_o = bat_disable_q; Tests: T44 T43 T58  50 51 logic rst_req_q, rst_req_d; 52 1/1 assign rst_req_d = rst_req_q | combo_ot_pulse; Tests: T36 T43 T296  53 1/1 assign rst_req_o = rst_req_q; Tests: T36 T43 T296  54 55 //////////////////// 56 // EC reset logic // 57 //////////////////// 58 59 // OT reset will also reset EC 60 logic timer_expired; 61 logic ec_rst_l_q, ec_rst_l_d; 62 1/1 assign ec_rst_l_o = ec_rst_l_q; Tests: T6 T1 T14  63 1/1 assign ec_rst_l_d = (combo_ec_rst_pulse || Tests: T4 T5 T6  64 ec_rst_l_det_pulse) ? 1'b0 : 65 (timer_expired) ? 1'b1 : ec_rst_l_q; 66 67 68 // Reset stretching counter 69 logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q; 70 1/1 assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q); Tests: T4 T5 T6  71 1/1 assign timer_cnt_d = (timer_expired) ? '0 : Tests: T4 T5 T6  72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; 73 74 /////////////// 75 // Registers // 76 /////////////// 77 78 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 79 1/1 if (!rst_ni) begin Tests: T4 T5 T6  80 1/1 bat_disable_q <= 1'b0; Tests: T4 T5 T6  81 1/1 ec_rst_l_det_q <= 1'b1; // active low signal Tests: T4 T5 T6  82 1/1 rst_req_q <= 1'b0; Tests: T4 T5 T6  83 1/1 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted Tests: T4 T5 T6  84 1/1 timer_cnt_q <= '0; Tests: T4 T5 T6  85 end else begin 86 1/1 bat_disable_q <= bat_disable_d; Tests: T4 T5 T6  87 1/1 ec_rst_l_det_q <= ec_rst_l_i; Tests: T4 T5 T6  88 1/1 rst_req_q <= rst_req_d; Tests: T4 T5 T6  89 1/1 ec_rst_l_q <= ec_rst_l_d; Tests: T4 T5 T6  90 1/1 timer_cnt_q <= timer_cnt_d; Tests: T4 T5 T6 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT35,T36,T37
10CoveredT44,T43,T59
11CoveredT44,T43,T58

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT36,T43,T94
10CoveredT35,T37,T44
11CoveredT35,T37,T44

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT35,T37,T44
10CoveredT36,T43,T59
11CoveredT36,T43,T296

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT35,T44,T69
10CoveredT34,T36,T37
11CoveredT36,T37,T43

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T43,T58
10CoveredT44,T43,T58

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT36,T43,T296
10CoveredT36,T43,T296

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT35,T37,T44

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT6,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00


63 assign ec_rst_l_d = (combo_ec_rst_pulse || 64 ec_rst_l_det_pulse) ? 1'b0 : -1- ==> 65 (timer_expired) ? 1'b1 : ec_rst_l_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T6,T1,T14
0 0 Covered T4,T5,T6


71 assign timer_cnt_d = (timer_expired) ? '0 : -1- ==> 72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T14
0 1 Covered T4,T5,T6
0 0 Covered T6,T1,T14


79 if (!rst_ni) begin -1- 80 bat_disable_q <= 1'b0; ==> 81 ec_rst_l_det_q <= 1'b1; // active low signal 82 rst_req_q <= 1'b0; 83 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted 84 timer_cnt_q <= '0; 85 end else begin 86 bat_disable_q <= bat_disable_d; ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00

33 logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse; 34 1/1 assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i; Tests: T34 T35 T36  35 1/1 assign combo_ec_rst_pulse = cfg_ec_rst_en_i & combo_det_pulse_i; Tests: T34 T35 T36  36 1/1 assign combo_ot_pulse = cfg_rst_req_en_i & combo_det_pulse_i; Tests: T35 T37 T44  37 1/1 assign combo_intr_pulse_o = cfg_intr_en_i & combo_det_pulse_i; Tests: T35 T37 T44  38 39 //ec_rst_l_i high->low detection 40 logic ec_rst_l_det_pulse, ec_rst_l_det_q; 41 1/1 assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q; Tests: T4 T5 T6  42 43 //////////////////////////////////// 44 // Bat / OT reset pulse latching // 45 //////////////////////////////////// 46 47 logic bat_disable_q, bat_disable_d; 48 1/1 assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse; Tests: T44 T45 T46  49 1/1 assign bat_disable_o = bat_disable_q; Tests: T44 T45 T46  50 51 logic rst_req_q, rst_req_d; 52 1/1 assign rst_req_d = rst_req_q | combo_ot_pulse; Tests: T43 T45 T46  53 1/1 assign rst_req_o = rst_req_q; Tests: T43 T45 T46  54 55 //////////////////// 56 // EC reset logic // 57 //////////////////// 58 59 // OT reset will also reset EC 60 logic timer_expired; 61 logic ec_rst_l_q, ec_rst_l_d; 62 1/1 assign ec_rst_l_o = ec_rst_l_q; Tests: T6 T1 T14  63 1/1 assign ec_rst_l_d = (combo_ec_rst_pulse || Tests: T4 T5 T6  64 ec_rst_l_det_pulse) ? 1'b0 : 65 (timer_expired) ? 1'b1 : ec_rst_l_q; 66 67 68 // Reset stretching counter 69 logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q; 70 1/1 assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q); Tests: T4 T5 T6  71 1/1 assign timer_cnt_d = (timer_expired) ? '0 : Tests: T4 T5 T6  72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; 73 74 /////////////// 75 // Registers // 76 /////////////// 77 78 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 79 1/1 if (!rst_ni) begin Tests: T4 T5 T6  80 1/1 bat_disable_q <= 1'b0; Tests: T4 T5 T6  81 1/1 ec_rst_l_det_q <= 1'b1; // active low signal Tests: T4 T5 T6  82 1/1 rst_req_q <= 1'b0; Tests: T4 T5 T6  83 1/1 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted Tests: T4 T5 T6  84 1/1 timer_cnt_q <= '0; Tests: T4 T5 T6  85 end else begin 86 1/1 bat_disable_q <= bat_disable_d; Tests: T4 T5 T6  87 1/1 ec_rst_l_det_q <= ec_rst_l_i; Tests: T4 T5 T6  88 1/1 rst_req_q <= rst_req_d; Tests: T4 T5 T6  89 1/1 ec_rst_l_q <= ec_rst_l_d; Tests: T4 T5 T6  90 1/1 timer_cnt_q <= timer_cnt_d; Tests: T4 T5 T6 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT35,T37,T43
10CoveredT34,T36,T44
11CoveredT44,T45,T46

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT37,T44,T43
10CoveredT34,T35,T36
11CoveredT35,T59,T69

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT35,T37,T44
10CoveredT43,T94,T96
11CoveredT43,T45,T46

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT35,T37,T43
10CoveredT44,T95,T45
11CoveredT44,T45,T46

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T45,T46
10CoveredT44,T45,T46

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT43,T45,T46
10CoveredT43,T45,T46

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT35,T59,T69

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT6,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00


63 assign ec_rst_l_d = (combo_ec_rst_pulse || 64 ec_rst_l_det_pulse) ? 1'b0 : -1- ==> 65 (timer_expired) ? 1'b1 : ec_rst_l_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T6,T1,T14
0 0 Covered T4,T5,T6


71 assign timer_cnt_d = (timer_expired) ? '0 : -1- ==> 72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T14
0 1 Covered T4,T5,T6
0 0 Covered T6,T1,T14


79 if (!rst_ni) begin -1- 80 bat_disable_q <= 1'b0; ==> 81 ec_rst_l_det_q <= 1'b1; // active low signal 82 rst_req_q <= 1'b0; 83 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted 84 timer_cnt_q <= '0; 85 end else begin 86 bat_disable_q <= bat_disable_d; ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
TOTAL2424100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3511100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3711100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6311100.00
CONT_ASSIGN7011100.00
CONT_ASSIGN7111100.00
ALWAYS791111100.00

33 logic combo_bat_disable_pulse, combo_ot_pulse, combo_ec_rst_pulse; 34 1/1 assign combo_bat_disable_pulse = cfg_bat_disable_en_i & combo_det_pulse_i; Tests: T34 T35 T36  35 1/1 assign combo_ec_rst_pulse = cfg_ec_rst_en_i & combo_det_pulse_i; Tests: T35 T36 T37  36 1/1 assign combo_ot_pulse = cfg_rst_req_en_i & combo_det_pulse_i; Tests: T35 T36 T37  37 1/1 assign combo_intr_pulse_o = cfg_intr_en_i & combo_det_pulse_i; Tests: T34 T35 T36  38 39 //ec_rst_l_i high->low detection 40 logic ec_rst_l_det_pulse, ec_rst_l_det_q; 41 1/1 assign ec_rst_l_det_pulse = ~ec_rst_l_i & ec_rst_l_det_q; Tests: T4 T5 T6  42 43 //////////////////////////////////// 44 // Bat / OT reset pulse latching // 45 //////////////////////////////////// 46 47 logic bat_disable_q, bat_disable_d; 48 1/1 assign bat_disable_d = bat_disable_q | combo_bat_disable_pulse; Tests: T44 T43 T130  49 1/1 assign bat_disable_o = bat_disable_q; Tests: T44 T43 T130  50 51 logic rst_req_q, rst_req_d; 52 1/1 assign rst_req_d = rst_req_q | combo_ot_pulse; Tests: T44 T43 T45  53 1/1 assign rst_req_o = rst_req_q; Tests: T44 T43 T45  54 55 //////////////////// 56 // EC reset logic // 57 //////////////////// 58 59 // OT reset will also reset EC 60 logic timer_expired; 61 logic ec_rst_l_q, ec_rst_l_d; 62 1/1 assign ec_rst_l_o = ec_rst_l_q; Tests: T6 T1 T14  63 1/1 assign ec_rst_l_d = (combo_ec_rst_pulse || Tests: T4 T5 T6  64 ec_rst_l_det_pulse) ? 1'b0 : 65 (timer_expired) ? 1'b1 : ec_rst_l_q; 66 67 68 // Reset stretching counter 69 logic [TimerWidth-1:0] timer_cnt_d, timer_cnt_q; 70 1/1 assign timer_expired = (ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q); Tests: T4 T5 T6  71 1/1 assign timer_cnt_d = (timer_expired) ? '0 : Tests: T4 T5 T6  72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; 73 74 /////////////// 75 // Registers // 76 /////////////// 77 78 always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs 79 1/1 if (!rst_ni) begin Tests: T4 T5 T6  80 1/1 bat_disable_q <= 1'b0; Tests: T4 T5 T6  81 1/1 ec_rst_l_det_q <= 1'b1; // active low signal Tests: T4 T5 T6  82 1/1 rst_req_q <= 1'b0; Tests: T4 T5 T6  83 1/1 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted Tests: T4 T5 T6  84 1/1 timer_cnt_q <= '0; Tests: T4 T5 T6  85 end else begin 86 1/1 bat_disable_q <= bat_disable_d; Tests: T4 T5 T6  87 1/1 ec_rst_l_det_q <= ec_rst_l_i; Tests: T4 T5 T6  88 1/1 rst_req_q <= rst_req_d; Tests: T4 T5 T6  89 1/1 ec_rst_l_q <= ec_rst_l_d; Tests: T4 T5 T6  90 1/1 timer_cnt_q <= timer_cnt_d; Tests: T4 T5 T6 

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
TotalCoveredPercent
Conditions414097.56
Logical414097.56
Non-Logical00
Event00

 LINE       34
 EXPRESSION (cfg_bat_disable_en_i & combo_det_pulse_i)
             ----------1---------   --------2--------
-1--2-StatusTests
01CoveredT35,T36,T37
10CoveredT34,T44,T43
11CoveredT44,T43,T130

 LINE       35
 EXPRESSION (cfg_ec_rst_en_i & combo_det_pulse_i)
             -------1-------   --------2--------
-1--2-StatusTests
01CoveredT36,T45,T142
10CoveredT35,T37,T44
11CoveredT35,T37,T44

 LINE       36
 EXPRESSION (cfg_rst_req_en_i & combo_det_pulse_i)
             --------1-------   --------2--------
-1--2-StatusTests
01CoveredT35,T36,T37
10CoveredT44,T43,T59
11CoveredT44,T43,T45

 LINE       37
 EXPRESSION (cfg_intr_en_i & combo_det_pulse_i)
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT35,T36,T37
10CoveredT34,T44,T43
11CoveredT44,T43,T47

 LINE       41
 EXPRESSION (((~ec_rst_l_i)) & ec_rst_l_det_q)
             -------1-------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT4,T5,T6

 LINE       48
 EXPRESSION (bat_disable_q | combo_bat_disable_pulse)
             ------1------   -----------2-----------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T43,T130
10CoveredT44,T43,T130

 LINE       52
 EXPRESSION (rst_req_q | combo_ot_pulse)
             ----1----   -------2------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT44,T43,T45
10CoveredT44,T43,T45

 LINE       63
 EXPRESSION ((combo_ec_rst_pulse || ec_rst_l_det_pulse) ? 1'b0 : (timer_expired ? 1'b1 : ec_rst_l_q))
             ---------------------1--------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       63
 SUB-EXPRESSION (combo_ec_rst_pulse || ec_rst_l_det_pulse)
                 ---------1--------    ---------2--------
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT35,T37,T44

 LINE       63
 SUB-EXPRESSION (timer_expired ? 1'b1 : ec_rst_l_q)
                 ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       70
 EXPRESSION ((ec_rst_l_q == 1'b0) && (timer_cnt_q == ec_rst_ctl_i.q))
             ----------1---------    ---------------2---------------
-1--2-StatusTests
01Not Covered
10CoveredT4,T5,T6
11CoveredT6,T1,T14

 LINE       70
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       70
 SUB-EXPRESSION (timer_cnt_q == ec_rst_ctl_i.q)
                ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 EXPRESSION (timer_expired ? '0 : ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q))
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T14

 LINE       71
 SUB-EXPRESSION ((ec_rst_l_q == 1'b0) ? ((timer_cnt_q + 1'b1)) : timer_cnt_q)
                 ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

 LINE       71
 SUB-EXPRESSION (ec_rst_l_q == 1'b0)
                ----------1---------
-1-StatusTests
0CoveredT6,T1,T14
1CoveredT4,T5,T6

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_combo_act
Line No.TotalCoveredPercent
Branches 8 8 100.00
TERNARY 63 3 3 100.00
TERNARY 71 3 3 100.00
IF 79 2 2 100.00


63 assign ec_rst_l_d = (combo_ec_rst_pulse || 64 ec_rst_l_det_pulse) ? 1'b0 : -1- ==> 65 (timer_expired) ? 1'b1 : ec_rst_l_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T6,T1,T14
0 0 Covered T4,T5,T6


71 assign timer_cnt_d = (timer_expired) ? '0 : -1- ==> 72 (ec_rst_l_q == 1'b0) ? timer_cnt_q + 1'b1 : timer_cnt_q; -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T6,T1,T14
0 1 Covered T4,T5,T6
0 0 Covered T6,T1,T14


79 if (!rst_ni) begin -1- 80 bat_disable_q <= 1'b0; ==> 81 ec_rst_l_det_q <= 1'b1; // active low signal 82 rst_req_q <= 1'b0; 83 ec_rst_l_q <= 1'b0; // asserted when power-on-reset is asserted 84 timer_cnt_q <= '0; 85 end else begin 86 bat_disable_q <= bat_disable_d; ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%