| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 75.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| sysrst_ctrl_combo_precondition_det_cg1 | 66.67 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_precondition_det_cg2 | 66.67 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_precondition_det_cg3 | 66.67 | 1 | 100 | 1 | 64 | 64 |
| sysrst_ctrl_combo_precondition_det_cg0 | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 66.67 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 1 | 2 | 66.67 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_precondition_timer | 3 | 1 | 2 | 66.67 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 66.67 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 1 | 2 | 66.67 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_precondition_timer | 3 | 1 | 2 | 66.67 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 66.67 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 1 | 2 | 66.67 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_precondition_timer | 3 | 1 | 2 | 66.67 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_precondition_timer | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 1 | 2 | 66.67 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| mid_range | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 31 | 1 | T44 | 6 | T266 | 11 | T361 | 10 | ||||
| min_range | 347 | 1 | T33 | 8 | T34 | 7 | T35 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 1 | 2 | 66.67 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| mid_range | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 19 | 1 | T243 | 1 | T373 | 11 | T384 | 2 | ||||
| min_range | 350 | 1 | T33 | 8 | T34 | 7 | T35 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 1 | 2 | 66.67 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| mid_range | 0 | 1 | 1 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 19 | 1 | T95 | 1 | T96 | 11 | T372 | 3 | ||||
| min_range | 359 | 1 | T33 | 8 | T34 | 7 | T35 | 7 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| max_range | 14 | 1 | T385 | 5 | T386 | 4 | T360 | 5 | ||||
| mid_range | 21 | 1 | T247 | 1 | T361 | 10 | T362 | 10 | ||||
| min_range | 343 | 1 | T33 | 8 | T34 | 7 | T35 | 7 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |