Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg
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Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
95.12 95.12 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_combo_key_combinations_cg 95.12 1 100 1 64 64




Group Instance : sysrst_ctrl_combo_key_combinations_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.12 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 20 0 20 100.00
Crosses 62 4 58 93.55


Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_ac_present_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key0_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key1_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_key2_in_sel 2 0 2 100.00 100 1 1 2
cp_precondition_pwrb_in_sel 2 0 2 100.00 100 1 1 2
cp_pwrb_in_sel 2 0 2 100.00 100 1 1 2


Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cross_key_combinations_combo_precondition_sel 31 4 27 87.10 100 1 1 0
cross_key_combinations_combo_detection_sel 31 0 31 100.00 100 1 1 0


Summary for Variable cp_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1870 1 T19 4 T33 34 T54 17
auto[1] 582 1 T33 6 T54 11 T44 2



Summary for Variable cp_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1921 1 T19 4 T33 36 T54 22
auto[1] 531 1 T33 4 T54 6 T55 2



Summary for Variable cp_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1864 1 T33 36 T54 28 T44 16
auto[1] 588 1 T19 4 T33 4 T44 4



Summary for Variable cp_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1814 1 T19 4 T33 34 T54 23
auto[1] 638 1 T33 6 T54 5 T55 4



Summary for Variable cp_precondition_ac_present_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_ac_present_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2269 1 T19 4 T33 30 T54 28
auto[1] 183 1 T33 10 T94 10 T96 6



Summary for Variable cp_precondition_key0_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key0_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2209 1 T19 4 T33 34 T54 28
auto[1] 243 1 T33 6 T44 2 T94 4



Summary for Variable cp_precondition_key1_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key1_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2224 1 T19 4 T33 28 T54 23
auto[1] 228 1 T33 12 T54 5 T243 12



Summary for Variable cp_precondition_key2_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_key2_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2196 1 T19 4 T33 36 T54 22
auto[1] 256 1 T33 4 T54 6 T44 4



Summary for Variable cp_precondition_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2210 1 T19 4 T33 40 T54 28
auto[1] 242 1 T96 12 T122 6 T123 1



Summary for Variable cp_pwrb_in_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in_sel

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1790 1 T33 24 T54 28 T44 16
auto[1] 662 1 T19 4 T33 16 T44 4



Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 31 4 27 87.10 4
Automatically Generated Cross Bins 31 4 27 87.10 4
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins
cp_precondition_key0_in_sel   cp_precondition_key1_in_sel   cp_precondition_key2_in_sel   cp_precondition_pwrb_in_sel   cp_precondition_ac_present_sel   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_precondition_key0_in_sel   cp_precondition_key1_in_sel   cp_precondition_key2_in_sel   cp_precondition_pwrb_in_sel   cp_precondition_ac_present_sel   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] auto[0] auto[0] 733 1 T19 4 T55 3 T121 1
auto[0] auto[0] auto[0] auto[0] auto[1] 49 1 T94 6 T126 1 T345 4
auto[0] auto[0] auto[0] auto[1] auto[0] 82 1 T47 12 T244 3 T266 9
auto[0] auto[0] auto[0] auto[1] auto[1] 20 1 T47 11 T348 3 T356 6
auto[0] auto[0] auto[1] auto[0] auto[0] 79 1 T54 4 T44 4 T357 3
auto[0] auto[0] auto[1] auto[0] auto[1] 31 1 T33 4 T358 3 T115 3
auto[0] auto[0] auto[1] auto[1] auto[0] 8 1 T359 2 T360 6 - -
auto[0] auto[0] auto[1] auto[1] auto[1] 8 1 T96 6 T348 2 - -
auto[0] auto[1] auto[0] auto[0] auto[0] 102 1 T54 2 T244 3 T361 8
auto[0] auto[1] auto[0] auto[0] auto[1] 18 1 T33 6 T115 2 T362 4
auto[0] auto[1] auto[0] auto[1] auto[0] 10 1 T123 1 T244 2 T362 7
auto[0] auto[1] auto[0] auto[1] auto[1] 2 1 T363 1 T364 1 - -
auto[0] auto[1] auto[1] auto[0] auto[0] 15 1 T357 2 T348 1 T365 1
auto[0] auto[1] auto[1] auto[0] auto[1] 2 1 T366 2 - - - -
auto[0] auto[1] auto[1] auto[1] auto[0] 17 1 T345 3 T367 9 T360 5
auto[1] auto[0] auto[0] auto[0] auto[0] 66 1 T44 2 T357 1 T368 3
auto[1] auto[0] auto[0] auto[0] auto[1] 20 1 T94 4 T47 8 T358 1
auto[1] auto[0] auto[0] auto[1] auto[0] 50 1 T96 6 T122 6 T369 1
auto[1] auto[0] auto[0] auto[1] auto[1] 3 1 T368 2 T341 1 - -
auto[1] auto[0] auto[1] auto[0] auto[0] 43 1 T266 4 T358 1 T370 6
auto[1] auto[0] auto[1] auto[0] auto[1] 10 1 T241 4 T266 1 T358 1
auto[1] auto[0] auto[1] auto[1] auto[0] 4 1 T368 2 T343 2 - -
auto[1] auto[1] auto[0] auto[0] auto[0] 13 1 T33 6 T122 6 T371 1
auto[1] auto[1] auto[0] auto[0] auto[1] 1 1 T372 1 - - - -
auto[1] auto[1] auto[0] auto[1] auto[0] 6 1 T239 1 T373 5 - -
auto[1] auto[1] auto[1] auto[0] auto[0] 6 1 T258 4 T360 2 - -
auto[1] auto[1] auto[1] auto[1] auto[0] 1 1 T361 1 - - - -


User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins
NAMECOUNTSTATUS
detection_disable 0 Excluded



Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 31 0 31 100.00
Automatically Generated Cross Bins 31 0 31 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins
cp_key0_in_sel   cp_key1_in_sel   cp_key2_in_sel   cp_pwrb_in_sel   cp_ac_present_sel   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[0] auto[0] auto[0] auto[1] 109 1 T44 2 T45 10 T357 5
auto[0] auto[0] auto[0] auto[1] auto[0] 123 1 T42 7 T147 12 T115 3
auto[0] auto[0] auto[0] auto[1] auto[1] 52 1 T33 6 T122 6 T257 5
auto[0] auto[0] auto[1] auto[0] auto[0] 97 1 T47 12 T336 10 T147 12
auto[0] auto[0] auto[1] auto[0] auto[1] 61 1 T54 2 T41 6 T244 3
auto[0] auto[0] auto[1] auto[1] auto[0] 86 1 T33 6 T336 14 T115 2
auto[0] auto[0] auto[1] auto[1] auto[1] 25 1 T260 2 T269 5 T270 3
auto[0] auto[1] auto[0] auto[0] auto[0] 79 1 T94 4 T47 8 T125 7
auto[0] auto[1] auto[0] auto[0] auto[1] 50 1 T96 6 T42 5 T43 3
auto[0] auto[1] auto[0] auto[1] auto[0] 73 1 T19 4 T44 4 T261 3
auto[0] auto[1] auto[0] auto[1] auto[1] 48 1 T249 2 T336 10 T115 4
auto[0] auto[1] auto[1] auto[0] auto[0] 54 1 T94 6 T45 6 T122 6
auto[0] auto[1] auto[1] auto[0] auto[1] 30 1 T41 3 T261 3 T127 1
auto[0] auto[1] auto[1] auto[1] auto[0] 17 1 T41 4 T129 3 T253 3
auto[0] auto[1] auto[1] auto[1] auto[1] 15 1 T55 2 T249 2 T357 1
auto[1] auto[0] auto[0] auto[0] auto[0] 47 1 T96 6 T244 3 T348 2
auto[1] auto[0] auto[0] auto[0] auto[1] 47 1 T54 4 T267 5 T348 1
auto[1] auto[0] auto[0] auto[1] auto[0] 53 1 T257 3 T272 5 T248 3
auto[1] auto[0] auto[0] auto[1] auto[1] 20 1 T267 4 T124 3 T127 3
auto[1] auto[0] auto[1] auto[0] auto[0] 76 1 T45 8 T123 1 T46 6
auto[1] auto[0] auto[1] auto[0] auto[1] 6 1 T250 1 T374 2 T375 3
auto[1] auto[0] auto[1] auto[1] auto[0] 40 1 T185 1 T335 5 T253 5
auto[1] auto[0] auto[1] auto[1] auto[1] 3 1 T272 1 T341 2 - -
auto[1] auto[1] auto[0] auto[0] auto[0] 64 1 T249 5 T43 2 T272 6
auto[1] auto[1] auto[0] auto[0] auto[1] 24 1 T131 2 T376 1 T252 3
auto[1] auto[1] auto[0] auto[1] auto[0] 33 1 T33 4 T272 3 T336 3
auto[1] auto[1] auto[0] auto[1] auto[1] 11 1 T248 1 T251 2 T377 3
auto[1] auto[1] auto[1] auto[0] auto[0] 37 1 T43 1 T46 6 T336 4
auto[1] auto[1] auto[1] auto[0] auto[1] 10 1 T121 1 T45 4 T132 1
auto[1] auto[1] auto[1] auto[1] auto[0] 7 1 T41 2 T336 2 T338 2
auto[1] auto[1] auto[1] auto[1] auto[1] 2 1 T55 1 T257 1 - -


User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins
NAMECOUNTSTATUS
detection_disable 0 Excluded