Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

626

1

T28

9

T65

10

T89

8

auto[1]

594

1

T28

11

T65

10

T89

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

285

1

T28

3

T65

6

T89

8

from_0to1

291

1

T28

3

T65

7

T89

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

631

1

T28

11

T65

12

T89

7

auto[1]

589

1

T28

9

T65

8

T89

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T28

10

T65

8

T89

12

auto[1]

590

1

T28

10

T65

12

T89

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T90

2

T395

2

T106

1

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T65

2

T89

1

T395

1

auto[0]

from_1to0

auto[1]

auto[0]

32

1

T89

2

T100

3

T242

3

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T65

1

T90

1

T106

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T90

2

T307

1

T226

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T65

3

T106

1

T100

2

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T28

1

T89

2

T90

1

auto[0]

from_0to1

auto[1]

auto[1]

37

1

T89

1

T106

1

T307

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T65

2

T89

1

T106

1

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T28

2

T89

1

T106

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T28

1

T65

1

T89

1

auto[1]

from_1to0

auto[1]

auto[1]

35

1

T89

2

T90

1

T227

1

auto[1]

from_0to1

auto[0]

auto[0]

28

1

T90

1

T106

1

T307

1

auto[1]

from_0to1

auto[0]

auto[1]

30

1

T28

1

T65

1

T89

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T65

3

T89

4

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T28

1

T90

1

T395

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T28

9

T65

8

T89

14

auto[1]

611

1

T28

11

T65

12

T89

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

283

1

T28

4

T65

5

T89

3

from_0to1

286

1

T28

4

T65

6

T89

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T28

13

T65

9

T89

8

auto[1]

590

1

T28

7

T65

11

T89

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T28

9

T65

9

T89

9

auto[1]

580

1

T28

11

T65

11

T89

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T28

1

T106

3

T307

1

auto[0]

from_1to0

auto[0]

auto[1]

27

1

T28

1

T90

2

T106

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T90

1

T395

1

T100

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T65

2

T100

1

T242

1

auto[0]

from_0to1

auto[0]

auto[0]

42

1

T89

2

T395

1

T106

2

auto[0]

from_0to1

auto[0]

auto[1]

32

1

T28

1

T65

2

T90

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T28

1

T65

2

T90

1

auto[0]

from_0to1

auto[1]

auto[1]

35

1

T89

1

T395

1

T106

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T89

1

T90

2

T395

1

auto[1]

from_1to0

auto[0]

auto[1]

29

1

T65

1

T89

1

T395

1

auto[1]

from_1to0

auto[1]

auto[0]

38

1

T28

1

T65

1

T100

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T28

1

T65

1

T89

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T28

1

T395

1

T106

1

auto[1]

from_0to1

auto[0]

auto[1]

28

1

T28

1

T65

1

T90

3

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T65

1

T90

1

T106

1

auto[1]

from_0to1

auto[1]

auto[1]

32

1

T100

2

T226

1

T396

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T28

6

T65

12

T89

9

auto[1]

616

1

T28

14

T65

8

T89

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

293

1

T28

8

T65

4

T89

5

from_0to1

293

1

T28

7

T65

3

T89

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

617

1

T28

10

T65

15

T89

11

auto[1]

603

1

T28

10

T65

5

T89

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

640

1

T28

10

T65

9

T89

9

auto[1]

580

1

T28

10

T65

11

T89

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T90

1

T106

1

T307

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T28

2

T65

2

T89

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T28

1

T90

1

T395

1

auto[0]

from_1to0

auto[1]

auto[1]

30

1

T89

1

T90

1

T100

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T28

1

T65

1

T89

1

auto[0]

from_0to1

auto[0]

auto[1]

37

1

T90

1

T106

1

T100

1

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T89

1

T90

1

T395

1

auto[0]

from_0to1

auto[1]

auto[1]

31

1

T89

1

T307

1

T396

1

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T28

1

T65

1

T89

1

auto[1]

from_1to0

auto[0]

auto[1]

31

1

T28

2

T106

2

T242

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T28

2

T65

1

T89

1

auto[1]

from_1to0

auto[1]

auto[1]

44

1

T89

1

T90

1

T395

2

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T65

1

T89

2

T395

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T65

1

T395

4

T106

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T28

3

T90

4

T106

1

auto[1]

from_0to1

auto[1]

auto[1]

27

1

T28

3

T90

1

T242

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T28

10

T65

11

T89

7

auto[1]

614

1

T28

10

T65

9

T89

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

300

1

T28

5

T65

6

T89

7

from_0to1

293

1

T28

4

T65

6

T89

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T28

11

T65

9

T89

11

auto[1]

602

1

T28

9

T65

11

T89

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T28

11

T65

8

T89

14

auto[1]

605

1

T28

9

T65

12

T89

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

30

1

T28

3

T106

1

T100

1

auto[0]

from_1to0

auto[0]

auto[1]

39

1

T28

1

T65

1

T89

1

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T65

1

T89

1

T90

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T28

1

T90

1

T395

3

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T65

1

T89

1

T90

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T28

2

T65

1

T242

3

auto[0]

from_0to1

auto[1]

auto[0]

34

1

T89

1

T90

1

T100

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T395

1

T307

2

T226

1

auto[1]

from_1to0

auto[0]

auto[0]

41

1

T65

1

T89

2

T90

1

auto[1]

from_1to0

auto[0]

auto[1]

34

1

T89

1

T395

1

T106

2

auto[1]

from_1to0

auto[1]

auto[0]

47

1

T65

2

T89

2

T90

2

auto[1]

from_1to0

auto[1]

auto[1]

38

1

T65

1

T90

1

T307

2

auto[1]

from_0to1

auto[0]

auto[0]

31

1

T89

1

T90

2

T106

3

auto[1]

from_0to1

auto[0]

auto[1]

33

1

T65

1

T89

1

T395

2

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T28

1

T89

1

T90

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T28

1

T65

3

T89

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T28

11

T65

11

T89

8

auto[1]

616

1

T28

9

T65

9

T89

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

295

1

T28

5

T65

5

T89

6

from_0to1

316

1

T28

6

T65

5

T89

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

602

1

T28

10

T65

9

T89

7

auto[1]

618

1

T28

10

T65

11

T89

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577

1

T28

7

T65

9

T89

11

auto[1]

643

1

T28

13

T65

11

T89

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

36

1

T28

1

T65

2

T90

1

auto[0]

from_1to0

auto[0]

auto[1]

33

1

T28

2

T90

1

T395

1

auto[0]

from_1to0

auto[1]

auto[0]

32

1

T65

1

T89

2

T90

2

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T65

2

T89

1

T395

2

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T28

1

T100

2

T307

1

auto[0]

from_0to1

auto[0]

auto[1]

44

1

T28

1

T65

1

T89

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T28

1

T65

1

T106

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T65

1

T89

1

T106

1

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T90

1

T227

1

T397

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T395

1

T106

1

T100

2

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T28

1

T89

2

T106

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T28

1

T89

1

T242

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T65

1

T89

2

T90

2

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T28

2

T90

2

T307

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T89

1

T90

1

T395

2

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T28

1

T65

1

T89

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

587

1

T28

11

T65

9

T89

10

auto[1]

633

1

T28

9

T65

11

T89

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

305

1

T28

3

T65

5

T89

5

from_0to1

304

1

T28

3

T65

5

T89

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T28

12

T65

10

T89

8

auto[1]

617

1

T28

8

T65

10

T89

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T28

9

T65

8

T89

8

auto[1]

624

1

T28

11

T65

12

T89

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T65

1

T89

1

T226

3

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T90

1

T395

1

T242

2

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T28

1

T90

1

T395

1

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T28

1

T65

1

T89

2

auto[0]

from_0to1

auto[0]

auto[0]

45

1

T28

1

T65

2

T90

1

auto[0]

from_0to1

auto[0]

auto[1]

25

1

T89

2

T90

1

T106

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T90

1

T395

1

T106

1

auto[0]

from_0to1

auto[1]

auto[1]

31

1

T28

1

T65

1

T90

1

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T65

1

T395

1

T106

2

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T28

1

T65

1

T90

1

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T89

1

T395

1

T100

1

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T65

1

T89

1

T90

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T28

1

T89

1

T106

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T89

1

T395

1

T106

2

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T65

2

T90

1

T395

2

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T89

1

T395

1

T100

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T28

13

T65

7

T89

7

auto[1]

604

1

T28

7

T65

13

T89

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

293

1

T28

4

T65

3

T89

4

from_0to1

295

1

T28

5

T65

4

T89

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T28

8

T65

12

T89

13

auto[1]

615

1

T28

12

T65

8

T89

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T28

10

T65

15

T89

12

auto[1]

610

1

T28

10

T65

5

T89

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T28

1

T90

1

T242

1

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T90

1

T242

1

T307

1

auto[0]

from_1to0

auto[1]

auto[0]

28

1

T28

1

T65

1

T90

1

auto[0]

from_1to0

auto[1]

auto[1]

32

1

T106

2

T100

1

T242

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T65

2

T106

1

T242

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T28

1

T90

1

T307

2

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T395

2

T106

2

T242

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T28

2

T242

1

T307

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T65

1

T89

1

T395

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T65

1

T89

1

T90

1

auto[1]

from_1to0

auto[1]

auto[0]

46

1

T28

1

T89

1

T90

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T28

1

T89

1

T395

1

auto[1]

from_0to1

auto[0]

auto[0]

26

1

T28

2

T65

1

T89

2

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T89

1

T395

2

T106

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T89

1

T395

2

T100

1

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T65

1

T90

3

T395

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591

1

T28

11

T65

7

T89

5

auto[1]

629

1

T28

9

T65

13

T89

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

285

1

T28

7

T65

7

T89

5

from_0to1

278

1

T28

6

T65

6

T89

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T28

9

T65

15

T89

9

auto[1]

608

1

T28

11

T65

5

T89

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

621

1

T28

12

T65

9

T89

9

auto[1]

599

1

T28

8

T65

11

T89

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T28

1

T65

3

T89

1

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T90

1

T106

2

T100

1

auto[0]

from_1to0

auto[1]

auto[0]

39

1

T28

3

T242

1

T226

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T90

1

T395

1

T106

2

auto[0]

from_0to1

auto[0]

auto[0]

37

1

T106

2

T100

2

T227

1

auto[0]

from_0to1

auto[0]

auto[1]

30

1

T28

2

T65

2

T106

1

auto[0]

from_0to1

auto[1]

auto[0]

30

1

T89

2

T106

1

T100

1

auto[0]

from_0to1

auto[1]

auto[1]

21

1

T100

1

T398

1

T399

2

auto[1]

from_1to0

auto[0]

auto[0]

28

1

T28

1

T106

1

T100

1

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T28

1

T65

3

T89

2

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T28

1

T89

1

T242

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T65

1

T89

1

T90

1

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T65

1

T89

1

T395

1

auto[1]

from_0to1

auto[0]

auto[1]

34

1

T28

1

T65

1

T89

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T28

3

T65

2

T89

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T106

1

T242

1

T397

1