Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137244	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

107040

1

T4

2

T5

22

T1

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	127999	1			T4	3		T5	2		T1	11
values[0x0]	57566	1			T4	2		T5	40		T1	4
values[0x1]	58719	1			T4	5		T5	21		T1	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	110765	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

133519

1

T4

3

T5

26

T1

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	683	1			T5	2		T65	2		T32	1
valid_sources[0x01]	868	1			T65	1		T194	1		T89	1
valid_sources[0x02]	692	1			T89	2		T90	1		T177	1
valid_sources[0x03]	838	1			T1	1		T89	1		T114	4
valid_sources[0x04]	848	1			T2	1		T29	1		T65	1
valid_sources[0x05]	771	1			T5	1		T86	5		T90	1
valid_sources[0x06]	2073	1			T114	15		T81	1		T33	1129
valid_sources[0x07]	718	1			T65	2		T114	7		T82	1
valid_sources[0x08]	1959	1			T87	15		T89	1		T90	3
valid_sources[0x09]	729	1			T179	2		T19	2		T105	8
valid_sources[0x0a]	919	1			T5	1		T87	20		T90	2
valid_sources[0x0b]	849	1			T8	2		T65	1		T273	1
valid_sources[0x0c]	934	1			T65	1		T89	1		T19	5
valid_sources[0x0d]	956	1			T14	1		T65	1		T86	2
valid_sources[0x0e]	746	1			T2	1		T86	1		T89	1
valid_sources[0x0f]	771	1			T29	1		T6	3		T89	1
valid_sources[0x10]	939	1			T89	1		T153	2		T395	1
valid_sources[0x11]	742	1			T9	1		T58	3		T19	1
valid_sources[0x12]	1721	1			T86	1		T27	1		T58	1
valid_sources[0x13]	1056	1			T5	1		T2	1		T11	2
valid_sources[0x14]	754	1			T13	1		T2	1		T29	1
valid_sources[0x15]	980	1			T65	1		T27	3		T9	1
valid_sources[0x16]	843	1			T91	1		T61	1		T133	3
valid_sources[0x17]	882	1			T29	1		T65	2		T86	2
valid_sources[0x18]	761	1			T99	1		T52	1		T34	1
valid_sources[0x19]	754	1			T5	1		T58	1		T133	1
valid_sources[0x1a]	2506	1			T65	1		T89	1		T101	10
valid_sources[0x1b]	846	1			T79	3		T53	21		T83	1
valid_sources[0x1c]	1360	1			T29	1		T89	1		T31	1
valid_sources[0x1d]	840	1			T13	2		T65	1		T89	1
valid_sources[0x1e]	736	1			T65	2		T194	1		T295	1
valid_sources[0x1f]	2345	1			T89	1		T90	2		T81	4
valid_sources[0x20]	974	1			T65	1		T395	4		T100	1
valid_sources[0x21]	1017	1			T73	1		T89	1		T19	1
valid_sources[0x22]	839	1			T15	6		T90	1		T34	2
valid_sources[0x23]	1092	1			T65	1		T75	1		T89	2
valid_sources[0x24]	689	1			T65	2		T12	2		T100	3
valid_sources[0x25]	840	1			T5	1		T29	1		T57	1
valid_sources[0x26]	925	1			T2	1		T3	5		T61	1
valid_sources[0x27]	886	1			T65	1		T19	2		T82	1
valid_sources[0x28]	735	1			T2	1		T65	1		T19	8
valid_sources[0x29]	874	1			T14	1		T27	2		T114	32
valid_sources[0x2a]	888	1			T65	2		T194	1		T89	2
valid_sources[0x2b]	773	1			T5	1		T87	35		T295	1
valid_sources[0x2c]	916	1			T5	2		T65	3		T56	1
valid_sources[0x2d]	1334	1			T29	3		T65	2		T6	2
valid_sources[0x2e]	765	1			T89	1		T153	1		T81	1
valid_sources[0x2f]	1743	1			T27	3		T89	1		T91	4
valid_sources[0x30]	1046	1			T193	9		T32	1		T9	1
valid_sources[0x31]	1085	1			T13	1		T89	1		T90	2
valid_sources[0x32]	867	1			T4	1		T65	3		T89	1
valid_sources[0x33]	1366	1			T13	3		T65	1		T90	1
valid_sources[0x34]	809	1			T29	1		T10	39		T19	1
valid_sources[0x35]	789	1			T89	1		T34	1		T54	3
valid_sources[0x36]	878	1			T65	1		T56	1		T75	1
valid_sources[0x37]	761	1			T295	1		T60	1		T395	3
valid_sources[0x38]	774	1			T13	4		T2	1		T65	1
valid_sources[0x39]	829	1			T13	1		T29	1		T30	2
valid_sources[0x3a]	991	1			T5	1		T29	1		T19	1
valid_sources[0x3b]	779	1			T2	1		T65	2		T91	5
valid_sources[0x3c]	723	1			T13	1		T29	1		T11	1
valid_sources[0x3d]	904	1			T13	1		T29	2		T65	2
valid_sources[0x3e]	1154	1			T90	1		T19	1		T34	1
valid_sources[0x3f]	1923	1			T12	1		T81	1		T77	1
valid_sources[0x40]	754	1			T5	1		T295	1		T50	1
valid_sources[0x41]	1643	1			T4	2		T29	3		T73	1
valid_sources[0x42]	890	1			T5	1		T2	1		T8	1
valid_sources[0x43]	835	1			T65	1		T153	5		T90	1
valid_sources[0x44]	932	1			T89	2		T90	3		T77	1
valid_sources[0x45]	831	1			T5	2		T65	1		T75	1
valid_sources[0x46]	789	1			T13	1		T19	2		T100	1
valid_sources[0x47]	813	1			T1	1		T65	1		T89	1
valid_sources[0x48]	1033	1			T5	1		T65	1		T178	1
valid_sources[0x49]	725	1			T29	1		T295	1		T27	1
valid_sources[0x4a]	773	1			T28	2		T32	1		T89	1
valid_sources[0x4b]	918	1			T5	1		T2	1		T65	2
valid_sources[0x4c]	915	1			T2	1		T89	2		T79	2
valid_sources[0x4d]	945	1			T65	1		T89	1		T81	1
valid_sources[0x4e]	840	1			T65	4		T90	1		T91	3
valid_sources[0x4f]	794	1			T65	3		T86	11		T89	1
valid_sources[0x50]	1372	1			T29	2		T32	6		T295	2
valid_sources[0x51]	810	1			T2	1		T89	1		T91	2
valid_sources[0x52]	850	1			T65	1		T6	2		T60	1
valid_sources[0x53]	780	1			T5	2		T2	2		T30	3
valid_sources[0x54]	803	1			T5	1		T13	3		T8	10
valid_sources[0x55]	711	1			T89	1		T9	3		T90	3
valid_sources[0x56]	835	1			T90	1		T100	1		T54	2
valid_sources[0x57]	826	1			T6	2		T89	3		T90	1
valid_sources[0x58]	784	1			T56	1		T89	1		T91	1
valid_sources[0x59]	1850	1			T5	1		T29	2		T90	2
valid_sources[0x5a]	988	1			T2	1		T114	20		T90	2
valid_sources[0x5b]	1023	1			T28	6		T179	1		T82	1
valid_sources[0x5c]	907	1			T15	7		T90	1		T34	2
valid_sources[0x5d]	1170	1			T194	2		T77	1		T100	1
valid_sources[0x5e]	791	1			T89	1		T90	1		T81	1
valid_sources[0x5f]	818	1			T2	1		T65	1		T27	3
valid_sources[0x60]	759	1			T27	1		T50	1		T19	3
valid_sources[0x61]	793	1			T295	1		T89	2		T90	2
valid_sources[0x62]	972	1			T86	3		T295	3		T27	1
valid_sources[0x63]	744	1			T5	1		T2	1		T30	1
valid_sources[0x64]	1343	1			T2	1		T32	1		T31	2
valid_sources[0x65]	1332	1			T13	1		T29	1		T89	1
valid_sources[0x66]	651	1			T28	7		T86	2		T179	1
valid_sources[0x67]	1018	1			T2	1		T24	33		T89	1
valid_sources[0x68]	784	1			T5	1		T153	3		T61	3
valid_sources[0x69]	795	1			T29	1		T60	1		T179	1
valid_sources[0x6a]	738	1			T29	1		T65	1		T176	1
valid_sources[0x6b]	901	1			T89	1		T79	3		T90	1
valid_sources[0x6c]	1049	1			T29	2		T26	45		T295	2
valid_sources[0x6d]	918	1			T78	2		T296	5		T92	1
valid_sources[0x6e]	1084	1			T5	1		T79	3		T57	2
valid_sources[0x6f]	756	1			T29	1		T195	1		T87	1
valid_sources[0x70]	1048	1			T81	1		T100	2		T103	6
valid_sources[0x71]	1749	1			T5	1		T29	1		T65	1
valid_sources[0x72]	1076	1			T29	1		T87	7		T295	2
valid_sources[0x73]	872	1			T3	1		T29	1		T86	1
valid_sources[0x74]	684	1			T29	1		T113	2		T90	1
valid_sources[0x75]	793	1			T4	1		T2	1		T29	2
valid_sources[0x76]	1085	1			T2	2		T65	3		T86	1
valid_sources[0x77]	1004	1			T13	1		T178	1		T19	1
valid_sources[0x78]	1993	1			T29	1		T295	1		T27	9
valid_sources[0x79]	685	1			T5	1		T86	10		T134	3
valid_sources[0x7a]	900	1			T1	2		T89	3		T77	1
valid_sources[0x7b]	734	1			T19	4		T100	1		T34	2
valid_sources[0x7c]	825	1			T61	4		T19	1		T68	1
valid_sources[0x7d]	728	1			T178	1		T179	2		T61	2
valid_sources[0x7e]	722	1			T13	2		T89	1		T90	1
valid_sources[0x7f]	832	1			T13	3		T65	1		T60	1
valid_sources[0x80]	720	1			T89	1		T50	1		T34	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

57773

1

T5

1

T1

5

T13

12

values[0x0]

all_enables

biggest_size

28434

1

T5

17

T1

1

T13

6

values[0x1]

all_enables

biggest_size

20833

1

T4

2

T5

4

T13

2