Line Coverage for Module :
sysrst_ctrl_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 28 | 28 | 100.00 |
| CONT_ASSIGN | 41 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| ALWAYS | 61 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
| ALWAYS | 78 | 6 | 6 | 100.00 |
| ALWAYS | 105 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 121 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 170 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 174 | 1 | 1 | 100.00 |
40 logic [NumAonIntrEvents-1:0] aon_reqs;
41 1/1 assign aon_reqs = {aon_ulp_wakeup_pulse_i,
Tests: T1 T2 T3
42 aon_combo_intr_i,
43 aon_h2l_key_intr_i,
44 aon_l2h_key_intr_i};
45
46 // Latch any event in the AON domain for generating the wakep request.
47 1/1 assign wkup_status_o.de = |aon_reqs;
Tests: T1 T2 T3
48 assign wkup_status_o.d = 1'b1;
49 1/1 assign aon_wkup_req_o = wkup_status_i.q;
Tests: T1 T2 T3
50
51 // aon interrupt requests are split into staging and request portions.
52 // The staging portion always absorbs the incoming event pulse.
53 // The request portion on the other hand does not change until
54 // a request/ack handshake cycle has completed.
55 logic [NumAonIntrEvents-1:0] aon_staging_reqs_q;
56 logic aon_ld_req;
57
58 // staging portion takes on the value of the incoming event match
59 // and clears when it is snapshot into request hold.
60 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
61 1/1 if (!rst_aon_ni) begin
Tests: T4 T5 T1
62 1/1 aon_staging_reqs_q <= '0;
Tests: T4 T5 T1
63 1/1 end else if (aon_ld_req) begin
Tests: T4 T5 T1
64 1/1 aon_staging_reqs_q <= aon_reqs;
Tests: T1 T2 T3
65 1/1 end else if (|aon_reqs) begin
Tests: T4 T5 T1
66 1/1 aon_staging_reqs_q <= aon_staging_reqs_q | aon_reqs;
Tests: T1 T2 T3
67 end
MISSING_ELSE
68 end
69
70 logic [NumAonIntrEvents-1:0] aon_req_hold_q;
71 logic aon_ack;
72
73 // staging has pending requsts
74 1/1 assign aon_ld_req = (aon_req_hold_q == '0) && |aon_staging_reqs_q;
Tests: T1 T2 T3
75
76 // request hold self clears when the handshake cycle is complete
77 always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
78 1/1 if (!rst_aon_ni) begin
Tests: T4 T5 T1
79 1/1 aon_req_hold_q <= '0;
Tests: T4 T5 T1
80 1/1 end else if (aon_ld_req) begin
Tests: T4 T5 T1
81 1/1 aon_req_hold_q <= aon_staging_reqs_q;
Tests: T1 T2 T3
82 1/1 end else if (aon_ack) begin
Tests: T4 T5 T1
83 1/1 aon_req_hold_q <= '0;
Tests: T1 T2 T3
84 end
MISSING_ELSE
85 end
86
87 logic dst_ack;
88 prim_sync_reqack u_match_sync (
89 .clk_src_i(clk_aon_i),
90 .rst_src_ni(rst_aon_ni),
91 .clk_dst_i(clk_i),
92 .rst_dst_ni(rst_ni),
93 .req_chk_i(1'b1),
94 .src_req_i(|aon_req_hold_q),
95 .src_ack_o(aon_ack),
96 .dst_req_o(dst_ack),
97 .dst_ack_i(dst_ack)
98 );
99
100 // Holding reg after the CDC. Note that aon_req_hold_q does not change until the handshake has
101 // been completed, hence we can sample it safely upon a dst_ack pulse.
102 logic dst_ack_q;
103 logic [NumAonIntrEvents-1:0] req_hold_q;
104 always_ff @(posedge clk_i or negedge rst_ni) begin
105 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
106 1/1 req_hold_q <= '0;
Tests: T4 T5 T1
107 1/1 dst_ack_q <= 1'b0;
Tests: T4 T5 T1
108 end else begin
109 1/1 dst_ack_q <= dst_ack;
Tests: T4 T5 T1
110 1/1 if (dst_ack) begin
Tests: T4 T5 T1
111 1/1 req_hold_q <= aon_req_hold_q;
Tests: T1 T2 T3
112 end
MISSING_ELSE
113 end
114 end
115
116 // To write into interrupt status registers.
117 logic [NumKeyIntr-1:0] l2h_key_intr, h2l_key_intr;
118 logic [NumCombo-1:0] combo_intr;
119 logic ulp_wakeup_pulse;
120
121 1/1 assign {ulp_wakeup_pulse,
Tests: T4 T5 T1
122 combo_intr,
123 h2l_key_intr,
124 l2h_key_intr} = {NumAonIntrEvents{dst_ack_q}} & req_hold_q;
125
126 // Key IRQ status
127 1/1 assign {key_intr_status_o.pwrb_l2h.de,
Tests: T4 T5 T1
128 key_intr_status_o.key0_in_l2h.de,
129 key_intr_status_o.key1_in_l2h.de,
130 key_intr_status_o.key2_in_l2h.de,
131 key_intr_status_o.ac_present_l2h.de,
132 key_intr_status_o.ec_rst_l_l2h.de,
133 key_intr_status_o.flash_wp_l_l2h.de} = l2h_key_intr;
134
135 1/1 assign {key_intr_status_o.pwrb_h2l.de,
Tests: T4 T5 T1
136 key_intr_status_o.key0_in_h2l.de,
137 key_intr_status_o.key1_in_h2l.de,
138 key_intr_status_o.key2_in_h2l.de,
139 key_intr_status_o.ac_present_h2l.de,
140 key_intr_status_o.ec_rst_l_h2l.de,
141 key_intr_status_o.flash_wp_l_h2l.de} = h2l_key_intr;
142
143 assign key_intr_status_o.pwrb_h2l.d = 1'b1;
144 assign key_intr_status_o.pwrb_l2h.d = 1'b1;
145 assign key_intr_status_o.key0_in_h2l.d = 1'b1;
146 assign key_intr_status_o.key0_in_l2h.d = 1'b1;
147 assign key_intr_status_o.key1_in_h2l.d = 1'b1;
148 assign key_intr_status_o.key1_in_l2h.d = 1'b1;
149 assign key_intr_status_o.key2_in_h2l.d = 1'b1;
150 assign key_intr_status_o.key2_in_l2h.d = 1'b1;
151 assign key_intr_status_o.ac_present_h2l.d = 1'b1;
152 assign key_intr_status_o.ac_present_l2h.d = 1'b1;
153 assign key_intr_status_o.ec_rst_l_h2l.d = 1'b1;
154 assign key_intr_status_o.ec_rst_l_l2h.d = 1'b1;
155 assign key_intr_status_o.flash_wp_l_h2l.d = 1'b1;
156 assign key_intr_status_o.flash_wp_l_l2h.d = 1'b1;
157
158 // Combo IRQ status
159 assign combo_intr_status_o.combo0_h2l.d = 1'b1;
160 assign combo_intr_status_o.combo1_h2l.d = 1'b1;
161 assign combo_intr_status_o.combo2_h2l.d = 1'b1;
162 assign combo_intr_status_o.combo3_h2l.d = 1'b1;
163 1/1 assign {combo_intr_status_o.combo3_h2l.de,
Tests: T4 T5 T1
164 combo_intr_status_o.combo2_h2l.de,
165 combo_intr_status_o.combo1_h2l.de,
166 combo_intr_status_o.combo0_h2l.de} = combo_intr;
167
168 // ULP wakeup status
169 assign ulp_status_o.d = 1'b1;
170 1/1 assign ulp_status_o.de = ulp_wakeup_pulse;
Tests: T4 T5 T1
171
172 // Aggregate interrupt event statuses.
173 logic intr_event_status;
174 1/1 assign intr_event_status = |{ulp_status_i,
Tests: T4 T5 T1
Cond Coverage for Module :
sysrst_ctrl_intr
| Total | Covered | Percent |
|---|
| Conditions | 5 | 5 | 100.00 |
| Logical | 5 | 5 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 74
EXPRESSION ((aon_req_hold_q == '0) && ((|aon_staging_reqs_q)))
-----------1---------- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T6 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 74
SUB-EXPRESSION (aon_req_hold_q == '0)
-----------1----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Module :
sysrst_ctrl_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
11 |
11 |
100.00 |
| IF |
61 |
4 |
4 |
100.00 |
| IF |
78 |
4 |
4 |
100.00 |
| IF |
105 |
3 |
3 |
100.00 |
61 if (!rst_aon_ni) begin
-1-
62 aon_staging_reqs_q <= '0;
==>
63 end else if (aon_ld_req) begin
-2-
64 aon_staging_reqs_q <= aon_reqs;
==>
65 end else if (|aon_reqs) begin
-3-
66 aon_staging_reqs_q <= aon_staging_reqs_q | aon_reqs;
==>
67 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T4,T5,T1 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T4,T5,T1 |
78 if (!rst_aon_ni) begin
-1-
79 aon_req_hold_q <= '0;
==>
80 end else if (aon_ld_req) begin
-2-
81 aon_req_hold_q <= aon_staging_reqs_q;
==>
82 end else if (aon_ack) begin
-3-
83 aon_req_hold_q <= '0;
==>
84 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T4,T5,T1 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T4,T5,T1 |
105 if (!rst_ni) begin
-1-
106 req_hold_q <= '0;
==>
107 dst_ack_q <= 1'b0;
108 end else begin
109 dst_ack_q <= dst_ack;
110 if (dst_ack) begin
-2-
111 req_hold_q <= aon_req_hold_q;
==>
112 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T1 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T5,T1 |
