Module Definition
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Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1256237361 9668 0 0
auto_block_debounce_ctl_rd_A 1256237361 1386 0 0
auto_block_out_ctl_rd_A 1256237361 2059 0 0
com_det_ctl_0_rd_A 1256237361 3218 0 0
com_det_ctl_1_rd_A 1256237361 3254 0 0
com_det_ctl_2_rd_A 1256237361 3379 0 0
com_det_ctl_3_rd_A 1256237361 3217 0 0
com_out_ctl_0_rd_A 1256237361 3830 0 0
com_out_ctl_1_rd_A 1256237361 3731 0 0
com_out_ctl_2_rd_A 1256237361 3682 0 0
com_out_ctl_3_rd_A 1256237361 3943 0 0
com_pre_det_ctl_0_rd_A 1256237361 986 0 0
com_pre_det_ctl_1_rd_A 1256237361 1165 0 0
com_pre_det_ctl_2_rd_A 1256237361 1015 0 0
com_pre_det_ctl_3_rd_A 1256237361 997 0 0
com_pre_sel_ctl_0_rd_A 1256237361 3913 0 0
com_pre_sel_ctl_1_rd_A 1256237361 3818 0 0
com_pre_sel_ctl_2_rd_A 1256237361 4107 0 0
com_pre_sel_ctl_3_rd_A 1256237361 4021 0 0
com_sel_ctl_0_rd_A 1256237361 3906 0 0
com_sel_ctl_1_rd_A 1256237361 3881 0 0
com_sel_ctl_2_rd_A 1256237361 3830 0 0
com_sel_ctl_3_rd_A 1256237361 4031 0 0
ec_rst_ctl_rd_A 1256237361 1984 0 0
intr_enable_rd_A 1256237361 1849 0 0
key_intr_ctl_rd_A 1256237361 3232 0 0
key_intr_debounce_ctl_rd_A 1256237361 1101 0 0
key_invert_ctl_rd_A 1256237361 4098 0 0
pin_allowed_ctl_rd_A 1256237361 4518 0 0
pin_out_ctl_rd_A 1256237361 2947 0 0
pin_out_value_rd_A 1256237361 3164 0 0
regwen_rd_A 1256237361 1453 0 0
ulp_ac_debounce_ctl_rd_A 1256237361 950 0 0
ulp_ctl_rd_A 1256237361 1208 0 0
ulp_lid_debounce_ctl_rd_A 1256237361 1135 0 0
ulp_pwrb_debounce_ctl_rd_A 1256237361 1053 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 9668 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T49 0 18 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T80 0 2 0 0
T87 202652 2 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T101 0 21 0 0
T114 0 15 0 0
T133 0 9 0 0
T136 0 7 0 0
T140 0 8 0 0
T231 46716 0 0 0
T238 0 7 0 0
T295 51985 0 0 0
T296 0 11 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1386 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T59 0 11 0 0
T61 0 7 0 0
T64 0 4 0 0
T75 100764 0 0 0
T87 202652 8 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T120 0 11 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T297 0 10 0 0
T298 0 11 0 0
T299 0 21 0 0
T300 0 7 0 0
T301 0 3 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 2059 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T59 0 8 0 0
T61 0 8 0 0
T64 0 16 0 0
T75 100764 0 0 0
T87 202652 4 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T120 0 12 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T297 0 9 0 0
T298 0 4 0 0
T299 0 6 0 0
T300 0 4 0 0
T302 0 7 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3218 0 0
T41 0 69 0 0
T42 0 80 0 0
T44 518669 0 0 0
T47 0 89 0 0
T54 134842 36 0 0
T78 414463 0 0 0
T92 882253 0 0 0
T94 0 51 0 0
T96 0 95 0 0
T122 0 39 0 0
T296 523570 0 0 0
T298 0 15 0 0
T299 0 11 0 0
T303 0 13 0 0
T304 202307 0 0 0
T305 193154 0 0 0
T306 77404 0 0 0
T307 60623 0 0 0
T308 65829 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3254 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 97 0 0
T42 0 47 0 0
T47 0 64 0 0
T54 0 68 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 16 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 46 0 0
T96 0 112 0 0
T122 0 52 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 13 0 0
T299 0 10 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3379 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 70 0 0
T42 0 79 0 0
T47 0 92 0 0
T54 0 41 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 14 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 54 0 0
T96 0 93 0 0
T122 0 56 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 4 0 0
T299 0 11 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3217 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 60 0 0
T42 0 67 0 0
T47 0 74 0 0
T54 0 31 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 12 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 43 0 0
T96 0 92 0 0
T122 0 47 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 19 0 0
T299 0 23 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3830 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 75 0 0
T42 0 66 0 0
T47 0 78 0 0
T54 0 53 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 18 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 52 0 0
T96 0 58 0 0
T122 0 40 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 6 0 0
T299 0 14 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3731 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 68 0 0
T42 0 68 0 0
T47 0 83 0 0
T54 0 58 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 11 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 46 0 0
T96 0 85 0 0
T122 0 38 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 10 0 0
T299 0 11 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3682 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 82 0 0
T42 0 37 0 0
T47 0 49 0 0
T54 0 42 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 16 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 40 0 0
T96 0 117 0 0
T122 0 51 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 11 0 0
T299 0 6 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3943 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 57 0 0
T42 0 77 0 0
T47 0 49 0 0
T54 0 41 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 9 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 43 0 0
T96 0 95 0 0
T122 0 47 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 18 0 0
T299 0 24 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 986 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 13 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 30 0 0
T157 0 15 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 6 0 0
T299 0 5 0 0
T303 0 4 0 0
T309 0 14 0 0
T310 0 14 0 0
T311 0 24 0 0
T312 0 13 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1165 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 15 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 37 0 0
T157 0 17 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 3 0 0
T299 0 21 0 0
T303 0 23 0 0
T309 0 29 0 0
T310 0 14 0 0
T311 0 29 0 0
T312 0 24 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1015 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 17 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 38 0 0
T157 0 25 0 0
T231 46716 0 0 0
T281 0 9 0 0
T295 51985 0 0 0
T298 0 7 0 0
T303 0 23 0 0
T309 0 16 0 0
T310 0 6 0 0
T311 0 40 0 0
T312 0 22 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 997 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 16 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 17 0 0
T157 0 15 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 11 0 0
T299 0 9 0 0
T303 0 31 0 0
T309 0 27 0 0
T310 0 20 0 0
T311 0 29 0 0
T312 0 13 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3913 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 52 0 0
T42 0 60 0 0
T47 0 76 0 0
T54 0 45 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 3 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 48 0 0
T96 0 85 0 0
T122 0 49 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 17 0 0
T303 0 4 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3818 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 69 0 0
T42 0 74 0 0
T47 0 74 0 0
T54 0 69 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 3 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 42 0 0
T96 0 78 0 0
T122 0 28 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 5 0 0
T299 0 1 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 4107 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 79 0 0
T42 0 45 0 0
T47 0 74 0 0
T54 0 55 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 10 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 61 0 0
T96 0 87 0 0
T122 0 30 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 3 0 0
T299 0 19 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 4021 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 73 0 0
T42 0 76 0 0
T47 0 91 0 0
T54 0 71 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 9 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 38 0 0
T96 0 104 0 0
T122 0 32 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 12 0 0
T299 0 4 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3906 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 45 0 0
T42 0 73 0 0
T47 0 64 0 0
T54 0 54 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 3 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 39 0 0
T96 0 99 0 0
T122 0 34 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 10 0 0
T299 0 21 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3881 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 69 0 0
T42 0 76 0 0
T47 0 74 0 0
T54 0 42 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 2 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 47 0 0
T96 0 69 0 0
T122 0 35 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 1 0 0
T299 0 16 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3830 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 62 0 0
T42 0 81 0 0
T47 0 62 0 0
T54 0 41 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 14 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 41 0 0
T96 0 92 0 0
T122 0 21 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 13 0 0
T299 0 19 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 4031 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T41 0 62 0 0
T42 0 71 0 0
T47 0 63 0 0
T54 0 53 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 13 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T94 0 32 0 0
T96 0 92 0 0
T122 0 37 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 11 0 0
T299 0 13 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1984 0 0
T24 208414 0 0 0
T30 210149 0 0 0
T32 57069 0 0 0
T35 0 2 0 0
T41 0 39 0 0
T54 0 30 0 0
T74 167105 6 0 0
T87 202652 5 0 0
T88 44726 0 0 0
T92 0 3 0 0
T93 0 1 0 0
T94 0 24 0 0
T95 0 6 0 0
T103 0 9 0 0
T113 112609 0 0 0
T194 26538 0 0 0
T195 21716 0 0 0
T295 51985 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1849 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T61 0 30 0 0
T75 100764 0 0 0
T87 202652 4 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 38 0 0
T157 0 19 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 17 0 0
T299 0 19 0 0
T303 0 7 0 0
T309 0 10 0 0
T310 0 12 0 0
T311 0 53 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3232 0 0
T6 57417 2 0 0
T9 0 5 0 0
T11 0 2 0 0
T24 208414 0 0 0
T26 247843 0 0 0
T30 210149 0 0 0
T32 57069 0 0 0
T35 0 72 0 0
T52 0 1 0 0
T74 167105 0 0 0
T87 0 8 0 0
T109 0 8 0 0
T113 112609 0 0 0
T192 0 7 0 0
T193 194124 0 0 0
T194 26538 0 0 0
T195 21716 0 0 0
T298 0 17 0 0
T299 0 14 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1101 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 3 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 19 0 0
T157 0 19 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 10 0 0
T299 0 7 0 0
T303 0 21 0 0
T309 0 29 0 0
T310 0 7 0 0
T311 0 53 0 0
T312 0 31 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 4098 0 0
T9 187384 0 0 0
T27 246771 82 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 5 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T146 0 71 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 7 0 0
T299 0 19 0 0
T303 0 8 0 0
T313 0 34 0 0
T314 0 56 0 0
T315 0 70 0 0
T316 0 80 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 4518 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 6 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T106 0 58 0 0
T155 0 77 0 0
T157 0 19 0 0
T227 0 82 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 22 0 0
T299 0 7 0 0
T303 0 15 0 0
T317 0 66 0 0
T318 0 61 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 2947 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 3 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T106 0 49 0 0
T155 0 69 0 0
T157 0 11 0 0
T227 0 60 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 10 0 0
T299 0 11 0 0
T303 0 15 0 0
T317 0 68 0 0
T318 0 80 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 3164 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 15 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T106 0 31 0 0
T155 0 51 0 0
T157 0 27 0 0
T227 0 68 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 21 0 0
T299 0 5 0 0
T303 0 38 0 0
T317 0 67 0 0
T318 0 52 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1453 0 0
T9 187384 0 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T56 211094 0 0 0
T75 100764 0 0 0
T87 202652 7 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T155 0 29 0 0
T157 0 16 0 0
T231 46716 0 0 0
T295 51985 0 0 0
T298 0 13 0 0
T299 0 12 0 0
T303 0 18 0 0
T309 0 9 0 0
T310 0 13 0 0
T311 0 42 0 0
T312 0 19 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 950 0 0
T24 208414 2 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T32 57069 0 0 0
T56 211094 0 0 0
T70 0 6 0 0
T71 0 7 0 0
T72 0 4 0 0
T75 100764 0 0 0
T77 0 3 0 0
T78 0 7 0 0
T87 202652 2 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T107 0 3 0 0
T295 51985 0 0 0
T298 0 14 0 0
T319 0 1 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1208 0 0
T24 208414 7 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T32 57069 0 0 0
T56 211094 0 0 0
T70 0 8 0 0
T71 0 9 0 0
T72 0 10 0 0
T75 100764 0 0 0
T77 0 3 0 0
T87 202652 24 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T107 0 14 0 0
T295 51985 0 0 0
T298 0 13 0 0
T299 0 10 0 0
T319 0 8 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1135 0 0
T24 208414 6 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T32 57069 0 0 0
T56 211094 0 0 0
T70 0 8 0 0
T71 0 5 0 0
T72 0 8 0 0
T75 100764 0 0 0
T77 0 8 0 0
T87 202652 14 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T107 0 7 0 0
T295 51985 0 0 0
T298 0 3 0 0
T299 0 6 0 0
T319 0 9 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1256237361 1053 0 0
T24 208414 1 0 0
T27 246771 0 0 0
T31 168771 0 0 0
T32 57069 0 0 0
T56 211094 0 0 0
T70 0 2 0 0
T71 0 16 0 0
T72 0 6 0 0
T75 100764 0 0 0
T77 0 11 0 0
T87 202652 9 0 0
T88 44726 0 0 0
T89 241321 0 0 0
T107 0 6 0 0
T295 51985 0 0 0
T298 0 17 0 0
T299 0 9 0 0
T319 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%