Line Coverage for Instance : tb.dut.u_reg.u_intr_state.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 1 | 50.00 |
| CONT_ASSIGN | 43 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 51 | 0 | 0 | |
| CONT_ASSIGN | 52 | 0 | 0 | |
| CONT_ASSIGN | 53 | 0 | 0 | |
42 end else if (SwAccess == SwAccessRO) begin : gen_ro
43 0/1 ==> assign wr_en = de;
44 1/1 assign wr_data = d;
Tests: T4 T5 T1
45 // Unused we, wd, q - Prevent lint errors.
46 logic unused_we;
47 logic [DW-1:0] unused_wd;
48 logic [DW-1:0] unused_q;
49 //VCS coverage off
50 // pragma coverage off
51 unreachable assign unused_we = we;
52 unreachable assign unused_wd = wd;
53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T4 T5 T1
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T4,T5,T1 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
112 end else if (SwAccess == SwAccessW0C) begin : gen_w0c
113 1/1 assign wr_en = we | de;
Tests: T36 T37 T38
114 if (Mubi) begin : gen_mubi
115 if (DW == 4) begin : gen_mubi4
116 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
117 (we ? prim_mubi_pkg::mubi4_t'(wd) :
118 prim_mubi_pkg::MuBi4True));
119 end else if (DW == 8) begin : gen_mubi8
120 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
121 (we ? prim_mubi_pkg::mubi8_t'(wd) :
122 prim_mubi_pkg::MuBi8True));
123 end else if (DW == 12) begin : gen_mubi12
124 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
125 (we ? prim_mubi_pkg::mubi12_t'(wd) :
126 prim_mubi_pkg::MuBi12True));
127 end else if (DW == 16) begin : gen_mubi16
128 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
129 (we ? prim_mubi_pkg::mubi16_t'(wd) :
130 prim_mubi_pkg::MuBi16True));
131 end else begin : gen_invalid_mubi
132 $error("%m: Invalid width for MuBi");
133 end
134 end else begin : gen_non_mubi
135 1/1 assign wr_data = (de ? d : q) & (we ? wd : '1);
Tests: T4 T5 T1
Cond Coverage for Instance : tb.dut.u_reg.u_regwen.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 113
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T36,T37,T38 |
LINE 135
EXPRESSION ((de ? d : q) & (we ? wd : '1))
------1----- -------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T36,T39,T40 |
| 1 | 0 | Covered | T36,T39,T40 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 135
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Unreachable | |
LINE 135
SUB-EXPRESSION (we ? wd : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T36,T37,T38 |
Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T4 T3 T7
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T4,T3,T7 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T3,T7 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T3,T7 |
Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T3,T7 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T2 T24 T10
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T24,T10 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T10 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T2 T24 T10
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T24,T10 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T10 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T2 T24 T10
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T24,T10 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T24,T10 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T24,T10 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T2 T10 T25
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T10,T25 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T10,T25 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_ulp_status.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T4 T5 T1
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T4 T5 T1
Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Covered | T2,T10,T25 |
| 1 | 0 | Covered | T2,T10,T25 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T2,T10,T25 |
| 1 | 1 | Covered | T2,T10,T25 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T25 |
Line Coverage for Instance : tb.dut.u_reg.u_wkup_status.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
87 // If both try to set/clr at the same bit pos, SW wins.
88 1/1 assign wr_en = we | de;
Tests: T1 T2 T3
89 if (Mubi) begin : gen_mubi
90 if (DW == 4) begin : gen_mubi4
91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q),
92 (we ? prim_mubi_pkg::mubi4_t'(~wd) :
93 prim_mubi_pkg::MuBi4True));
94 end else if (DW == 8) begin : gen_mubi8
95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q),
96 (we ? prim_mubi_pkg::mubi8_t'(~wd) :
97 prim_mubi_pkg::MuBi8True));
98 end else if (DW == 12) begin : gen_mubi12
99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q),
100 (we ? prim_mubi_pkg::mubi12_t'(~wd) :
101 prim_mubi_pkg::MuBi12True));
102 end else if (DW == 16) begin : gen_mubi16
103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q),
104 (we ? prim_mubi_pkg::mubi16_t'(~wd) :
105 prim_mubi_pkg::MuBi16True));
106 end else begin : gen_invalid_mubi
107 $error("%m: Invalid width for MuBi");
108 end
109 end else begin : gen_non_mubi
110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1);
Tests: T4 T5 T1
Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 88
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T10,T19 |
LINE 110
EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
------1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T2,T10,T19 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (de ? d : q)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T2,T3 |
LINE 110
SUB-EXPRESSION (we ? ((~wd)) : '1)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T10,T19 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key0_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key1_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_key2_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_in.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_pwrb_out.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_ac_present.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_bat_disable.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_lid_open.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T13 T26 T27
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T13,T26,T27 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T13,T26,T27 |
Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_z3_wakeup.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T13,T26,T27 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T5 T13 T28
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T13,T28 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_bat_disable_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T13,T28 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T5 T13 T28
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T13,T28 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_ec_rst_l_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T13,T28 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T5 T13 T28
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T13,T28 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_pwrb_out_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T13,T28 |
| 0 |
Covered |
T4,T5,T1 |
Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 33 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33 1/1 assign wr_en = we | de;
Tests: T5 T13 T28
34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
Tests: T4 T5 T1
35 // Unused q - Prevent lint errors.
36 logic [DW-1:0] unused_q;
37 //VCS coverage off
38 // pragma coverage off
39 unreachable assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
| Total | Covered | Percent |
|---|
| Conditions | 6 | 6 | 100.00 |
| Logical | 6 | 6 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 33
EXPRESSION (we | de)
-1 -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T1 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T5,T13,T28 |
LINE 34
EXPRESSION ((we == 1'b1) ? wd : d)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
LINE 34
SUB-EXPRESSION (we == 1'b1)
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T5,T13,T28 |
Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_key0_out_0.wr_en_data_arb
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| TERNARY |
34 |
2 |
2 |
100.00 |
34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T13,T28 |
| 0 |
Covered |
T4,T5,T1 |
