| T267 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3766399635 |
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Sep 24 09:17:18 PM UTC 24 |
Sep 24 09:18:23 PM UTC 24 |
87127215413 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.415286745 |
|
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Sep 24 09:18:07 PM UTC 24 |
Sep 24 09:18:27 PM UTC 24 |
329622610758 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2755169699 |
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Sep 24 09:18:22 PM UTC 24 |
Sep 24 09:18:28 PM UTC 24 |
2617413254 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3696328378 |
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Sep 24 09:18:16 PM UTC 24 |
Sep 24 09:18:31 PM UTC 24 |
2454089707 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1898548089 |
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Sep 24 09:18:25 PM UTC 24 |
Sep 24 09:18:33 PM UTC 24 |
3190704732 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3865844564 |
|
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Sep 24 09:18:28 PM UTC 24 |
Sep 24 09:18:35 PM UTC 24 |
6117928583 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.2777106833 |
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Sep 24 09:18:21 PM UTC 24 |
Sep 24 09:18:35 PM UTC 24 |
2255313135 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.762564577 |
|
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Sep 24 09:18:10 PM UTC 24 |
Sep 24 09:18:37 PM UTC 24 |
4139548471 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.874808287 |
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Sep 24 09:18:22 PM UTC 24 |
Sep 24 09:18:37 PM UTC 24 |
2512026844 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1929027001 |
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Sep 24 09:11:51 PM UTC 24 |
Sep 24 09:18:37 PM UTC 24 |
268499545501 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.671004067 |
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Sep 24 09:18:31 PM UTC 24 |
Sep 24 09:18:40 PM UTC 24 |
3624191165 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1353632950 |
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Sep 24 09:18:38 PM UTC 24 |
Sep 24 09:18:40 PM UTC 24 |
2581855259 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.4207106048 |
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Sep 24 09:18:38 PM UTC 24 |
Sep 24 09:18:42 PM UTC 24 |
2024074664 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1990366214 |
|
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Sep 24 09:18:38 PM UTC 24 |
Sep 24 09:18:43 PM UTC 24 |
2114640072 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.201372371 |
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Sep 24 09:18:36 PM UTC 24 |
Sep 24 09:18:44 PM UTC 24 |
5008350393 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.1004674979 |
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Sep 24 09:18:41 PM UTC 24 |
Sep 24 09:18:44 PM UTC 24 |
2572877524 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1587348434 |
|
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Sep 24 09:17:54 PM UTC 24 |
Sep 24 09:18:45 PM UTC 24 |
13269626794 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2713397520 |
|
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Sep 24 09:18:43 PM UTC 24 |
Sep 24 09:18:47 PM UTC 24 |
2623069020 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.947656848 |
|
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Sep 24 09:18:44 PM UTC 24 |
Sep 24 09:18:49 PM UTC 24 |
4566216639 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.4029340911 |
|
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Sep 24 09:18:09 PM UTC 24 |
Sep 24 09:18:51 PM UTC 24 |
55056049926 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.2861750699 |
|
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Sep 24 09:17:36 PM UTC 24 |
Sep 24 09:18:53 PM UTC 24 |
951971085914 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3779057116 |
|
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Sep 24 09:18:41 PM UTC 24 |
Sep 24 09:18:54 PM UTC 24 |
2110622963 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.1357455041 |
|
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Sep 24 09:18:49 PM UTC 24 |
Sep 24 09:18:55 PM UTC 24 |
3422451775 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2264999291 |
|
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Sep 24 09:18:46 PM UTC 24 |
Sep 24 09:18:59 PM UTC 24 |
3133813532 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3175290562 |
|
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Sep 24 09:18:24 PM UTC 24 |
Sep 24 09:19:00 PM UTC 24 |
11869801586 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.1667626473 |
|
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Sep 24 09:18:56 PM UTC 24 |
Sep 24 09:19:02 PM UTC 24 |
2466981657 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3367386924 |
|
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Sep 24 09:12:48 PM UTC 24 |
Sep 24 09:19:02 PM UTC 24 |
105063415727 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1690021684 |
|
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Sep 24 09:18:54 PM UTC 24 |
Sep 24 09:19:02 PM UTC 24 |
2016741252 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3261350253 |
|
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Sep 24 09:16:04 PM UTC 24 |
Sep 24 09:19:03 PM UTC 24 |
67489186351 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1776078509 |
|
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Sep 24 09:18:59 PM UTC 24 |
Sep 24 09:19:04 PM UTC 24 |
2162479454 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2016721768 |
|
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Sep 24 09:19:02 PM UTC 24 |
Sep 24 09:19:05 PM UTC 24 |
2538866003 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1518361581 |
|
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Sep 24 09:18:12 PM UTC 24 |
Sep 24 09:19:09 PM UTC 24 |
12682760822 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.3023592691 |
|
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Sep 24 09:18:55 PM UTC 24 |
Sep 24 09:19:09 PM UTC 24 |
2112371152 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.633158430 |
|
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Sep 24 09:19:03 PM UTC 24 |
Sep 24 09:19:09 PM UTC 24 |
3000537178 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.982612221 |
|
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Sep 24 09:19:04 PM UTC 24 |
Sep 24 09:19:12 PM UTC 24 |
6180444967 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2142115223 |
|
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Sep 24 09:18:33 PM UTC 24 |
Sep 24 09:19:14 PM UTC 24 |
47643040044 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.195197834 |
|
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Sep 24 09:19:04 PM UTC 24 |
Sep 24 09:19:15 PM UTC 24 |
3501904540 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.765898684 |
|
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Sep 24 09:18:09 PM UTC 24 |
Sep 24 09:19:16 PM UTC 24 |
46345250318 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.849969603 |
|
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Sep 24 09:19:06 PM UTC 24 |
Sep 24 09:19:17 PM UTC 24 |
3415955752 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.216454198 |
|
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Sep 24 09:19:13 PM UTC 24 |
Sep 24 09:19:17 PM UTC 24 |
2031352760 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.2741866908 |
|
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Sep 24 09:19:15 PM UTC 24 |
Sep 24 09:19:18 PM UTC 24 |
2129946149 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.1145956894 |
|
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Sep 24 09:19:16 PM UTC 24 |
Sep 24 09:19:20 PM UTC 24 |
2449766894 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.219811342 |
|
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Sep 24 09:19:03 PM UTC 24 |
Sep 24 09:19:21 PM UTC 24 |
2610805974 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3167175324 |
|
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Sep 24 09:19:10 PM UTC 24 |
Sep 24 09:19:21 PM UTC 24 |
6827214441 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.9425323 |
|
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Sep 24 09:18:50 PM UTC 24 |
Sep 24 09:19:21 PM UTC 24 |
27604641253 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.636264516 |
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Sep 24 09:18:52 PM UTC 24 |
Sep 24 09:19:25 PM UTC 24 |
11592847262 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.250988456 |
|
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Sep 24 09:19:18 PM UTC 24 |
Sep 24 09:19:26 PM UTC 24 |
2611273688 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.252737831 |
|
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Sep 24 09:19:10 PM UTC 24 |
Sep 24 09:19:27 PM UTC 24 |
4449978331 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.61899941 |
|
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Sep 24 09:19:19 PM UTC 24 |
Sep 24 09:19:27 PM UTC 24 |
2926108843 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1378985323 |
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Sep 24 09:19:18 PM UTC 24 |
Sep 24 09:19:28 PM UTC 24 |
2513181254 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.2903941519 |
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Sep 24 09:18:46 PM UTC 24 |
Sep 24 09:20:29 PM UTC 24 |
107216969006 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1648382604 |
|
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Sep 24 09:19:17 PM UTC 24 |
Sep 24 09:19:29 PM UTC 24 |
2108651948 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1283428569 |
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Sep 24 09:17:34 PM UTC 24 |
Sep 24 09:19:30 PM UTC 24 |
74088635363 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.3598266989 |
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Sep 24 09:19:23 PM UTC 24 |
Sep 24 09:19:31 PM UTC 24 |
4185636188 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.928931978 |
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Sep 24 09:19:05 PM UTC 24 |
Sep 24 09:19:33 PM UTC 24 |
41427281153 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2503669671 |
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Sep 24 09:19:29 PM UTC 24 |
Sep 24 09:19:34 PM UTC 24 |
2136040481 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3121158044 |
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Sep 24 09:19:29 PM UTC 24 |
Sep 24 09:19:35 PM UTC 24 |
2534073380 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3384857782 |
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Sep 24 09:19:20 PM UTC 24 |
Sep 24 09:19:35 PM UTC 24 |
3825784535 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.1247899821 |
|
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Sep 24 09:18:45 PM UTC 24 |
Sep 24 09:19:36 PM UTC 24 |
14733287936 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2204460785 |
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Sep 24 09:19:09 PM UTC 24 |
Sep 24 09:19:37 PM UTC 24 |
26263459728 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.1534321243 |
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Sep 24 09:18:53 PM UTC 24 |
Sep 24 09:19:37 PM UTC 24 |
12177103694 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1236511103 |
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Sep 24 09:19:29 PM UTC 24 |
Sep 24 09:19:37 PM UTC 24 |
2187402607 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.1279256574 |
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Sep 24 09:19:32 PM UTC 24 |
Sep 24 09:19:38 PM UTC 24 |
3015860780 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.265061005 |
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Sep 24 09:19:32 PM UTC 24 |
Sep 24 09:19:38 PM UTC 24 |
2624193389 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4104542980 |
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Sep 24 09:19:34 PM UTC 24 |
Sep 24 09:19:38 PM UTC 24 |
3953571375 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.1174568207 |
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Sep 24 09:19:28 PM UTC 24 |
Sep 24 09:19:39 PM UTC 24 |
2008854558 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.340464245 |
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Sep 24 09:19:39 PM UTC 24 |
Sep 24 09:19:42 PM UTC 24 |
2132737379 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2658538147 |
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Sep 24 09:19:27 PM UTC 24 |
Sep 24 09:19:43 PM UTC 24 |
9136124211 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3191972595 |
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Sep 24 09:19:29 PM UTC 24 |
Sep 24 09:19:43 PM UTC 24 |
2449312551 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3861902155 |
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Sep 24 09:19:40 PM UTC 24 |
Sep 24 09:19:45 PM UTC 24 |
2638445168 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.4121472650 |
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Sep 24 09:19:38 PM UTC 24 |
Sep 24 09:19:45 PM UTC 24 |
2011742424 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.2960048471 |
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Sep 24 09:19:39 PM UTC 24 |
Sep 24 09:19:46 PM UTC 24 |
2157495633 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1560937007 |
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Sep 24 09:19:39 PM UTC 24 |
Sep 24 09:19:46 PM UTC 24 |
2488396220 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2882107734 |
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Sep 24 09:19:26 PM UTC 24 |
Sep 24 09:19:47 PM UTC 24 |
44475844484 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.1431181379 |
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Sep 24 09:16:57 PM UTC 24 |
Sep 24 09:19:49 PM UTC 24 |
58923952694 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.1950701447 |
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Sep 24 09:19:40 PM UTC 24 |
Sep 24 09:19:49 PM UTC 24 |
2507468229 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1357312612 |
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Sep 24 09:19:44 PM UTC 24 |
Sep 24 09:19:50 PM UTC 24 |
2990862247 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3419288988 |
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Sep 24 09:19:46 PM UTC 24 |
Sep 24 09:19:50 PM UTC 24 |
3023267623 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2818921941 |
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Sep 24 09:19:37 PM UTC 24 |
Sep 24 09:19:53 PM UTC 24 |
26770549297 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.62862980 |
|
|
Sep 24 09:19:48 PM UTC 24 |
Sep 24 09:19:55 PM UTC 24 |
2020536757 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.712288504 |
|
|
Sep 24 09:17:02 PM UTC 24 |
Sep 24 09:19:55 PM UTC 24 |
41588261931 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.2946973857 |
|
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Sep 24 09:19:51 PM UTC 24 |
Sep 24 09:19:57 PM UTC 24 |
2523375581 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1158264916 |
|
|
Sep 24 09:19:36 PM UTC 24 |
Sep 24 09:20:00 PM UTC 24 |
4897865007 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.183863028 |
|
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Sep 24 09:19:43 PM UTC 24 |
Sep 24 09:20:00 PM UTC 24 |
3244271235 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3366758360 |
|
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Sep 24 09:12:30 PM UTC 24 |
Sep 24 09:20:00 PM UTC 24 |
210456316928 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.182164775 |
|
|
Sep 24 09:19:50 PM UTC 24 |
Sep 24 09:20:01 PM UTC 24 |
2114989530 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.456528241 |
|
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Sep 24 09:17:21 PM UTC 24 |
Sep 24 09:20:02 PM UTC 24 |
65355761857 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2650808826 |
|
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Sep 24 09:19:51 PM UTC 24 |
Sep 24 09:20:02 PM UTC 24 |
2460548379 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2757512835 |
|
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Sep 24 09:19:44 PM UTC 24 |
Sep 24 09:20:03 PM UTC 24 |
3580196844 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.710632499 |
|
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Sep 24 09:18:37 PM UTC 24 |
Sep 24 09:20:05 PM UTC 24 |
388945238500 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4238217693 |
|
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Sep 24 09:19:51 PM UTC 24 |
Sep 24 09:20:06 PM UTC 24 |
2138055172 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3872222195 |
|
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Sep 24 09:19:57 PM UTC 24 |
Sep 24 09:20:07 PM UTC 24 |
3058589054 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.929616579 |
|
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Sep 24 09:19:55 PM UTC 24 |
Sep 24 09:20:08 PM UTC 24 |
4064556845 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2943536920 |
|
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Sep 24 09:19:46 PM UTC 24 |
Sep 24 09:20:08 PM UTC 24 |
34803336721 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.28634514 |
|
|
Sep 24 09:20:06 PM UTC 24 |
Sep 24 09:20:09 PM UTC 24 |
2563723068 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2682238158 |
|
|
Sep 24 09:20:02 PM UTC 24 |
Sep 24 09:20:10 PM UTC 24 |
2865843293 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.933723348 |
|
|
Sep 24 09:19:54 PM UTC 24 |
Sep 24 09:20:10 PM UTC 24 |
2611642249 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2673868488 |
|
|
Sep 24 09:20:03 PM UTC 24 |
Sep 24 09:20:11 PM UTC 24 |
2010312529 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1058814203 |
|
|
Sep 24 09:20:07 PM UTC 24 |
Sep 24 09:20:11 PM UTC 24 |
2178832731 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.3986901574 |
|
|
Sep 24 09:20:04 PM UTC 24 |
Sep 24 09:20:12 PM UTC 24 |
2120625345 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.4127988737 |
|
|
Sep 24 09:20:08 PM UTC 24 |
Sep 24 09:20:12 PM UTC 24 |
2540571605 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3909177638 |
|
|
Sep 24 09:19:56 PM UTC 24 |
Sep 24 09:20:13 PM UTC 24 |
3801063316 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2633819403 |
|
|
Sep 24 09:20:12 PM UTC 24 |
Sep 24 09:20:16 PM UTC 24 |
2650111579 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3721695530 |
|
|
Sep 24 09:20:10 PM UTC 24 |
Sep 24 09:20:19 PM UTC 24 |
4888647562 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2464951429 |
|
|
Sep 24 09:20:03 PM UTC 24 |
Sep 24 09:20:19 PM UTC 24 |
7123359330 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2652303341 |
|
|
Sep 24 09:20:13 PM UTC 24 |
Sep 24 09:20:20 PM UTC 24 |
4591999203 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2413817801 |
|
|
Sep 24 09:20:13 PM UTC 24 |
Sep 24 09:20:21 PM UTC 24 |
2013139315 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3104819100 |
|
|
Sep 24 09:20:15 PM UTC 24 |
Sep 24 09:20:21 PM UTC 24 |
2131366490 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.475093413 |
|
|
Sep 24 09:20:09 PM UTC 24 |
Sep 24 09:20:22 PM UTC 24 |
2610477903 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.1413649638 |
|
|
Sep 24 09:20:18 PM UTC 24 |
Sep 24 09:20:23 PM UTC 24 |
2474958746 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.884876267 |
|
|
Sep 24 09:20:20 PM UTC 24 |
Sep 24 09:20:25 PM UTC 24 |
2262637637 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1708563467 |
|
|
Sep 24 09:20:20 PM UTC 24 |
Sep 24 09:20:28 PM UTC 24 |
2518523555 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3702986294 |
|
|
Sep 24 09:20:22 PM UTC 24 |
Sep 24 09:20:28 PM UTC 24 |
3883195308 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.757116044 |
|
|
Sep 24 09:20:21 PM UTC 24 |
Sep 24 09:20:30 PM UTC 24 |
2609910873 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3727062880 |
|
|
Sep 24 09:20:23 PM UTC 24 |
Sep 24 09:20:34 PM UTC 24 |
4686630409 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3883958251 |
|
|
Sep 24 09:20:25 PM UTC 24 |
Sep 24 09:20:34 PM UTC 24 |
3460875886 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.2502680543 |
|
|
Sep 24 09:20:31 PM UTC 24 |
Sep 24 09:20:36 PM UTC 24 |
2126473550 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.4089021944 |
|
|
Sep 24 09:20:30 PM UTC 24 |
Sep 24 09:20:36 PM UTC 24 |
2028200488 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3664105662 |
|
|
Sep 24 09:20:22 PM UTC 24 |
Sep 24 09:20:37 PM UTC 24 |
3420435636 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2055685238 |
|
|
Sep 24 09:20:33 PM UTC 24 |
Sep 24 09:20:38 PM UTC 24 |
2465602026 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1525440418 |
|
|
Sep 24 09:20:23 PM UTC 24 |
Sep 24 09:20:39 PM UTC 24 |
26340106329 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.325031368 |
|
|
Sep 24 09:20:35 PM UTC 24 |
Sep 24 09:20:40 PM UTC 24 |
2122420550 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.3096439993 |
|
|
Sep 24 09:20:35 PM UTC 24 |
Sep 24 09:20:41 PM UTC 24 |
2524161299 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1069051328 |
|
|
Sep 24 09:20:39 PM UTC 24 |
Sep 24 09:20:44 PM UTC 24 |
5492896058 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3968189807 |
|
|
Sep 24 09:19:28 PM UTC 24 |
Sep 24 09:20:44 PM UTC 24 |
218012243989 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.628635619 |
|
|
Sep 24 09:20:37 PM UTC 24 |
Sep 24 09:20:47 PM UTC 24 |
3248643501 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.778532071 |
|
|
Sep 24 09:20:29 PM UTC 24 |
Sep 24 09:20:49 PM UTC 24 |
4131215684 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3679384084 |
|
|
Sep 24 09:20:37 PM UTC 24 |
Sep 24 09:20:52 PM UTC 24 |
3278306121 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3817238983 |
|
|
Sep 24 09:20:30 PM UTC 24 |
Sep 24 09:20:52 PM UTC 24 |
8571161070 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.303328967 |
|
|
Sep 24 09:20:50 PM UTC 24 |
Sep 24 09:20:53 PM UTC 24 |
2136396604 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4051106694 |
|
|
Sep 24 09:20:36 PM UTC 24 |
Sep 24 09:20:53 PM UTC 24 |
2609183115 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3731773309 |
|
|
Sep 24 09:20:11 PM UTC 24 |
Sep 24 09:20:54 PM UTC 24 |
58270321332 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.928872572 |
|
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Sep 24 09:20:53 PM UTC 24 |
Sep 24 09:20:56 PM UTC 24 |
2561006052 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3782398865 |
|
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Sep 24 09:20:53 PM UTC 24 |
Sep 24 09:20:58 PM UTC 24 |
2128074082 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.4272399699 |
|
|
Sep 24 09:20:55 PM UTC 24 |
Sep 24 09:21:00 PM UTC 24 |
2626589411 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.683309758 |
|
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Sep 24 09:20:48 PM UTC 24 |
Sep 24 09:21:01 PM UTC 24 |
2016508033 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2681932207 |
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Sep 24 09:20:55 PM UTC 24 |
Sep 24 09:21:04 PM UTC 24 |
2513703039 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1566685833 |
|
|
Sep 24 09:19:48 PM UTC 24 |
Sep 24 09:21:06 PM UTC 24 |
803870626711 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1571410799 |
|
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Sep 24 09:21:56 PM UTC 24 |
Sep 24 09:22:07 PM UTC 24 |
2612057008 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2159787571 |
|
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Sep 24 09:20:57 PM UTC 24 |
Sep 24 09:21:07 PM UTC 24 |
3388236201 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3836805829 |
|
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Sep 24 09:20:45 PM UTC 24 |
Sep 24 09:21:07 PM UTC 24 |
3738535267 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1865925718 |
|
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Sep 24 09:20:12 PM UTC 24 |
Sep 24 09:21:12 PM UTC 24 |
54400595017 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2615009105 |
|
|
Sep 24 09:21:08 PM UTC 24 |
Sep 24 09:21:15 PM UTC 24 |
2112350458 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1104647958 |
|
|
Sep 24 09:21:01 PM UTC 24 |
Sep 24 09:21:18 PM UTC 24 |
2690219899 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.890558681 |
|
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Sep 24 09:21:16 PM UTC 24 |
Sep 24 09:21:19 PM UTC 24 |
2109780812 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.824883864 |
|
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Sep 24 09:20:56 PM UTC 24 |
Sep 24 09:21:19 PM UTC 24 |
3765651334 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2641683659 |
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Sep 24 09:21:08 PM UTC 24 |
Sep 24 09:21:20 PM UTC 24 |
2014666157 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1410022244 |
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Sep 24 09:20:45 PM UTC 24 |
Sep 24 09:21:23 PM UTC 24 |
8770056169 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.4068241356 |
|
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Sep 24 09:21:19 PM UTC 24 |
Sep 24 09:21:24 PM UTC 24 |
2532945533 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.384816798 |
|
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Sep 24 09:21:06 PM UTC 24 |
Sep 24 09:21:24 PM UTC 24 |
8044680212 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1370372489 |
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Sep 24 09:21:20 PM UTC 24 |
Sep 24 09:21:25 PM UTC 24 |
3576476951 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2885443836 |
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Sep 24 09:17:53 PM UTC 24 |
Sep 24 09:21:25 PM UTC 24 |
65581952111 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.2941294907 |
|
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Sep 24 09:21:20 PM UTC 24 |
Sep 24 09:21:26 PM UTC 24 |
2632682135 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.4214894667 |
|
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Sep 24 09:21:21 PM UTC 24 |
Sep 24 09:21:26 PM UTC 24 |
3495407401 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2998330339 |
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Sep 24 09:21:13 PM UTC 24 |
Sep 24 09:21:28 PM UTC 24 |
2464406991 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2354387269 |
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Sep 24 09:20:01 PM UTC 24 |
Sep 24 09:21:29 PM UTC 24 |
25332132340 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1547884374 |
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Sep 24 09:21:26 PM UTC 24 |
Sep 24 09:21:32 PM UTC 24 |
4396475622 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.710689500 |
|
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Sep 24 09:21:23 PM UTC 24 |
Sep 24 09:21:33 PM UTC 24 |
8683686015 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2492027725 |
|
|
Sep 24 09:21:29 PM UTC 24 |
Sep 24 09:21:36 PM UTC 24 |
2119814816 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1970930584 |
|
|
Sep 24 09:21:30 PM UTC 24 |
Sep 24 09:21:36 PM UTC 24 |
2463518275 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.1492477183 |
|
|
Sep 24 09:21:27 PM UTC 24 |
Sep 24 09:21:40 PM UTC 24 |
2013617840 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.2978872315 |
|
|
Sep 24 09:21:34 PM UTC 24 |
Sep 24 09:21:43 PM UTC 24 |
2514764460 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.820428101 |
|
|
Sep 24 09:21:33 PM UTC 24 |
Sep 24 09:21:44 PM UTC 24 |
2251788927 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1650547782 |
|
|
Sep 24 09:21:41 PM UTC 24 |
Sep 24 09:21:45 PM UTC 24 |
3579748486 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.869793622 |
|
|
Sep 24 09:21:37 PM UTC 24 |
Sep 24 09:21:46 PM UTC 24 |
4629795987 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.360192182 |
|
|
Sep 24 09:20:10 PM UTC 24 |
Sep 24 09:21:46 PM UTC 24 |
120218462482 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2897568018 |
|
|
Sep 24 09:21:44 PM UTC 24 |
Sep 24 09:21:48 PM UTC 24 |
3971285906 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.749368421 |
|
|
Sep 24 09:21:04 PM UTC 24 |
Sep 24 09:21:49 PM UTC 24 |
73369464989 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2810102031 |
|
|
Sep 24 09:21:37 PM UTC 24 |
Sep 24 09:21:50 PM UTC 24 |
2611845974 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2248632369 |
|
|
Sep 24 09:21:01 PM UTC 24 |
Sep 24 09:21:50 PM UTC 24 |
77801170630 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.972961680 |
|
|
Sep 24 09:21:46 PM UTC 24 |
Sep 24 09:21:51 PM UTC 24 |
3181058690 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3689540825 |
|
|
Sep 24 09:21:50 PM UTC 24 |
Sep 24 09:21:55 PM UTC 24 |
2132714394 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1173395996 |
|
|
Sep 24 09:21:26 PM UTC 24 |
Sep 24 09:21:55 PM UTC 24 |
6120346412 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.123018300 |
|
|
Sep 24 09:15:04 PM UTC 24 |
Sep 24 09:21:57 PM UTC 24 |
136998588917 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.4125097220 |
|
|
Sep 24 09:21:56 PM UTC 24 |
Sep 24 09:22:05 PM UTC 24 |
2510454093 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1609082440 |
|
|
Sep 24 09:22:03 PM UTC 24 |
Sep 24 09:22:08 PM UTC 24 |
2478546539 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1298161962 |
|
|
Sep 24 09:21:50 PM UTC 24 |
Sep 24 09:21:57 PM UTC 24 |
2014249023 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2627386502 |
|
|
Sep 24 09:19:22 PM UTC 24 |
Sep 24 09:22:00 PM UTC 24 |
74949405156 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.2303959475 |
|
|
Sep 24 09:21:52 PM UTC 24 |
Sep 24 09:22:00 PM UTC 24 |
2237093069 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.225181845 |
|
|
Sep 24 09:21:26 PM UTC 24 |
Sep 24 09:22:02 PM UTC 24 |
29613702945 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1740059778 |
|
|
Sep 24 09:21:47 PM UTC 24 |
Sep 24 09:22:02 PM UTC 24 |
6541570779 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.3184943809 |
|
|
Sep 24 09:20:41 PM UTC 24 |
Sep 24 09:22:03 PM UTC 24 |
199578499879 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.712163067 |
|
|
Sep 24 09:21:51 PM UTC 24 |
Sep 24 09:22:04 PM UTC 24 |
2463127382 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.684199904 |
|
|
Sep 24 09:22:01 PM UTC 24 |
Sep 24 09:22:07 PM UTC 24 |
6808495863 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2949073125 |
|
|
Sep 24 09:21:58 PM UTC 24 |
Sep 24 09:22:09 PM UTC 24 |
4185351296 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.27844032 |
|
|
Sep 24 09:22:06 PM UTC 24 |
Sep 24 09:22:09 PM UTC 24 |
2074238318 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2310828134 |
|
|
Sep 24 09:21:58 PM UTC 24 |
Sep 24 09:22:11 PM UTC 24 |
3578153714 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2669602891 |
|
|
Sep 24 09:20:01 PM UTC 24 |
Sep 24 09:22:14 PM UTC 24 |
36221909177 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1586545450 |
|
|
Sep 24 09:20:13 PM UTC 24 |
Sep 24 09:22:14 PM UTC 24 |
96205413312 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2523690698 |
|
|
Sep 24 09:22:03 PM UTC 24 |
Sep 24 09:22:15 PM UTC 24 |
2844561867 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.955876739 |
|
|
Sep 24 09:22:08 PM UTC 24 |
Sep 24 09:22:15 PM UTC 24 |
2111036717 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.37592209 |
|
|
Sep 24 09:22:10 PM UTC 24 |
Sep 24 09:22:16 PM UTC 24 |
2621210559 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3285849343 |
|
|
Sep 24 09:22:08 PM UTC 24 |
Sep 24 09:22:16 PM UTC 24 |
2452567239 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4000185130 |
|
|
Sep 24 09:21:47 PM UTC 24 |
Sep 24 09:22:17 PM UTC 24 |
29097513034 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.697843593 |
|
|
Sep 24 09:22:09 PM UTC 24 |
Sep 24 09:22:17 PM UTC 24 |
2251953155 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.1971090183 |
|
|
Sep 24 09:22:16 PM UTC 24 |
Sep 24 09:22:20 PM UTC 24 |
4111785445 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3057301066 |
|
|
Sep 24 09:22:15 PM UTC 24 |
Sep 24 09:22:21 PM UTC 24 |
3134147659 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.2570157241 |
|
|
Sep 24 09:22:18 PM UTC 24 |
Sep 24 09:22:21 PM UTC 24 |
2052630459 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.4292471613 |
|
|
Sep 24 09:22:15 PM UTC 24 |
Sep 24 09:22:22 PM UTC 24 |
4266970356 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.977921065 |
|
|
Sep 24 09:22:12 PM UTC 24 |
Sep 24 09:22:22 PM UTC 24 |
2742524565 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2977800577 |
|
|
Sep 24 09:22:18 PM UTC 24 |
Sep 24 09:22:25 PM UTC 24 |
2110265008 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.1267896579 |
|
|
Sep 24 09:22:20 PM UTC 24 |
Sep 24 09:22:25 PM UTC 24 |
2502520841 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3537384310 |
|
|
Sep 24 09:22:10 PM UTC 24 |
Sep 24 09:22:25 PM UTC 24 |
2508626722 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4260229874 |
|
|
Sep 24 09:22:22 PM UTC 24 |
Sep 24 09:22:28 PM UTC 24 |
2643018917 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3823306455 |
|
|
Sep 24 09:22:24 PM UTC 24 |
Sep 24 09:22:28 PM UTC 24 |
2541132438 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.316315570 |
|
|
Sep 24 09:21:27 PM UTC 24 |
Sep 24 09:22:29 PM UTC 24 |
59440381975 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2812074968 |
|
|
Sep 24 09:22:21 PM UTC 24 |
Sep 24 09:22:31 PM UTC 24 |
2520194615 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.1891941341 |
|
|
Sep 24 09:19:33 PM UTC 24 |
Sep 24 09:22:32 PM UTC 24 |
186562874795 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.1556666441 |
|
|
Sep 24 09:22:21 PM UTC 24 |
Sep 24 09:22:34 PM UTC 24 |
2120539917 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.2925656732 |
|
|
Sep 24 09:19:46 PM UTC 24 |
Sep 24 09:22:35 PM UTC 24 |
81584017309 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1160175830 |
|
|
Sep 24 09:22:18 PM UTC 24 |
Sep 24 09:22:36 PM UTC 24 |
10204135667 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.691207872 |
|
|
Sep 24 09:22:32 PM UTC 24 |
Sep 24 09:22:37 PM UTC 24 |
2031900297 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1642662678 |
|
|
Sep 24 09:22:17 PM UTC 24 |
Sep 24 09:22:37 PM UTC 24 |
9550135134 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1487181661 |
|
|
Sep 24 09:22:33 PM UTC 24 |
Sep 24 09:22:38 PM UTC 24 |
2126692522 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.173939321 |
|
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Sep 24 09:22:26 PM UTC 24 |
Sep 24 09:22:40 PM UTC 24 |
4623633104 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2391598206 |
|
|
Sep 24 09:22:37 PM UTC 24 |
Sep 24 09:22:44 PM UTC 24 |
2617065556 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1198221401 |
|
|
Sep 24 09:22:35 PM UTC 24 |
Sep 24 09:22:44 PM UTC 24 |
2072399271 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2336569982 |
|
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Sep 24 09:22:29 PM UTC 24 |
Sep 24 09:22:45 PM UTC 24 |
12294645086 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.899542467 |
|
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Sep 24 09:22:37 PM UTC 24 |
Sep 24 09:22:45 PM UTC 24 |
2512997141 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2825948579 |
|
|
Sep 24 09:22:38 PM UTC 24 |
Sep 24 09:22:45 PM UTC 24 |
3775458795 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.1566612847 |
|
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Sep 24 09:22:38 PM UTC 24 |
Sep 24 09:22:45 PM UTC 24 |
4849180209 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.1521730188 |
|
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Sep 24 09:22:39 PM UTC 24 |
Sep 24 09:22:45 PM UTC 24 |
19163945771 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.1296390327 |
|
|
Sep 24 09:22:46 PM UTC 24 |
Sep 24 09:22:48 PM UTC 24 |
2041852519 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1136367875 |
|
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Sep 24 09:22:33 PM UTC 24 |
Sep 24 09:22:49 PM UTC 24 |
2479441458 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2000054839 |
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Sep 24 09:22:44 PM UTC 24 |
Sep 24 09:22:49 PM UTC 24 |
3190205680 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3869428104 |
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Sep 24 09:22:26 PM UTC 24 |
Sep 24 09:22:50 PM UTC 24 |
1357180362335 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.3081788832 |
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Sep 24 09:22:29 PM UTC 24 |
Sep 24 09:22:52 PM UTC 24 |
11621106267 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2463167574 |
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Sep 24 09:22:47 PM UTC 24 |
Sep 24 09:22:55 PM UTC 24 |
2101511090 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.1878025515 |
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Sep 24 09:22:50 PM UTC 24 |
Sep 24 09:22:56 PM UTC 24 |
2524020111 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.789916176 |
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Sep 24 09:22:47 PM UTC 24 |
Sep 24 09:22:56 PM UTC 24 |
2476542500 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1524196938 |
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Sep 24 09:22:46 PM UTC 24 |
Sep 24 09:22:59 PM UTC 24 |
8553823895 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3763468525 |
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Sep 24 09:22:16 PM UTC 24 |
Sep 24 09:22:59 PM UTC 24 |
92540351866 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2676261489 |
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Sep 24 09:22:46 PM UTC 24 |
Sep 24 09:22:59 PM UTC 24 |
2110985678 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.2104749214 |
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Sep 24 09:22:01 PM UTC 24 |
Sep 24 09:23:03 PM UTC 24 |
87906213595 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1983821679 |
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Sep 24 09:22:50 PM UTC 24 |
Sep 24 09:23:04 PM UTC 24 |
3623384653 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2523671527 |
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Sep 24 09:22:50 PM UTC 24 |
Sep 24 09:23:04 PM UTC 24 |
2609915984 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2908441728 |
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Sep 24 09:23:00 PM UTC 24 |
Sep 24 09:23:05 PM UTC 24 |
2125582659 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.4109429837 |
|
|
Sep 24 09:23:00 PM UTC 24 |
Sep 24 09:23:05 PM UTC 24 |
2036938374 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.70316788 |
|
|
Sep 24 09:22:56 PM UTC 24 |
Sep 24 09:23:05 PM UTC 24 |
4764258427 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3742261588 |
|
|
Sep 24 09:15:00 PM UTC 24 |
Sep 24 09:23:05 PM UTC 24 |
116201931119 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.480168295 |
|
|
Sep 24 09:22:51 PM UTC 24 |
Sep 24 09:23:07 PM UTC 24 |
2859795236 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2248845821 |
|
|
Sep 24 09:22:53 PM UTC 24 |
Sep 24 09:23:09 PM UTC 24 |
9276642420 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.1171851102 |
|
|
Sep 24 09:23:05 PM UTC 24 |
Sep 24 09:23:10 PM UTC 24 |
2531686156 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.2496274196 |
|
|
Sep 24 09:23:05 PM UTC 24 |
Sep 24 09:23:11 PM UTC 24 |
2620049448 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2016905283 |
|
|
Sep 24 09:23:05 PM UTC 24 |
Sep 24 09:23:11 PM UTC 24 |
3956460549 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1753472358 |
|
|
Sep 24 09:23:07 PM UTC 24 |
Sep 24 09:23:13 PM UTC 24 |
2638588461 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2201519018 |
|
|
Sep 24 09:23:04 PM UTC 24 |
Sep 24 09:23:13 PM UTC 24 |
2474134495 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3283258944 |
|
|
Sep 24 09:22:58 PM UTC 24 |
Sep 24 09:23:13 PM UTC 24 |
3646291726 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.3884151712 |
|
|
Sep 24 09:22:26 PM UTC 24 |
Sep 24 09:23:13 PM UTC 24 |
58377891464 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3499934356 |
|
|
Sep 24 09:23:05 PM UTC 24 |
Sep 24 09:23:13 PM UTC 24 |
2181959704 ps |