| T185 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.829890817 |
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Sep 24 09:22:04 PM UTC 24 |
Sep 24 09:23:15 PM UTC 24 |
47327058815 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1912058838 |
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Sep 24 09:23:13 PM UTC 24 |
Sep 24 09:23:17 PM UTC 24 |
2060059258 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1849905802 |
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Sep 24 09:23:11 PM UTC 24 |
Sep 24 09:23:17 PM UTC 24 |
3348069640 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2892212732 |
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Sep 24 09:23:05 PM UTC 24 |
Sep 24 09:23:18 PM UTC 24 |
3559308427 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3503350648 |
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Sep 24 09:23:14 PM UTC 24 |
Sep 24 09:23:19 PM UTC 24 |
2519391682 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.4167905061 |
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Sep 24 09:23:14 PM UTC 24 |
Sep 24 09:23:19 PM UTC 24 |
2132596531 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.44805528 |
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Sep 24 09:23:15 PM UTC 24 |
Sep 24 09:23:21 PM UTC 24 |
2628135495 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.4159770202 |
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Sep 24 09:21:49 PM UTC 24 |
Sep 24 09:23:22 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2931767434 |
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Sep 24 09:23:12 PM UTC 24 |
Sep 24 09:23:24 PM UTC 24 |
8415688106 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.4246394300 |
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Sep 24 09:23:14 PM UTC 24 |
Sep 24 09:23:24 PM UTC 24 |
2048657232 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.542358350 |
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Sep 24 09:23:18 PM UTC 24 |
Sep 24 09:23:26 PM UTC 24 |
2953616162 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2237483027 |
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Sep 24 09:23:14 PM UTC 24 |
Sep 24 09:23:29 PM UTC 24 |
2510962546 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3398643270 |
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Sep 24 09:23:26 PM UTC 24 |
Sep 24 09:23:31 PM UTC 24 |
2135299699 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.23421356 |
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Sep 24 09:23:20 PM UTC 24 |
Sep 24 09:23:32 PM UTC 24 |
3282942888 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.3296105192 |
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Sep 24 09:21:24 PM UTC 24 |
Sep 24 09:23:34 PM UTC 24 |
119403845466 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1544330611 |
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Sep 24 09:23:31 PM UTC 24 |
Sep 24 09:23:36 PM UTC 24 |
2489005362 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3122389353 |
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Sep 24 09:23:25 PM UTC 24 |
Sep 24 09:23:36 PM UTC 24 |
7450267151 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1537134379 |
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Sep 24 09:17:33 PM UTC 24 |
Sep 24 09:23:36 PM UTC 24 |
116151256251 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.1461494649 |
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Sep 24 09:23:25 PM UTC 24 |
Sep 24 09:23:37 PM UTC 24 |
2014334980 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.124748508 |
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Sep 24 09:23:00 PM UTC 24 |
Sep 24 09:23:38 PM UTC 24 |
17228628727 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3025048035 |
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Sep 24 09:23:34 PM UTC 24 |
Sep 24 09:23:38 PM UTC 24 |
2626069749 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.4021711227 |
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Sep 24 09:23:35 PM UTC 24 |
Sep 24 09:23:40 PM UTC 24 |
4097983333 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.230274737 |
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Sep 24 09:23:34 PM UTC 24 |
Sep 24 09:23:42 PM UTC 24 |
2517006450 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.848268146 |
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Sep 24 09:23:37 PM UTC 24 |
Sep 24 09:23:43 PM UTC 24 |
3473969261 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.384879063 |
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Sep 24 09:22:58 PM UTC 24 |
Sep 24 09:23:44 PM UTC 24 |
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| T222 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.3572555033 |
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Sep 24 09:23:38 PM UTC 24 |
Sep 24 09:23:44 PM UTC 24 |
3877221251 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3222020496 |
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Sep 24 09:23:37 PM UTC 24 |
Sep 24 09:23:44 PM UTC 24 |
3903100529 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.196978665 |
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Sep 24 09:23:22 PM UTC 24 |
Sep 24 09:23:44 PM UTC 24 |
107510908242 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.3684145701 |
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Sep 24 09:23:32 PM UTC 24 |
Sep 24 09:23:45 PM UTC 24 |
2243796547 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.795573587 |
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Sep 24 09:23:44 PM UTC 24 |
Sep 24 09:23:48 PM UTC 24 |
2128439277 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1474572048 |
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Sep 24 09:23:45 PM UTC 24 |
Sep 24 09:23:48 PM UTC 24 |
2677112499 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.752112469 |
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Sep 24 09:23:40 PM UTC 24 |
Sep 24 09:23:48 PM UTC 24 |
4712189507 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.2881280392 |
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Sep 24 09:13:32 PM UTC 24 |
Sep 24 09:23:49 PM UTC 24 |
332888926105 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1925958926 |
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Sep 24 09:23:45 PM UTC 24 |
Sep 24 09:23:50 PM UTC 24 |
2473341009 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.3750587911 |
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Sep 24 09:23:43 PM UTC 24 |
Sep 24 09:23:51 PM UTC 24 |
2011092556 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1632039716 |
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Sep 24 09:23:48 PM UTC 24 |
Sep 24 09:23:53 PM UTC 24 |
3951079497 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.2956700362 |
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Sep 24 09:23:45 PM UTC 24 |
Sep 24 09:23:53 PM UTC 24 |
2049489109 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.145008777 |
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Sep 24 09:18:28 PM UTC 24 |
Sep 24 09:23:54 PM UTC 24 |
76888796857 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2332448531 |
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Sep 24 09:16:15 PM UTC 24 |
Sep 24 09:23:55 PM UTC 24 |
136321001825 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.2422351172 |
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Sep 24 09:23:50 PM UTC 24 |
Sep 24 09:23:56 PM UTC 24 |
5831534500 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2731623444 |
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Sep 24 09:23:54 PM UTC 24 |
Sep 24 09:23:58 PM UTC 24 |
2053201974 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.328634981 |
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Sep 24 09:23:45 PM UTC 24 |
Sep 24 09:23:59 PM UTC 24 |
2514043595 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2842786416 |
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Sep 24 09:23:46 PM UTC 24 |
Sep 24 09:24:02 PM UTC 24 |
2826730030 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2745082864 |
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Sep 24 09:23:56 PM UTC 24 |
Sep 24 09:24:02 PM UTC 24 |
2471046753 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3652082348 |
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Sep 24 09:22:28 PM UTC 24 |
Sep 24 09:24:06 PM UTC 24 |
134003142442 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1768530178 |
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Sep 24 09:24:00 PM UTC 24 |
Sep 24 09:24:06 PM UTC 24 |
2633056850 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1100447862 |
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Sep 24 09:23:56 PM UTC 24 |
Sep 24 09:24:08 PM UTC 24 |
2127521990 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3446147427 |
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Sep 24 09:23:55 PM UTC 24 |
Sep 24 09:24:09 PM UTC 24 |
2112848616 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3365161210 |
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Sep 24 09:23:52 PM UTC 24 |
Sep 24 09:24:10 PM UTC 24 |
3217050649 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3379047422 |
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Sep 24 09:17:22 PM UTC 24 |
Sep 24 09:24:12 PM UTC 24 |
2366478437110 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.4050643956 |
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Sep 24 09:23:59 PM UTC 24 |
Sep 24 09:24:12 PM UTC 24 |
2513936321 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.355783644 |
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Sep 24 09:21:08 PM UTC 24 |
Sep 24 09:24:13 PM UTC 24 |
52919079481 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3620272006 |
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Sep 24 09:24:07 PM UTC 24 |
Sep 24 09:24:13 PM UTC 24 |
8635285900 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1110725115 |
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Sep 24 09:24:03 PM UTC 24 |
Sep 24 09:24:19 PM UTC 24 |
3571259507 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1858594483 |
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Sep 24 09:23:41 PM UTC 24 |
Sep 24 09:24:19 PM UTC 24 |
14322171911 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.3921428334 |
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Sep 24 09:24:09 PM UTC 24 |
Sep 24 09:24:19 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2470877142 |
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Sep 24 09:24:13 PM UTC 24 |
Sep 24 09:24:21 PM UTC 24 |
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| T654 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.283093006 |
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Sep 24 09:24:40 PM UTC 24 |
Sep 24 09:24:44 PM UTC 24 |
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| T655 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1034678660 |
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Sep 24 09:24:03 PM UTC 24 |
Sep 24 09:24:23 PM UTC 24 |
3284279785 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1254877923 |
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Sep 24 09:24:14 PM UTC 24 |
Sep 24 09:24:23 PM UTC 24 |
2116275259 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.2010161367 |
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Sep 24 09:22:54 PM UTC 24 |
Sep 24 09:24:24 PM UTC 24 |
88060825734 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2725912462 |
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Sep 24 09:24:21 PM UTC 24 |
Sep 24 09:24:24 PM UTC 24 |
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| T658 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1090173877 |
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Sep 24 09:24:14 PM UTC 24 |
Sep 24 09:24:24 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1020211737 |
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Sep 24 09:24:13 PM UTC 24 |
Sep 24 09:24:25 PM UTC 24 |
9834680048 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.568877837 |
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Sep 24 09:24:21 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.4280757114 |
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Sep 24 09:24:20 PM UTC 24 |
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| T662 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.928672453 |
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Sep 24 09:24:22 PM UTC 24 |
Sep 24 09:24:27 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2627184314 |
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Sep 24 09:24:10 PM UTC 24 |
Sep 24 09:24:28 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1051582546 |
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Sep 24 09:20:42 PM UTC 24 |
Sep 24 09:24:29 PM UTC 24 |
63612172132 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.3212525751 |
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Sep 24 09:24:27 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2761676650 |
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Sep 24 09:23:48 PM UTC 24 |
Sep 24 09:24:29 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.1373596910 |
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Sep 24 09:24:26 PM UTC 24 |
Sep 24 09:24:31 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.918536274 |
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Sep 24 09:24:27 PM UTC 24 |
Sep 24 09:24:32 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.2941164739 |
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Sep 24 09:24:28 PM UTC 24 |
Sep 24 09:24:32 PM UTC 24 |
2184034455 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.4052798190 |
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Sep 24 09:15:58 PM UTC 24 |
Sep 24 09:24:40 PM UTC 24 |
152147935203 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3924480755 |
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Sep 24 09:24:28 PM UTC 24 |
Sep 24 09:24:33 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2544799298 |
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Sep 24 09:24:33 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.4057824558 |
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Sep 24 09:24:34 PM UTC 24 |
Sep 24 09:24:39 PM UTC 24 |
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| T674 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3467767525 |
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Sep 24 09:24:30 PM UTC 24 |
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2613072565 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3265192435 |
|
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Sep 24 09:24:30 PM UTC 24 |
Sep 24 09:24:41 PM UTC 24 |
2511222773 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3200552596 |
|
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Sep 24 09:24:41 PM UTC 24 |
Sep 24 09:24:46 PM UTC 24 |
2146845357 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.1801730008 |
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Sep 24 09:24:39 PM UTC 24 |
Sep 24 09:24:47 PM UTC 24 |
7459109576 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.4011563607 |
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Sep 24 09:23:54 PM UTC 24 |
Sep 24 09:24:47 PM UTC 24 |
13682477138 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.41546314 |
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Sep 24 09:24:47 PM UTC 24 |
Sep 24 09:24:52 PM UTC 24 |
2636685816 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.3039291146 |
|
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Sep 24 09:24:40 PM UTC 24 |
Sep 24 09:24:52 PM UTC 24 |
2109376905 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1605349524 |
|
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Sep 24 09:24:48 PM UTC 24 |
Sep 24 09:24:54 PM UTC 24 |
3980866860 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2842390068 |
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Sep 24 09:24:45 PM UTC 24 |
Sep 24 09:24:54 PM UTC 24 |
2511988220 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1503465162 |
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Sep 24 09:22:17 PM UTC 24 |
Sep 24 09:24:55 PM UTC 24 |
70598171712 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3133926163 |
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Sep 24 09:24:41 PM UTC 24 |
Sep 24 09:24:56 PM UTC 24 |
2439825279 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1488044260 |
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Sep 24 09:24:39 PM UTC 24 |
Sep 24 09:24:58 PM UTC 24 |
3605770280 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4174710563 |
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Sep 24 09:24:48 PM UTC 24 |
Sep 24 09:24:58 PM UTC 24 |
3427712181 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.4005590004 |
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Sep 24 09:24:53 PM UTC 24 |
Sep 24 09:24:59 PM UTC 24 |
5449930295 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3807152910 |
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Sep 24 09:23:22 PM UTC 24 |
Sep 24 09:25:02 PM UTC 24 |
63998387026 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.2426584283 |
|
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Sep 24 09:24:55 PM UTC 24 |
Sep 24 09:25:02 PM UTC 24 |
9744076948 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3142455126 |
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Sep 24 09:24:50 PM UTC 24 |
Sep 24 09:25:03 PM UTC 24 |
10330723531 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.1437274230 |
|
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Sep 24 09:25:00 PM UTC 24 |
Sep 24 09:25:06 PM UTC 24 |
2194819686 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3366766829 |
|
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Sep 24 09:24:59 PM UTC 24 |
Sep 24 09:25:07 PM UTC 24 |
2474245803 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.1275352259 |
|
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Sep 24 09:24:59 PM UTC 24 |
Sep 24 09:25:08 PM UTC 24 |
2109835712 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.4019227126 |
|
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Sep 24 09:22:03 PM UTC 24 |
Sep 24 09:25:08 PM UTC 24 |
52560856303 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.5355697 |
|
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Sep 24 09:24:54 PM UTC 24 |
Sep 24 09:25:08 PM UTC 24 |
4315824889 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.2231807758 |
|
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Sep 24 09:24:56 PM UTC 24 |
Sep 24 09:25:10 PM UTC 24 |
2011723435 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.143552779 |
|
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Sep 24 09:25:03 PM UTC 24 |
Sep 24 09:25:12 PM UTC 24 |
2613587525 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2345062695 |
|
|
Sep 24 09:25:03 PM UTC 24 |
Sep 24 09:25:17 PM UTC 24 |
2514320382 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.3234470133 |
|
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Sep 24 09:25:08 PM UTC 24 |
Sep 24 09:25:18 PM UTC 24 |
6237679491 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.1064877982 |
|
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Sep 24 09:25:08 PM UTC 24 |
Sep 24 09:25:20 PM UTC 24 |
4384052652 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3685715974 |
|
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Sep 24 09:25:06 PM UTC 24 |
Sep 24 09:25:23 PM UTC 24 |
3352210118 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.372592401 |
|
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Sep 24 09:25:19 PM UTC 24 |
Sep 24 09:25:23 PM UTC 24 |
2129290403 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3046625027 |
|
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Sep 24 09:24:53 PM UTC 24 |
Sep 24 09:25:24 PM UTC 24 |
43107762365 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.3189140537 |
|
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Sep 24 09:25:18 PM UTC 24 |
Sep 24 09:25:25 PM UTC 24 |
2010436381 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1318223577 |
|
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Sep 24 09:24:23 PM UTC 24 |
Sep 24 09:25:25 PM UTC 24 |
21472372473 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2200700411 |
|
|
Sep 24 09:25:04 PM UTC 24 |
Sep 24 09:25:25 PM UTC 24 |
3845737976 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3824447133 |
|
|
Sep 24 09:25:24 PM UTC 24 |
Sep 24 09:25:27 PM UTC 24 |
2132814378 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.42222009 |
|
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Sep 24 09:25:21 PM UTC 24 |
Sep 24 09:25:31 PM UTC 24 |
2462417808 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.233789486 |
|
|
Sep 24 09:25:24 PM UTC 24 |
Sep 24 09:25:32 PM UTC 24 |
2522772749 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.1352860362 |
|
|
Sep 24 09:24:34 PM UTC 24 |
Sep 24 09:25:32 PM UTC 24 |
58886579706 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.4084591119 |
|
|
Sep 24 09:25:11 PM UTC 24 |
Sep 24 09:25:33 PM UTC 24 |
10787513783 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2477788139 |
|
|
Sep 24 09:25:25 PM UTC 24 |
Sep 24 09:25:34 PM UTC 24 |
2613926188 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2344346109 |
|
|
Sep 24 09:25:25 PM UTC 24 |
Sep 24 09:25:39 PM UTC 24 |
3427771130 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.2313502755 |
|
|
Sep 24 09:23:18 PM UTC 24 |
Sep 24 09:25:40 PM UTC 24 |
115178180687 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.2934408674 |
|
|
Sep 24 09:25:32 PM UTC 24 |
Sep 24 09:25:42 PM UTC 24 |
3658884545 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3367843992 |
|
|
Sep 24 09:25:35 PM UTC 24 |
Sep 24 09:25:42 PM UTC 24 |
2017259331 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.2770693316 |
|
|
Sep 24 09:25:08 PM UTC 24 |
Sep 24 09:25:43 PM UTC 24 |
60982386644 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1769425741 |
|
|
Sep 24 09:25:40 PM UTC 24 |
Sep 24 09:25:46 PM UTC 24 |
2120780106 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.4040629087 |
|
|
Sep 24 09:25:44 PM UTC 24 |
Sep 24 09:25:47 PM UTC 24 |
2635410738 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.425387756 |
|
|
Sep 24 09:24:32 PM UTC 24 |
Sep 24 09:25:48 PM UTC 24 |
123776694111 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.3132412502 |
|
|
Sep 24 09:25:41 PM UTC 24 |
Sep 24 09:25:50 PM UTC 24 |
2481343560 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3310769817 |
|
|
Sep 24 09:25:33 PM UTC 24 |
Sep 24 09:25:50 PM UTC 24 |
3277079167 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2506700104 |
|
|
Sep 24 09:25:44 PM UTC 24 |
Sep 24 09:25:51 PM UTC 24 |
2248278491 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.537135422 |
|
|
Sep 24 09:25:48 PM UTC 24 |
Sep 24 09:25:54 PM UTC 24 |
6302523326 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2365468702 |
|
|
Sep 24 09:25:47 PM UTC 24 |
Sep 24 09:25:54 PM UTC 24 |
3755496902 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1260989244 |
|
|
Sep 24 09:25:48 PM UTC 24 |
Sep 24 09:25:55 PM UTC 24 |
3825677098 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.409839052 |
|
|
Sep 24 09:25:45 PM UTC 24 |
Sep 24 09:25:56 PM UTC 24 |
2613698841 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3275880051 |
|
|
Sep 24 09:25:55 PM UTC 24 |
Sep 24 09:25:58 PM UTC 24 |
2093020717 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2981696011 |
|
|
Sep 24 09:25:51 PM UTC 24 |
Sep 24 09:25:59 PM UTC 24 |
4011127277 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2946357103 |
|
|
Sep 24 09:25:56 PM UTC 24 |
Sep 24 09:26:00 PM UTC 24 |
2133411694 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.1928516750 |
|
|
Sep 24 09:25:58 PM UTC 24 |
Sep 24 09:26:02 PM UTC 24 |
2187764431 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2216440922 |
|
|
Sep 24 09:25:57 PM UTC 24 |
Sep 24 09:26:02 PM UTC 24 |
2476660443 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2738822683 |
|
|
Sep 24 09:23:51 PM UTC 24 |
Sep 24 09:26:04 PM UTC 24 |
147449822376 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1434151938 |
|
|
Sep 24 09:26:00 PM UTC 24 |
Sep 24 09:26:04 PM UTC 24 |
2623531264 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3664831002 |
|
|
Sep 24 09:23:12 PM UTC 24 |
Sep 24 09:26:07 PM UTC 24 |
1590743844116 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3662100825 |
|
|
Sep 24 09:26:00 PM UTC 24 |
Sep 24 09:26:08 PM UTC 24 |
2517144550 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.530342279 |
|
|
Sep 24 09:25:34 PM UTC 24 |
Sep 24 09:26:08 PM UTC 24 |
11133293800 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1947806665 |
|
|
Sep 24 09:26:04 PM UTC 24 |
Sep 24 09:26:10 PM UTC 24 |
6457738157 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2768003798 |
|
|
Sep 24 09:23:11 PM UTC 24 |
Sep 24 09:26:11 PM UTC 24 |
69057560568 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3554515762 |
|
|
Sep 24 09:26:08 PM UTC 24 |
Sep 24 09:26:12 PM UTC 24 |
4307978117 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.3177179956 |
|
|
Sep 24 09:25:55 PM UTC 24 |
Sep 24 09:26:14 PM UTC 24 |
8970357745 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2738484092 |
|
|
Sep 24 09:26:03 PM UTC 24 |
Sep 24 09:26:14 PM UTC 24 |
3539220553 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.736228186 |
|
|
Sep 24 09:26:02 PM UTC 24 |
Sep 24 09:26:15 PM UTC 24 |
3975939387 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2763620499 |
|
|
Sep 24 09:25:52 PM UTC 24 |
Sep 24 09:26:16 PM UTC 24 |
7379549293 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3251789415 |
|
|
Sep 24 09:26:12 PM UTC 24 |
Sep 24 09:26:16 PM UTC 24 |
2128865415 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.1263290617 |
|
|
Sep 24 09:26:13 PM UTC 24 |
Sep 24 09:26:17 PM UTC 24 |
2491215080 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.4157731346 |
|
|
Sep 24 09:25:13 PM UTC 24 |
Sep 24 09:26:17 PM UTC 24 |
13026048650 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.2542355744 |
|
|
Sep 24 09:26:14 PM UTC 24 |
Sep 24 09:26:18 PM UTC 24 |
2559378774 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.3977238689 |
|
|
Sep 24 09:26:14 PM UTC 24 |
Sep 24 09:26:19 PM UTC 24 |
2194059061 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.374736573 |
|
|
Sep 24 09:26:17 PM UTC 24 |
Sep 24 09:26:22 PM UTC 24 |
4984150772 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3728894282 |
|
|
Sep 24 09:26:09 PM UTC 24 |
Sep 24 09:26:22 PM UTC 24 |
4572572754 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.1950561636 |
|
|
Sep 24 09:26:19 PM UTC 24 |
Sep 24 09:26:23 PM UTC 24 |
2928859299 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1239327412 |
|
|
Sep 24 09:26:18 PM UTC 24 |
Sep 24 09:26:25 PM UTC 24 |
9534228984 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3693690291 |
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Sep 24 09:26:12 PM UTC 24 |
Sep 24 09:26:25 PM UTC 24 |
2015407161 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.3031730639 |
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Sep 24 09:26:23 PM UTC 24 |
Sep 24 09:26:26 PM UTC 24 |
2133782523 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.981045750 |
|
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Sep 24 09:24:54 PM UTC 24 |
Sep 24 09:26:32 PM UTC 24 |
28831625354 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1634942290 |
|
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Sep 24 09:26:16 PM UTC 24 |
Sep 24 09:26:32 PM UTC 24 |
2610078499 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2230643982 |
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Sep 24 09:26:18 PM UTC 24 |
Sep 24 09:26:34 PM UTC 24 |
3464950684 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2049308928 |
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Sep 24 09:26:23 PM UTC 24 |
Sep 24 09:26:35 PM UTC 24 |
8800290459 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.204021273 |
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Sep 24 09:22:45 PM UTC 24 |
Sep 24 09:26:40 PM UTC 24 |
138779870995 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.36579817 |
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Sep 24 09:25:27 PM UTC 24 |
Sep 24 09:26:43 PM UTC 24 |
698281017267 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.1055385039 |
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Sep 24 09:26:11 PM UTC 24 |
Sep 24 09:26:45 PM UTC 24 |
8232487212 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.852207344 |
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Sep 24 09:26:22 PM UTC 24 |
Sep 24 09:26:46 PM UTC 24 |
6322512871 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3561805636 |
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Sep 24 09:26:40 PM UTC 24 |
Sep 24 09:26:52 PM UTC 24 |
34590146644 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1338390137 |
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Sep 24 09:26:33 PM UTC 24 |
Sep 24 09:27:00 PM UTC 24 |
27100744089 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1525807277 |
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Sep 24 09:26:33 PM UTC 24 |
Sep 24 09:27:00 PM UTC 24 |
28354357642 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3450999210 |
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Sep 24 09:22:46 PM UTC 24 |
Sep 24 09:27:00 PM UTC 24 |
330887929990 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2757258028 |
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Sep 24 09:25:10 PM UTC 24 |
Sep 24 09:27:08 PM UTC 24 |
31080851859 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.492908944 |
|
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Sep 24 09:26:25 PM UTC 24 |
Sep 24 09:27:16 PM UTC 24 |
54769604237 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.3138240462 |
|
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Sep 24 09:25:49 PM UTC 24 |
Sep 24 09:27:25 PM UTC 24 |
27638559369 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2398752241 |
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Sep 24 09:27:05 PM UTC 24 |
Sep 24 09:27:26 PM UTC 24 |
33393501931 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2616136291 |
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Sep 24 09:26:09 PM UTC 24 |
Sep 24 09:27:41 PM UTC 24 |
54900253543 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.555414053 |
|
|
Sep 24 09:19:35 PM UTC 24 |
Sep 24 09:27:41 PM UTC 24 |
123337798700 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.3040241060 |
|
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Sep 24 09:24:33 PM UTC 24 |
Sep 24 09:27:48 PM UTC 24 |
116695065820 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1169394807 |
|
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Sep 24 09:27:01 PM UTC 24 |
Sep 24 09:27:55 PM UTC 24 |
63340085353 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.966756684 |
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Sep 24 09:26:54 PM UTC 24 |
Sep 24 09:27:56 PM UTC 24 |
36836775322 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3079952209 |
|
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Sep 24 09:27:13 PM UTC 24 |
Sep 24 09:28:04 PM UTC 24 |
66060333496 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3634566697 |
|
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Sep 24 09:25:33 PM UTC 24 |
Sep 24 09:28:06 PM UTC 24 |
48016622581 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3869607929 |
|
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Sep 24 09:26:36 PM UTC 24 |
Sep 24 09:28:10 PM UTC 24 |
22830732962 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2630316119 |
|
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Sep 24 09:27:17 PM UTC 24 |
Sep 24 09:28:14 PM UTC 24 |
69479195569 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2708973799 |
|
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Sep 24 09:20:27 PM UTC 24 |
Sep 24 09:28:23 PM UTC 24 |
168691003666 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.3110294187 |
|
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Sep 24 09:26:18 PM UTC 24 |
Sep 24 09:28:34 PM UTC 24 |
172828089278 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.574739712 |
|
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Sep 24 09:27:27 PM UTC 24 |
Sep 24 09:28:34 PM UTC 24 |
63486929710 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1681791849 |
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Sep 24 09:26:44 PM UTC 24 |
Sep 24 09:28:35 PM UTC 24 |
25828975320 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.4142395849 |
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Sep 24 09:13:18 PM UTC 24 |
Sep 24 09:28:36 PM UTC 24 |
258071813134 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1694594715 |
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|
Sep 24 09:26:04 PM UTC 24 |
Sep 24 09:28:39 PM UTC 24 |
83751589186 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2529986965 |
|
|
Sep 24 09:20:01 PM UTC 24 |
Sep 24 09:28:40 PM UTC 24 |
158988514904 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3085158038 |
|
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Sep 24 09:26:20 PM UTC 24 |
Sep 24 09:28:40 PM UTC 24 |
73287818475 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3269524315 |
|
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Sep 24 09:21:46 PM UTC 24 |
Sep 24 09:28:43 PM UTC 24 |
142334497542 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1537273865 |
|
|
Sep 24 09:26:27 PM UTC 24 |
Sep 24 09:28:44 PM UTC 24 |
29331957179 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.3269355413 |
|
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Sep 24 09:24:07 PM UTC 24 |
Sep 24 09:28:50 PM UTC 24 |
81737808952 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.381789320 |
|
|
Sep 24 09:27:49 PM UTC 24 |
Sep 24 09:28:54 PM UTC 24 |
59662176685 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.3134694000 |
|
|
Sep 24 09:17:49 PM UTC 24 |
Sep 24 09:29:04 PM UTC 24 |
217079608644 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.1144802894 |
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Sep 24 09:27:28 PM UTC 24 |
Sep 24 09:29:09 PM UTC 24 |
73184452990 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1734626438 |
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Sep 24 09:27:30 PM UTC 24 |
Sep 24 09:29:22 PM UTC 24 |
124851881599 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.498123176 |
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Sep 24 09:27:42 PM UTC 24 |
Sep 24 09:29:24 PM UTC 24 |
58669117357 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2577709845 |
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Sep 24 09:28:45 PM UTC 24 |
Sep 24 09:29:31 PM UTC 24 |
81547421395 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.895582911 |
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Sep 24 09:28:35 PM UTC 24 |
Sep 24 09:29:32 PM UTC 24 |
35012911973 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2688409176 |
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Sep 24 09:27:42 PM UTC 24 |
Sep 24 09:29:37 PM UTC 24 |
177789385364 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.390079185 |
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Sep 24 09:29:06 PM UTC 24 |
Sep 24 09:29:40 PM UTC 24 |
83430011522 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.1816514445 |
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Sep 24 09:23:37 PM UTC 24 |
Sep 24 09:29:41 PM UTC 24 |
115668496072 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.779112127 |
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Sep 24 09:27:09 PM UTC 24 |
Sep 24 09:29:41 PM UTC 24 |
120013453278 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.660681624 |
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Sep 24 09:28:15 PM UTC 24 |
Sep 24 09:29:42 PM UTC 24 |
25583697173 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.804504789 |
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Sep 24 09:28:35 PM UTC 24 |
Sep 24 09:29:45 PM UTC 24 |
71924999246 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2489799643 |
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Sep 24 09:29:04 PM UTC 24 |
Sep 24 09:29:53 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.825971963 |
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Sep 24 09:22:41 PM UTC 24 |
Sep 24 09:29:58 PM UTC 24 |
132086707153 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.1609873265 |
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Sep 24 09:25:51 PM UTC 24 |
Sep 24 09:29:59 PM UTC 24 |
61862175896 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4040423293 |
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Sep 24 09:29:25 PM UTC 24 |
Sep 24 09:30:05 PM UTC 24 |
45648067280 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.2828411945 |
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Sep 24 09:24:24 PM UTC 24 |
Sep 24 09:30:10 PM UTC 24 |
201395446601 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.134717634 |
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Sep 24 09:28:44 PM UTC 24 |
Sep 24 09:30:17 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1000407799 |
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Sep 24 09:26:48 PM UTC 24 |
Sep 24 09:30:19 PM UTC 24 |
72850785088 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.941248521 |
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Sep 24 09:28:41 PM UTC 24 |
Sep 24 09:30:28 PM UTC 24 |
39964539665 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2812865526 |
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Sep 24 09:28:59 PM UTC 24 |
Sep 24 09:30:34 PM UTC 24 |
129203793833 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1093205142 |
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Sep 24 09:28:07 PM UTC 24 |
Sep 24 09:30:34 PM UTC 24 |
51773790386 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2227789651 |
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Sep 24 09:23:38 PM UTC 24 |
Sep 24 09:30:37 PM UTC 24 |
250802606985 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1455096973 |
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Sep 24 09:26:26 PM UTC 24 |
Sep 24 09:31:02 PM UTC 24 |
59028525406 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1449509192 |
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Sep 24 09:29:11 PM UTC 24 |
Sep 24 09:31:05 PM UTC 24 |
106991922537 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2187101194 |
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Sep 24 09:28:41 PM UTC 24 |
Sep 24 09:31:16 PM UTC 24 |
122953489259 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2754575043 |
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Sep 24 09:28:37 PM UTC 24 |
Sep 24 09:31:18 PM UTC 24 |
160881163980 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1819691593 |
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Sep 24 09:27:01 PM UTC 24 |
Sep 24 09:31:20 PM UTC 24 |
74736197807 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.378012664 |
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Sep 24 09:26:35 PM UTC 24 |
Sep 24 09:31:34 PM UTC 24 |
77258168869 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.1120409016 |
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Sep 24 09:23:50 PM UTC 24 |
Sep 24 09:31:42 PM UTC 24 |
113355986008 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.838886424 |
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Sep 24 09:28:41 PM UTC 24 |
Sep 24 09:31:45 PM UTC 24 |
97443840725 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3933469088 |
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Sep 24 09:26:46 PM UTC 24 |
Sep 24 09:31:55 PM UTC 24 |
108065234674 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.4218335835 |
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Sep 24 09:24:26 PM UTC 24 |
Sep 24 09:32:05 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.96288426 |
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Sep 24 09:28:05 PM UTC 24 |
Sep 24 09:32:26 PM UTC 24 |
81351146102 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.2299083713 |
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Sep 24 09:29:32 PM UTC 24 |
Sep 24 09:32:38 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1540954526 |
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Sep 24 09:14:33 PM UTC 24 |
Sep 24 09:32:42 PM UTC 24 |
324230444615 ps |
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/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1404470193 |
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Sep 24 09:28:54 PM UTC 24 |
Sep 24 09:33:15 PM UTC 24 |
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Sep 24 09:23:08 PM UTC 24 |
Sep 24 09:33:29 PM UTC 24 |
167152304161 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1243325780 |
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Sep 24 09:27:55 PM UTC 24 |
Sep 24 09:33:33 PM UTC 24 |
86287761223 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.1575391638 |
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Sep 24 09:23:20 PM UTC 24 |
Sep 24 09:33:36 PM UTC 24 |
185562481582 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.755504885 |
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Sep 24 09:28:35 PM UTC 24 |
Sep 24 09:34:10 PM UTC 24 |
108870195409 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3562345873 |
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Sep 24 09:29:24 PM UTC 24 |
Sep 24 09:34:13 PM UTC 24 |
73264274881 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.4073783552 |
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Sep 24 09:27:57 PM UTC 24 |
Sep 24 09:34:21 PM UTC 24 |
225630606895 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.355090971 |
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Sep 24 09:19:37 PM UTC 24 |
Sep 24 09:34:59 PM UTC 24 |
288332200268 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.533945885 |
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Sep 24 09:25:29 PM UTC 24 |
Sep 24 09:35:43 PM UTC 24 |
173656390796 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.3289632583 |
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Sep 24 09:20:41 PM UTC 24 |
Sep 24 09:36:25 PM UTC 24 |
1114929733043 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2771163955 |
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Sep 24 09:25:26 PM UTC 24 |
Sep 24 09:41:34 PM UTC 24 |
288669212293 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.3916897143 |
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Sep 24 09:16:59 PM UTC 24 |
Sep 24 09:49:41 PM UTC 24 |
1192550609350 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1546049658 |
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Sep 24 09:14:45 PM UTC 24 |
Sep 24 10:01:16 PM UTC 24 |
1018174863252 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1592204002 |
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Sep 24 09:35:52 PM UTC 24 |
Sep 24 09:35:56 PM UTC 24 |
2119388704 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1658012008 |
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Sep 24 09:35:54 PM UTC 24 |
Sep 24 09:35:57 PM UTC 24 |
2052291598 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3837517774 |
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Sep 24 09:35:52 PM UTC 24 |
Sep 24 09:35:57 PM UTC 24 |
6311857779 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_09_23/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2642192792 |
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Sep 24 09:35:52 PM UTC 24 |
Sep 24 09:35:57 PM UTC 24 |
3831887463 ps |