Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T13

2

T21

12

T34

10

auto[1]

1794

1

T13

13

T21

12

T34

15

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2351

1

T13

13

T21

20

T34

20

auto[1]

565

1

T13

2

T21

4

T34

5

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2745

1

T13

15

T21

20

T34

25

auto[1]

171

1

T21

4

T40

3

T41

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2768

1

T13

13

T21

23

T34

25

auto[1]

148

1

T13

2

T21

1

T42

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2744

1

T13

15

T21

24

T34

20

auto[1]

172

1

T34

5

T43

4

T44

2

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1663

1

T13

4

T21

24

T34

6

auto[1]

1253

1

T13

11

T34

19

T42

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T13

6

T21

9

T34

12

auto[1]

1704

1

T13

9

T21

15

T34

13

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T21

11

T34

10

T42

13

auto[1]

1798

1

T13

15

T21

13

T34

15

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1287

1

T21

9

T34

12

T42

14

auto[1]

1629

1

T13

15

T21

15

T34

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1298

1

T13

15

T21

10

T34

12

auto[1]

1618

1

T21

14

T34

13

T42

14

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

39

1

T21

1

T97

1

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T34

1

T43

1

T372

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T42

2

T97

1

T40

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T34

2

T96

1

T244

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T34

1

T42

1

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T259

1

T372

1

T373

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T42

2

T97

2

T41

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T96

2

T43

1

T113

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T97

1

T172

1

T107

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T34

1

T168

1

T284

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T97

1

T40

4

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T40

5

T283

1

T284

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T258

1

T254

2

T252

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T34

1

T244

3

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

33

1

T21

1

T92

1

T172

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T244

1

T284

2

T372

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T21

1

T40

4

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T34

2

T96

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

32

1

T41

1

T43

1

T255

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T92

2

T284

1

T372

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T21

2

T42

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T168

1

T259

1

T257

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

69

1

T21

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T244

1

T43

1

T168

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T13

1

T42

1

T43

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T259

1

T284

1

T285

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T13

1

T21

1

T42

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

33

1

T13

2

T34

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

21

1

T97

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T34

1

T96

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T97

1

T92

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

46

1

T92

4

T257

2

T372

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T97

1

T41

1

T43

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T43

1

T283

1

T113

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T97

1

T93

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T34

1

T96

1

T244

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T96

1

T97

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T43

1

T259

1

T113

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29

1

T21

1

T42

1

T282

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T42

7

T96

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41

1

T21

2

T97

1

T41

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

25

1

T244

3

T41

1

T294

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T21

1

T41

2

T172

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T96

1

T244

1

T168

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T21

2

T43

1

T294

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T96

1

T244

2

T259

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T97

1

T41

2

T44

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

50

1

T41

2

T43

1

T284

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42

1

T21

2

T43

2

T172

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T34

1

T283

1

T113

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T97

1

T92

2

T244

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

36

1

T34

1

T96

1

T92

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

30

1

T172

2

T258

1

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

26

1

T96

1

T244

1

T43

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T93

1

T172

1

T266

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

66

1

T34

2

T93

9

T294

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T13

1

T42

1

T43

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T259

1

T283

1

T113

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T13

1

T21

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

66

1

T13

7

T96

2

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T97

2

T258

1

T262

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T42

1

T41

2

T283

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

247

1

T21

4

T34

5

T97

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T96

1

T244

1

T43

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T286

1

T115

2

T374

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T168

1

T284

1

T372

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T96

1

T168

1

T375

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T244

1

T376

1

T226

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T34

1

T96

1

T228

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T372

2

T377

1

T119

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T375

1

T378

1

T292

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T168

1

T285

1

T226

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T96

1

T43

1

T168

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T43

1

T284

1

T228

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T257

2

T113

1

T261

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T43

1

T372

1

T286

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T42

1

T168

1

T376

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

18

1

T13

2

T34

1

T244

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T254

6

T226

1

T377

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T168

1

T228

1

T377

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T284

1

T376

1

T226

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T168

2

T284

2

T376

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T34

1

T244

1

T376

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T285

1

T376

1

T115

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

15

1

T41

4

T168

1

T259

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T119

1

T379

1

T380

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T381

1

T215

1

T293

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T34

1

T43

1

T168

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T376

2

T226

1

T228

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T168

1

T113

1

T382

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T96

1

T257

2

T115

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T93

1

T43

1

T259

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T228

2

T286

1

T383

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T96

1

T259

1

T286

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T42

1

T41

1

T381

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

145

1

T34

1

T96

6

T244

3

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	[auto[0]]	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T21

1

T97

2

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T34

1

T43

1

T372

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T42

2

T97

1

T40

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T34

2

T96

1

T244

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T34

1

T42

1

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T96

1

T168

1

T259

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T42

2

T97

2

T41

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T96

2

T244

1

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T97

1

T172

1

T107

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T34

2

T96

1

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T21

1

T97

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T40

5

T283

1

T284

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T21

1

T258

1

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T34

1

T244

3

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T21

1

T92

1

T172

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T244

1

T168

1

T284

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

48

1

T21

1

T40

4

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

43

1

T34

2

T96

2

T43

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

35

1

T41

1

T43

1

T255

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T92

2

T43

1

T284

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T21

2

T42

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T168

1

T259

1

T257

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

74

1

T21

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T244

1

T43

2

T168

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T13

1

T42

1

T43

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T42

1

T168

1

T259

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T13

1

T21

1

T42

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

50

1

T13

4

T34

2

T244

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T97

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T34

1

T96

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

62

1

T97

1

T92

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

57

1

T92

4

T168

1

T257

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

51

1

T97

1

T41

1

T43

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T283

1

T284

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

47

1

T97

2

T93

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T34

1

T96

1

T244

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T21

1

T96

1

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T34

1

T244

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

30

1

T21

1

T42

1

T172

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T42

7

T96

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T21

2

T97

1

T41

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T244

3

T41

4

T168

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T21

1

T41

1

T172

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T96

1

T244

1

T168

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T21

2

T43

1

T294

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T96

1

T244

2

T259

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

53

1

T97

1

T44

6

T384

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

61

1

T34

1

T41

2

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T21

2

T43

2

T172

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T34

1

T283

1

T113

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T97

1

T92

2

T244

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

42

1

T34

1

T96

1

T92

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T172

2

T258

1

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

35

1

T96

2

T244

1

T43

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T93

1

T172

1

T266

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

78

1

T34

2

T93

10

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T13

1

T42

1

T43

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T259

1

T283

1

T113

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T13

1

T21

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

79

1

T13

7

T96

3

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T97

2

T258

1

T262

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T42

2

T41

3

T283

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

151

1

T21

1

T34

5

T97

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

127

1

T34

1

T96

7

T244

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T385

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T386

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T41

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T387

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

31

1

T43

3

T168

4

T285

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	25	71	73.96	25
Automatically Generated Cross Bins	96	25	71	73.96	25
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[0]]	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T21

1

T97

2

T92

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T34

1

T43

1

T372

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T42

1

T97

1

T40

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

29

1

T34

2

T96

1

T244

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T34

1

T42

1

T97

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T96

1

T168

1

T259

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T42

2

T97

2

T41

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T96

2

T244

1

T43

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T97

1

T172

1

T107

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T34

2

T96

1

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

34

1

T21

1

T97

1

T40

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T40

5

T283

1

T284

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

29

1

T21

1

T258

1

T254

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T34

1

T244

3

T168

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T21

1

T92

1

T172

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T244

1

T168

1

T284

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T21

1

T40

4

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

43

1

T34

2

T96

2

T43

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T41

1

T43

1

T255

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T92

2

T43

1

T284

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

46

1

T21

2

T42

1

T41

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

25

1

T168

1

T259

1

T257

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T21

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

51

1

T244

1

T43

2

T168

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T13

1

T42

1

T43

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T42

1

T168

1

T259

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T13

1

T21

1

T42

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T13

2

T34

2

T244

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T97

1

T43

1

T172

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T34

1

T96

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T97

1

T92

1

T43

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

57

1

T92

4

T168

1

T257

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T97

1

T41

1

T43

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T43

1

T283

1

T284

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T97

2

T93

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T34

1

T96

1

T244

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

33

1

T21

1

T96

1

T97

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T34

1

T244

1

T43

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

31

1

T21

1

T172

1

T384

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

31

1

T42

7

T96

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T21

2

T97

1

T43

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T244

3

T41

4

T168

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

33

1

T21

1

T41

2

T172

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

26

1

T96

1

T244

1

T168

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T21

2

T43

1

T294

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T96

1

T244

2

T259

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

55

1

T97

1

T41

2

T44

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

61

1

T34

1

T41

2

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T21

2

T43

2

T172

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

29

1

T34

1

T283

1

T113

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T97

1

T92

2

T244

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

41

1

T34

1

T96

1

T92

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T172

2

T258

1

T257

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

35

1

T96

2

T244

1

T43

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

60

1

T93

1

T172

1

T266

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

79

1

T34

2

T93

10

T43

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T13

1

T42

1

T43

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

40

1

T259

1

T283

1

T113

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

75

1

T13

1

T21

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

79

1

T13

7

T96

3

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T97

2

T258

1

T262

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T42

2

T41

3

T283

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

194

1

T21

4

T34

5

T97

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

146

1

T34

1

T96

7

T244

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T375

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T375

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T13

2

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T41

1

T380

2

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T380

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T388

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T259

2

T372

1

T376

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded