Design Hierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb 98.84 99.29 97.93 100.00 96.79 99.52 99.52
dut 98.84 99.29 97.93 100.00 96.79 99.52 99.52
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
sysrst_ctrl_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00
u_prim_flop_2sync_input 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_reg 99.52 99.38 98.40 100.00 99.80 100.00
subtree...
u_sysrst_ctrl_autoblock 98.92 100.00 94.59 100.00 100.00 100.00
u_sysrst_ctrl_detect 98.18 100.00 90.91 100.00 100.00 100.00
u_sysrst_ctrl_combo 99.63 100.00 98.14 100.00 100.00 100.00
gen_combo_trigger[0].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect 99.09 100.00 95.45 100.00 100.00 100.00
gen_combo_trigger[0].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[1].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[2].u_sysrst_ctrl_detect_pre 100.00 100.00 100.00 100.00 100.00 100.00
gen_combo_trigger[3].u_combo_act 99.19 100.00 97.56 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect 99.09 100.00 95.45 100.00 100.00 100.00
gen_combo_trigger[3].u_sysrst_ctrl_detect_pre 98.95 100.00 94.74 100.00 100.00 100.00
u_sysrst_ctrl_intr 98.61 100.00 94.44 100.00 100.00
u_match_sync 93.75 100.00 75.00 100.00 100.00
gen_nrz_hs_protocol.ack_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
gen_nrz_hs_protocol.req_sync 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_intr_o 100.00 100.00 100.00 100.00 100.00
u_sysrst_ctrl_keyintr 96.07 97.84 93.83 94.05 96.94 97.70
gen_keyfsm[0].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
gen_keyfsm[0].u_sysrst_ctrl_detect_l2h 97.70 97.83 95.45 100.00 95.24 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_h2l 99.09 100.00 95.45 100.00 100.00 100.00
gen_keyfsm[1].u_sysrst_ctrl_detect_l2h 91.69 95.65 90.91 83.33 95.24 93.33
gen_keyfsm[2].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
gen_keyfsm[2].u_sysrst_ctrl_detect_l2h 97.70 97.83 95.45 100.00 95.24 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_h2l 99.09 100.00 95.45 100.00 100.00 100.00
gen_keyfsm[3].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
gen_keyfsm[4].u_sysrst_ctrl_detect_h2l 90.39 93.48 90.91 83.33 90.48 93.75
gen_keyfsm[4].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
gen_keyfsm[5].u_sysrst_ctrl_detect_h2l 91.78 95.65 90.91 83.33 95.24 93.75
gen_keyfsm[5].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_h2l 97.70 97.83 95.45 100.00 95.24 100.00
gen_keyfsm[6].u_sysrst_ctrl_detect_l2h 99.09 100.00 95.45 100.00 100.00 100.00
u_sysrst_ctrl_pin 100.00 100.00 100.00 100.00
u_cfg_ac_present_i_pin 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_1 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sync_2 100.00 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00 100.00
u_sysrst_ctrl_ulp 99.03 100.00 95.16 100.00 100.00 100.00
u_sysrst_ctrl_detect_ac_present 98.75 100.00 93.75 100.00 100.00 100.00
u_sysrst_ctrl_detect_lid_open 98.95 100.00 94.74 100.00 100.00 100.00
u_sysrst_ctrl_detect_pwrb 98.95 100.00 94.74 100.00 100.00 100.00
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