Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.03 99.29 97.93 100.00 96.79 99.52 99.52 86.18


Total tests in report: 910
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
43.55 43.55 65.74 65.74 44.53 44.53 58.11 58.11 10.26 10.26 69.27 69.27 53.56 53.56 3.40 3.40 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3457922544
69.42 25.87 88.96 23.22 76.41 31.88 64.27 6.16 71.79 61.54 89.55 20.27 85.84 32.27 9.12 5.72 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4208471918
76.87 7.45 92.38 3.42 84.22 7.81 91.21 26.94 71.79 0.00 93.07 3.52 87.09 1.25 18.35 9.23 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3531090340
79.61 2.73 94.97 2.58 88.34 4.12 93.49 2.28 71.79 0.00 95.63 2.56 88.44 1.35 24.58 6.23 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.308214370
81.98 2.37 95.51 0.54 89.71 1.37 94.75 1.26 71.79 0.00 95.96 0.33 88.63 0.19 37.49 12.91 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.135799531
83.74 1.76 95.94 0.43 90.52 0.81 95.43 0.68 73.72 1.92 96.33 0.37 89.40 0.77 44.85 7.36 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3298070997
85.28 1.54 96.78 0.84 91.43 0.91 95.66 0.23 79.49 5.77 96.96 0.63 91.43 2.02 45.24 0.40 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2852730987
86.82 1.53 97.12 0.34 92.04 0.61 95.66 0.00 80.13 0.64 97.03 0.07 91.71 0.29 54.02 8.78 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.806744259
88.26 1.44 97.68 0.56 92.06 0.03 95.66 0.00 89.10 8.97 97.55 0.52 91.71 0.00 54.02 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.4016537398
89.20 0.94 97.68 0.00 92.16 0.10 95.66 0.00 89.10 0.00 97.55 0.00 91.91 0.19 60.31 6.29 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1124296466
90.11 0.91 97.70 0.02 92.39 0.23 96.35 0.68 89.10 0.00 97.59 0.04 91.91 0.00 65.74 5.44 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3240519025
90.79 0.68 97.70 0.00 92.57 0.18 97.26 0.91 89.10 0.00 97.59 0.00 95.47 3.56 65.86 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1297445127
91.34 0.55 98.20 0.51 93.83 1.26 97.95 0.68 89.10 0.00 98.30 0.70 96.05 0.58 65.97 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.900224155
91.86 0.52 98.32 0.11 94.36 0.53 97.95 0.00 91.03 1.92 98.41 0.11 97.01 0.96 65.97 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3078406016
92.32 0.46 98.37 0.06 95.27 0.91 97.95 0.00 91.03 0.00 98.48 0.07 97.01 0.00 68.12 2.15 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444807001
92.74 0.42 98.43 0.06 95.37 0.10 97.95 0.00 91.03 0.00 98.48 0.00 97.11 0.10 70.84 2.72 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2153041388
93.08 0.34 98.50 0.07 95.45 0.08 97.95 0.00 91.03 0.00 98.55 0.07 97.11 0.00 72.99 2.15 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2779048745
93.41 0.33 98.60 0.09 95.65 0.20 97.95 0.00 92.31 1.28 98.67 0.11 97.50 0.39 73.22 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.960040165
93.73 0.32 98.60 0.00 95.70 0.05 99.77 1.83 92.31 0.00 98.67 0.00 97.59 0.10 73.50 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3480781875
93.98 0.25 98.69 0.09 95.78 0.08 99.77 0.00 93.59 1.28 98.78 0.11 97.78 0.19 73.50 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.4272141525
94.21 0.23 98.73 0.04 95.80 0.03 99.77 0.00 93.59 0.00 98.78 0.00 97.78 0.00 75.03 1.53 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.1682261129
94.42 0.21 98.73 0.00 95.80 0.00 99.77 0.00 93.59 0.00 98.78 0.00 97.78 0.00 76.50 1.47 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2915164987
94.62 0.20 98.76 0.04 95.88 0.08 99.77 0.00 94.23 0.64 98.81 0.04 97.88 0.10 77.01 0.51 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3532319574
94.81 0.19 98.80 0.04 96.08 0.20 99.77 0.00 94.87 0.64 98.85 0.04 98.27 0.39 77.01 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1823890590
94.99 0.18 98.84 0.04 96.26 0.18 99.77 0.00 94.87 0.00 98.93 0.07 98.94 0.67 77.29 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3275698799
95.14 0.15 98.84 0.00 96.36 0.10 99.77 0.00 94.87 0.00 98.93 0.00 98.94 0.00 78.26 0.96 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4181813498
95.28 0.15 98.91 0.07 96.41 0.05 99.77 0.00 95.51 0.64 99.04 0.11 99.04 0.10 78.31 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.1387724034
95.42 0.13 98.95 0.04 96.46 0.05 99.77 0.00 96.15 0.64 99.07 0.04 99.13 0.10 78.37 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.386096636
95.55 0.13 98.99 0.04 96.49 0.03 99.77 0.00 96.15 0.00 99.07 0.00 99.13 0.00 79.22 0.85 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2434152683
95.67 0.13 98.99 0.00 97.32 0.83 99.77 0.00 96.15 0.00 99.07 0.00 99.13 0.00 79.28 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3407235259
95.79 0.12 99.03 0.04 97.35 0.03 99.77 0.00 96.79 0.64 99.11 0.04 99.23 0.10 79.28 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3128670127
95.90 0.11 99.03 0.00 97.42 0.08 99.77 0.00 96.79 0.00 99.11 0.00 99.23 0.00 79.95 0.68 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2846700950
96.01 0.11 99.03 0.00 97.42 0.00 99.77 0.00 96.79 0.00 99.11 0.00 99.23 0.00 80.69 0.74 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.354172637
96.10 0.09 99.03 0.00 97.42 0.00 99.77 0.00 96.79 0.00 99.11 0.00 99.23 0.00 81.31 0.62 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.923504978
96.16 0.06 99.03 0.00 97.42 0.00 99.77 0.00 96.79 0.00 99.11 0.00 99.23 0.00 81.77 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.574096639
96.22 0.06 99.03 0.00 97.42 0.00 99.77 0.00 96.79 0.00 99.11 0.00 99.23 0.00 82.22 0.45 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.476937624
96.28 0.06 99.03 0.00 97.45 0.03 99.77 0.00 96.79 0.00 99.11 0.00 99.33 0.10 82.50 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3308658215
96.34 0.06 99.10 0.07 97.52 0.08 99.77 0.00 96.79 0.00 99.26 0.15 99.42 0.10 82.50 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2045173758
96.39 0.05 99.16 0.06 97.60 0.08 100.00 0.23 96.79 0.00 99.26 0.00 99.42 0.00 82.50 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2968560403
96.44 0.05 99.16 0.00 97.72 0.13 100.00 0.00 96.79 0.00 99.26 0.00 99.52 0.10 82.62 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.81620357
96.48 0.04 99.16 0.00 97.72 0.00 100.00 0.00 96.79 0.00 99.26 0.00 99.52 0.00 82.90 0.28 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1299848390
96.51 0.03 99.16 0.00 97.72 0.00 100.00 0.00 96.79 0.00 99.26 0.00 99.52 0.00 83.13 0.23 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.4180874738
96.54 0.03 99.16 0.00 97.75 0.03 100.00 0.00 96.79 0.00 99.30 0.04 99.52 0.00 83.24 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.62535371
96.56 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 83.41 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.920395959
96.59 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 83.58 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3986731725
96.61 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 83.75 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1067163055
96.63 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 83.92 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.239518263
96.66 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.09 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1907547499
96.68 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.26 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.532118139
96.71 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.43 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.317561770
96.73 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.60 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2431784739
96.75 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.77 0.17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.254047799
96.77 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.88 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1050247701
96.79 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 84.99 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1489742765
96.80 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 85.11 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3354250940
96.82 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 85.22 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2022926769
96.84 0.02 99.16 0.00 97.75 0.00 100.00 0.00 96.79 0.00 99.30 0.00 99.52 0.00 85.33 0.11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2120861752
96.85 0.02 99.18 0.02 97.75 0.00 100.00 0.00 96.79 0.00 99.33 0.04 99.52 0.00 85.39 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2874242451
96.87 0.02 99.21 0.04 97.75 0.00 100.00 0.00 96.79 0.00 99.41 0.07 99.52 0.00 85.39 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2720797434
96.88 0.01 99.21 0.00 97.77 0.03 100.00 0.00 96.79 0.00 99.41 0.00 99.52 0.00 85.45 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3039440560
96.89 0.01 99.21 0.00 97.80 0.03 100.00 0.00 96.79 0.00 99.41 0.00 99.52 0.00 85.50 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.3983078341
96.90 0.01 99.23 0.02 97.83 0.03 100.00 0.00 96.79 0.00 99.44 0.04 99.52 0.00 85.50 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.551476056
96.91 0.01 99.25 0.02 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.56 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2783107924
96.92 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.62 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1076167634
96.93 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.67 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1662745975
96.94 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.73 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2433679502
96.95 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.79 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2555904109
96.95 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.84 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.1716082532
96.96 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.90 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2151487735
96.97 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 85.96 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.1900525558
96.98 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 86.01 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.4131654170
96.99 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 86.07 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.249571109
96.99 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 86.13 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3693510708
97.00 0.01 99.25 0.00 97.83 0.00 100.00 0.00 96.79 0.00 99.44 0.00 99.52 0.00 86.18 0.06 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1274415899
97.01 0.01 99.27 0.02 97.83 0.00 100.00 0.00 96.79 0.00 99.48 0.04 99.52 0.00 86.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.577244644
97.02 0.01 99.29 0.02 97.83 0.00 100.00 0.00 96.79 0.00 99.52 0.04 99.52 0.00 86.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1024565255
97.03 0.01 99.29 0.00 97.88 0.05 100.00 0.00 96.79 0.00 99.52 0.00 99.52 0.00 86.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2885358265
97.03 0.01 99.29 0.00 97.93 0.05 100.00 0.00 96.79 0.00 99.52 0.00 99.52 0.00 86.18 0.00 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.453154191

Tests that do not contribute to grading

Name   
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3094559945
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3291853484
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.322969165
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.2517933130
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2707874411
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2957552218
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2135893902
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4096574645
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.291076725
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1625824957
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3915761406
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1206488932
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1694941477
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2357719798
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2472382276
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3436956537
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1742485893
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2768398450
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.4235570406
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.812713874
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.724289613
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3072415775
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1264184720
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.12266777
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3042141943
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1440408954
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.173925179
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.3378467122
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2224427309
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1945397368
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2221138871
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1027021274
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3147149579
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3283918781
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3442385623
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2147130163
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.824852229
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1129019662
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.658759612
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1069350732
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3960162332
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3577454110
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.134179388
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2002490898
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1683636278
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.920199083
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2590422738
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3035695244
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3522815251
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.317771151
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1726169974
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.92637123
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1890284538
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3444011903
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.702647447
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.438279628
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/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.279690386
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2561232017
/workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3674309717
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Total test records in report: 910
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2408311817 Oct 02 10:40:48 PM UTC 24 Oct 02 10:40:52 PM UTC 24 2145737612 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1452602096 Oct 02 10:40:49 PM UTC 24 Oct 02 10:40:52 PM UTC 24 2350123048 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1321750487 Oct 02 10:40:49 PM UTC 24 Oct 02 10:40:53 PM UTC 24 2138633364 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.900224155 Oct 02 10:40:49 PM UTC 24 Oct 02 10:40:53 PM UTC 24 2222999670 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.308214370 Oct 02 10:40:48 PM UTC 24 Oct 02 10:40:54 PM UTC 24 2454419112 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.4181813498 Oct 02 10:40:51 PM UTC 24 Oct 02 10:40:55 PM UTC 24 3286492425 ps
T1 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3523141831 Oct 02 10:40:53 PM UTC 24 Oct 02 10:40:57 PM UTC 24 5276514208 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2066480846 Oct 02 10:40:50 PM UTC 24 Oct 02 10:40:57 PM UTC 24 2611107088 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.3457922544 Oct 02 10:40:53 PM UTC 24 Oct 02 10:40:58 PM UTC 24 3224197367 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3039440560 Oct 02 10:40:49 PM UTC 24 Oct 02 10:40:59 PM UTC 24 2508419880 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.2580725027 Oct 02 10:40:55 PM UTC 24 Oct 02 10:41:00 PM UTC 24 2122348676 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3419367703 Oct 02 10:40:58 PM UTC 24 Oct 02 10:41:01 PM UTC 24 2317631798 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.461111339 Oct 02 10:40:59 PM UTC 24 Oct 02 10:41:03 PM UTC 24 2635492299 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2968560403 Oct 02 10:40:55 PM UTC 24 Oct 02 10:41:04 PM UTC 24 2013979235 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.2850497692 Oct 02 10:40:54 PM UTC 24 Oct 02 10:41:05 PM UTC 24 5907562061 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.3078406016 Oct 02 10:41:02 PM UTC 24 Oct 02 10:41:07 PM UTC 24 4241777086 ps
T84 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.2773425148 Oct 02 10:40:59 PM UTC 24 Oct 02 10:41:07 PM UTC 24 2510818415 ps
T56 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2925723875 Oct 02 10:40:57 PM UTC 24 Oct 02 10:41:07 PM UTC 24 2255334568 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.2163519528 Oct 02 10:40:56 PM UTC 24 Oct 02 10:41:09 PM UTC 24 2461814528 ps
T69 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3798554021 Oct 02 10:41:00 PM UTC 24 Oct 02 10:41:10 PM UTC 24 2778426710 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1297445127 Oct 02 10:41:04 PM UTC 24 Oct 02 10:41:12 PM UTC 24 5467793781 ps
T182 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.216103906 Oct 02 10:40:59 PM UTC 24 Oct 02 10:41:13 PM UTC 24 2144965776 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.3655316006 Oct 02 10:41:09 PM UTC 24 Oct 02 10:41:13 PM UTC 24 2487407485 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1489742765 Oct 02 10:41:00 PM UTC 24 Oct 02 10:41:14 PM UTC 24 3446257111 ps
T183 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.871355844 Oct 02 10:41:12 PM UTC 24 Oct 02 10:41:16 PM UTC 24 2207609124 ps
T297 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.4038092682 Oct 02 10:41:08 PM UTC 24 Oct 02 10:41:17 PM UTC 24 2010455022 ps
T70 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4168502988 Oct 02 10:40:51 PM UTC 24 Oct 02 10:41:17 PM UTC 24 4346424195 ps
T71 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3769305924 Oct 02 10:41:04 PM UTC 24 Oct 02 10:41:17 PM UTC 24 8911604472 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3789297813 Oct 02 10:41:08 PM UTC 24 Oct 02 10:41:18 PM UTC 24 2111245075 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.927377025 Oct 02 10:41:45 PM UTC 24 Oct 02 10:41:49 PM UTC 24 2119964340 ps
T85 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3531090340 Oct 02 10:41:13 PM UTC 24 Oct 02 10:41:18 PM UTC 24 2528167600 ps
T57 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3780458915 Oct 02 10:41:10 PM UTC 24 Oct 02 10:41:19 PM UTC 24 2261880403 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3412698255 Oct 02 10:41:15 PM UTC 24 Oct 02 10:41:20 PM UTC 24 3367387113 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3881023597 Oct 02 10:41:17 PM UTC 24 Oct 02 10:41:21 PM UTC 24 2847179970 ps
T72 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3153872528 Oct 02 10:41:14 PM UTC 24 Oct 02 10:41:21 PM UTC 24 2506191035 ps
T298 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.11542730 Oct 02 10:41:19 PM UTC 24 Oct 02 10:41:22 PM UTC 24 2038322299 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4096458162 Oct 02 10:41:11 PM UTC 24 Oct 02 10:41:22 PM UTC 24 2536259267 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.2883057488 Oct 02 10:41:21 PM UTC 24 Oct 02 10:41:26 PM UTC 24 2174024041 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3323650522 Oct 02 10:41:19 PM UTC 24 Oct 02 10:41:27 PM UTC 24 2115974589 ps
T86 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.715580952 Oct 02 10:41:23 PM UTC 24 Oct 02 10:41:27 PM UTC 24 2661817519 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.562734002 Oct 02 10:41:21 PM UTC 24 Oct 02 10:41:28 PM UTC 24 2429356740 ps
T77 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.2404165031 Oct 02 10:41:20 PM UTC 24 Oct 02 10:41:28 PM UTC 24 2469073498 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.4208471918 Oct 02 10:40:54 PM UTC 24 Oct 02 10:41:28 PM UTC 24 40623619228 ps
T65 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1995359537 Oct 02 10:41:13 PM UTC 24 Oct 02 10:41:29 PM UTC 24 2612385528 ps
T58 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3160440453 Oct 02 10:41:21 PM UTC 24 Oct 02 10:41:30 PM UTC 24 2353274685 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1183060916 Oct 02 10:41:27 PM UTC 24 Oct 02 10:41:31 PM UTC 24 3914280099 ps
T66 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2846700950 Oct 02 10:41:23 PM UTC 24 Oct 02 10:41:32 PM UTC 24 2518323174 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.2669114773 Oct 02 10:41:28 PM UTC 24 Oct 02 10:41:34 PM UTC 24 3162183171 ps
T67 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2419297472 Oct 02 10:41:24 PM UTC 24 Oct 02 10:41:34 PM UTC 24 3389588650 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.1076167634 Oct 02 10:40:53 PM UTC 24 Oct 02 10:41:35 PM UTC 24 52690590365 ps
T94 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.389099622 Oct 02 10:41:33 PM UTC 24 Oct 02 10:41:35 PM UTC 24 2140347354 ps
T95 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1602176086 Oct 02 10:41:18 PM UTC 24 Oct 02 10:41:36 PM UTC 24 6708561650 ps
T150 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.3343894200 Oct 02 10:41:35 PM UTC 24 Oct 02 10:41:38 PM UTC 24 2104539158 ps
T151 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.2957906683 Oct 02 10:41:30 PM UTC 24 Oct 02 10:41:39 PM UTC 24 2022790325 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.890640538 Oct 02 10:41:35 PM UTC 24 Oct 02 10:41:40 PM UTC 24 2331827138 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2443233336 Oct 02 10:41:29 PM UTC 24 Oct 02 10:41:40 PM UTC 24 5359399424 ps
T73 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3472524729 Oct 02 10:41:38 PM UTC 24 Oct 02 10:41:42 PM UTC 24 3871911546 ps
T78 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.1400722664 Oct 02 10:41:33 PM UTC 24 Oct 02 10:41:43 PM UTC 24 2452646675 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.1527654924 Oct 02 10:41:36 PM UTC 24 Oct 02 10:41:44 PM UTC 24 2519148907 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3270226020 Oct 02 10:41:01 PM UTC 24 Oct 02 10:41:45 PM UTC 24 88671488647 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2945582453 Oct 02 10:41:35 PM UTC 24 Oct 02 10:41:46 PM UTC 24 2396961626 ps
T274 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2920095998 Oct 02 10:41:44 PM UTC 24 Oct 02 10:41:48 PM UTC 24 2038703537 ps
T79 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.336309110 Oct 02 10:41:45 PM UTC 24 Oct 02 10:41:50 PM UTC 24 2473274880 ps
T275 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2398278519 Oct 02 10:41:36 PM UTC 24 Oct 02 10:41:50 PM UTC 24 2609061851 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.61983085 Oct 02 10:41:39 PM UTC 24 Oct 02 10:41:50 PM UTC 24 2685764275 ps
T276 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1672970286 Oct 02 10:41:47 PM UTC 24 Oct 02 10:41:51 PM UTC 24 3091014415 ps
T277 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.997347572 Oct 02 10:41:46 PM UTC 24 Oct 02 10:41:51 PM UTC 24 2515400884 ps
T278 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3227982280 Oct 02 10:41:46 PM UTC 24 Oct 02 10:41:53 PM UTC 24 2616928699 ps
T74 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4022275881 Oct 02 10:41:49 PM UTC 24 Oct 02 10:41:53 PM UTC 24 7746841058 ps
T438 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.1964508861 Oct 02 10:41:52 PM UTC 24 Oct 02 10:41:55 PM UTC 24 2141858168 ps
T295 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3252339697 Oct 02 10:41:19 PM UTC 24 Oct 02 10:41:57 PM UTC 24 22012870518 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3480781875 Oct 02 10:40:54 PM UTC 24 Oct 02 10:41:57 PM UTC 24 42034314554 ps
T317 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.1900063812 Oct 02 10:41:52 PM UTC 24 Oct 02 10:41:57 PM UTC 24 2018144080 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.2207591348 Oct 02 10:41:54 PM UTC 24 Oct 02 10:41:57 PM UTC 24 2083850707 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.3839202009 Oct 02 10:41:44 PM UTC 24 Oct 02 10:41:58 PM UTC 24 2113435638 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1304159301 Oct 02 10:41:41 PM UTC 24 Oct 02 10:41:59 PM UTC 24 10148280248 ps
T59 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.719963926 Oct 02 10:41:29 PM UTC 24 Oct 02 10:41:59 PM UTC 24 7812453263 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.3308658215 Oct 02 10:40:53 PM UTC 24 Oct 02 10:41:59 PM UTC 24 85432463634 ps
T125 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.668387494 Oct 02 10:41:54 PM UTC 24 Oct 02 10:42:00 PM UTC 24 2523548089 ps
T126 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3000859023 Oct 02 10:41:55 PM UTC 24 Oct 02 10:42:00 PM UTC 24 2635431331 ps
T80 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.2907395537 Oct 02 10:41:54 PM UTC 24 Oct 02 10:42:00 PM UTC 24 2485485348 ps
T127 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1552913687 Oct 02 10:41:29 PM UTC 24 Oct 02 10:42:01 PM UTC 24 22051824035 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.984107680 Oct 02 10:41:51 PM UTC 24 Oct 02 10:42:01 PM UTC 24 2852557921 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.2045173758 Oct 02 10:41:58 PM UTC 24 Oct 02 10:42:02 PM UTC 24 5237669234 ps
T128 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.2254636766 Oct 02 10:42:35 PM UTC 24 Oct 02 10:42:39 PM UTC 24 2186855618 ps
T129 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1795001039 Oct 02 10:41:55 PM UTC 24 Oct 02 10:42:04 PM UTC 24 2592679280 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.1739748275 Oct 02 10:42:00 PM UTC 24 Oct 02 10:42:05 PM UTC 24 2039467988 ps
T60 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3806836647 Oct 02 10:41:48 PM UTC 24 Oct 02 10:42:05 PM UTC 24 3386578249 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3184524714 Oct 02 10:41:43 PM UTC 24 Oct 02 10:42:05 PM UTC 24 22053289738 ps
T239 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3634062897 Oct 02 10:42:01 PM UTC 24 Oct 02 10:42:07 PM UTC 24 2523825227 ps
T240 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1739140057 Oct 02 10:42:35 PM UTC 24 Oct 02 10:42:38 PM UTC 24 2060658646 ps
T241 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.318385516 Oct 02 10:42:01 PM UTC 24 Oct 02 10:42:07 PM UTC 24 2629978070 ps
T242 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1367760946 Oct 02 10:42:00 PM UTC 24 Oct 02 10:42:07 PM UTC 24 2109387118 ps
T61 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3298070997 Oct 02 10:41:51 PM UTC 24 Oct 02 10:42:08 PM UTC 24 48074118413 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3235629509 Oct 02 10:41:51 PM UTC 24 Oct 02 10:42:09 PM UTC 24 27594989845 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.135799531 Oct 02 10:41:02 PM UTC 24 Oct 02 10:42:09 PM UTC 24 78958157738 ps
T439 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.843131894 Oct 02 10:42:06 PM UTC 24 Oct 02 10:42:09 PM UTC 24 2088390189 ps
T54 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.709805718 Oct 02 10:42:05 PM UTC 24 Oct 02 10:42:09 PM UTC 24 2998293614 ps
T440 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1456303383 Oct 02 10:42:01 PM UTC 24 Oct 02 10:42:13 PM UTC 24 2159689736 ps
T81 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.3414740677 Oct 02 10:42:07 PM UTC 24 Oct 02 10:42:13 PM UTC 24 2477361174 ps
T441 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.3475268953 Oct 02 10:42:09 PM UTC 24 Oct 02 10:42:13 PM UTC 24 2074812177 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.358088779 Oct 02 10:42:11 PM UTC 24 Oct 02 10:42:15 PM UTC 24 2964603413 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.577244644 Oct 02 10:42:33 PM UTC 24 Oct 02 10:42:39 PM UTC 24 4687682679 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.4189797671 Oct 02 10:42:04 PM UTC 24 Oct 02 10:42:15 PM UTC 24 5555369017 ps
T174 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.1355238657 Oct 02 10:42:07 PM UTC 24 Oct 02 10:42:15 PM UTC 24 2121378336 ps
T175 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3608268000 Oct 02 10:42:10 PM UTC 24 Oct 02 10:42:15 PM UTC 24 2625482118 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2733799982 Oct 02 10:42:06 PM UTC 24 Oct 02 10:42:15 PM UTC 24 10721864859 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.2286382027 Oct 02 10:41:06 PM UTC 24 Oct 02 10:42:16 PM UTC 24 22012903557 ps
T82 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.1648616371 Oct 02 10:42:01 PM UTC 24 Oct 02 10:42:17 PM UTC 24 2470943872 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3532192754 Oct 02 10:42:14 PM UTC 24 Oct 02 10:42:18 PM UTC 24 2054199131 ps
T68 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2852730987 Oct 02 10:41:00 PM UTC 24 Oct 02 10:42:18 PM UTC 24 2242544750514 ps
T178 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.243705262 Oct 02 10:42:16 PM UTC 24 Oct 02 10:42:21 PM UTC 24 2116863650 ps
T179 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.938590331 Oct 02 10:42:13 PM UTC 24 Oct 02 10:42:22 PM UTC 24 9073611521 ps
T62 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3183495565 Oct 02 10:42:10 PM UTC 24 Oct 02 10:42:22 PM UTC 24 3634851752 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3286220584 Oct 02 10:42:18 PM UTC 24 Oct 02 10:42:23 PM UTC 24 4211632808 ps
T83 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.837931110 Oct 02 10:42:16 PM UTC 24 Oct 02 10:42:23 PM UTC 24 2481196156 ps
T235 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.805569171 Oct 02 10:42:09 PM UTC 24 Oct 02 10:42:23 PM UTC 24 2511838862 ps
T236 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.777488512 Oct 02 10:41:59 PM UTC 24 Oct 02 10:42:23 PM UTC 24 6240931612 ps
T63 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1669274310 Oct 02 10:41:58 PM UTC 24 Oct 02 10:42:25 PM UTC 24 160946920373 ps
T237 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1460551950 Oct 02 10:42:17 PM UTC 24 Oct 02 10:42:25 PM UTC 24 5450673339 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.1387724034 Oct 02 10:41:41 PM UTC 24 Oct 02 10:42:25 PM UTC 24 16639153015 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3902764196 Oct 02 10:42:10 PM UTC 24 Oct 02 10:42:25 PM UTC 24 2702842306 ps
T210 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.2621678755 Oct 02 10:42:16 PM UTC 24 Oct 02 10:42:26 PM UTC 24 2156941825 ps
T211 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1632466775 Oct 02 10:42:16 PM UTC 24 Oct 02 10:42:27 PM UTC 24 2514494429 ps
T212 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1485869236 Oct 02 10:42:16 PM UTC 24 Oct 02 10:42:27 PM UTC 24 2611079053 ps
T64 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4208067203 Oct 02 10:42:04 PM UTC 24 Oct 02 10:42:28 PM UTC 24 23888807905 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3444077417 Oct 02 10:42:18 PM UTC 24 Oct 02 10:42:28 PM UTC 24 3428912715 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3280691443 Oct 02 10:42:24 PM UTC 24 Oct 02 10:42:28 PM UTC 24 2641884078 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.140178950 Oct 02 10:42:25 PM UTC 24 Oct 02 10:42:28 PM UTC 24 7813973336 ps
T159 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3038338245 Oct 02 10:42:24 PM UTC 24 Oct 02 10:42:29 PM UTC 24 2530485615 ps
T160 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.251608164 Oct 02 10:42:22 PM UTC 24 Oct 02 10:42:29 PM UTC 24 2019825915 ps
T96 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.4254345081 Oct 02 10:41:17 PM UTC 24 Oct 02 10:42:29 PM UTC 24 157175618283 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.1100165448 Oct 02 10:42:24 PM UTC 24 Oct 02 10:42:29 PM UTC 24 2493022387 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3142839606 Oct 02 10:42:17 PM UTC 24 Oct 02 10:42:31 PM UTC 24 3412196384 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.737900130 Oct 02 10:42:24 PM UTC 24 Oct 02 10:42:31 PM UTC 24 2112612467 ps
T163 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.3309613368 Oct 02 10:42:23 PM UTC 24 Oct 02 10:42:32 PM UTC 24 2112080791 ps
T53 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.2391284647 Oct 02 10:42:27 PM UTC 24 Oct 02 10:42:33 PM UTC 24 3286742514 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1734954163 Oct 02 10:42:19 PM UTC 24 Oct 02 10:42:34 PM UTC 24 4861499007 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4175638718 Oct 02 10:42:30 PM UTC 24 Oct 02 10:42:34 PM UTC 24 2641253049 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.906117671 Oct 02 10:42:29 PM UTC 24 Oct 02 10:42:34 PM UTC 24 2473714620 ps
T443 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2337327255 Oct 02 10:42:30 PM UTC 24 Oct 02 10:42:35 PM UTC 24 2708221447 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.210814938 Oct 02 10:42:28 PM UTC 24 Oct 02 10:42:35 PM UTC 24 6500051436 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.1420280927 Oct 02 10:42:30 PM UTC 24 Oct 02 10:42:35 PM UTC 24 2526686598 ps
T419 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.990018909 Oct 02 10:42:14 PM UTC 24 Oct 02 10:42:36 PM UTC 24 6623501549 ps
T444 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2856897334 Oct 02 10:42:29 PM UTC 24 Oct 02 10:42:37 PM UTC 24 2112477748 ps
T445 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.873141931 Oct 02 10:42:29 PM UTC 24 Oct 02 10:42:38 PM UTC 24 2220217563 ps
T446 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.433403260 Oct 02 10:42:29 PM UTC 24 Oct 02 10:42:40 PM UTC 24 2017013785 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2842081635 Oct 02 10:42:30 PM UTC 24 Oct 02 10:42:40 PM UTC 24 3188458556 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1110144627 Oct 02 10:42:19 PM UTC 24 Oct 02 10:42:42 PM UTC 24 25608286506 ps
T447 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2704463856 Oct 02 10:42:28 PM UTC 24 Oct 02 10:42:42 PM UTC 24 4775992477 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.574096639 Oct 02 10:42:36 PM UTC 24 Oct 02 10:42:42 PM UTC 24 2533479075 ps
T448 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2266624238 Oct 02 10:42:35 PM UTC 24 Oct 02 10:42:42 PM UTC 24 2113030660 ps
T449 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.880616779 Oct 02 10:42:36 PM UTC 24 Oct 02 10:42:42 PM UTC 24 2621460457 ps
T335 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.162630253 Oct 02 10:42:35 PM UTC 24 Oct 02 10:42:42 PM UTC 24 2445486899 ps
T450 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3582973173 Oct 02 10:43:16 PM UTC 24 Oct 02 10:43:23 PM UTC 24 3548992835 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.472524825 Oct 02 10:42:31 PM UTC 24 Oct 02 10:42:44 PM UTC 24 9635140453 ps
T451 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2952147811 Oct 02 10:42:34 PM UTC 24 Oct 02 10:42:45 PM UTC 24 6659021612 ps
T55 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.3116461040 Oct 02 10:42:39 PM UTC 24 Oct 02 10:42:45 PM UTC 24 3185014511 ps
T322 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.502057559 Oct 02 10:42:25 PM UTC 24 Oct 02 10:42:47 PM UTC 24 3506946458 ps
T452 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.216403844 Oct 02 10:42:42 PM UTC 24 Oct 02 10:42:47 PM UTC 24 2117590338 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.2469227060 Oct 02 10:42:44 PM UTC 24 Oct 02 10:42:47 PM UTC 24 2597758566 ps
T453 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.3235287254 Oct 02 10:42:42 PM UTC 24 Oct 02 10:42:48 PM UTC 24 2152933873 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.3511423187 Oct 02 10:43:21 PM UTC 24 Oct 02 10:43:25 PM UTC 24 2022814366 ps
T98 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1943321247 Oct 02 10:42:39 PM UTC 24 Oct 02 10:42:48 PM UTC 24 6526032098 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.703151786 Oct 02 10:42:44 PM UTC 24 Oct 02 10:42:49 PM UTC 24 2636252451 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.1099555621 Oct 02 10:42:42 PM UTC 24 Oct 02 10:42:49 PM UTC 24 2469457543 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.801171461 Oct 02 10:42:45 PM UTC 24 Oct 02 10:42:50 PM UTC 24 3211298575 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3513064028 Oct 02 10:42:37 PM UTC 24 Oct 02 10:42:50 PM UTC 24 4227381274 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3691442143 Oct 02 10:42:44 PM UTC 24 Oct 02 10:42:50 PM UTC 24 3524639243 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2246949017 Oct 02 10:42:24 PM UTC 24 Oct 02 10:42:50 PM UTC 24 5636467888 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1381705795 Oct 02 10:42:48 PM UTC 24 Oct 02 10:42:51 PM UTC 24 2119703350 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.205393412 Oct 02 10:42:41 PM UTC 24 Oct 02 10:42:51 PM UTC 24 2015419716 ps
T217 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.551476056 Oct 02 10:42:46 PM UTC 24 Oct 02 10:42:52 PM UTC 24 5323458709 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2811423456 Oct 02 10:42:38 PM UTC 24 Oct 02 10:42:53 PM UTC 24 3900460843 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.950484854 Oct 02 10:42:50 PM UTC 24 Oct 02 10:42:53 PM UTC 24 2063154432 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.4029198345 Oct 02 10:42:50 PM UTC 24 Oct 02 10:42:54 PM UTC 24 2470500672 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.4016537398 Oct 02 10:41:02 PM UTC 24 Oct 02 10:42:55 PM UTC 24 34226972970 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.392659345 Oct 02 10:42:51 PM UTC 24 Oct 02 10:42:57 PM UTC 24 3215514774 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.428438713 Oct 02 10:42:51 PM UTC 24 Oct 02 10:42:57 PM UTC 24 2625087572 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3428082790 Oct 02 10:42:33 PM UTC 24 Oct 02 10:42:57 PM UTC 24 8047060684 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.1067163055 Oct 02 10:42:51 PM UTC 24 Oct 02 10:42:57 PM UTC 24 2514889030 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.26817218 Oct 02 10:42:55 PM UTC 24 Oct 02 10:42:59 PM UTC 24 2017128898 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.809132657 Oct 02 10:42:22 PM UTC 24 Oct 02 10:43:01 PM UTC 24 12375435213 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3983633970 Oct 02 10:42:50 PM UTC 24 Oct 02 10:43:02 PM UTC 24 2109621280 ps
T208 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1458208181 Oct 02 10:42:53 PM UTC 24 Oct 02 10:43:02 PM UTC 24 3084749024 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2649846966 Oct 02 10:42:52 PM UTC 24 Oct 02 10:43:02 PM UTC 24 9327769349 ps
T97 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3354250940 Oct 02 10:41:18 PM UTC 24 Oct 02 10:43:03 PM UTC 24 136026244297 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2628725866 Oct 02 10:43:00 PM UTC 24 Oct 02 10:43:03 PM UTC 24 3911371067 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.4205111868 Oct 02 10:42:58 PM UTC 24 Oct 02 10:43:05 PM UTC 24 2515914790 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2816317244 Oct 02 10:42:48 PM UTC 24 Oct 02 10:43:07 PM UTC 24 3999679522 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.3812023505 Oct 02 10:43:04 PM UTC 24 Oct 02 10:43:07 PM UTC 24 2174086090 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.1633713351 Oct 02 10:43:04 PM UTC 24 Oct 02 10:43:07 PM UTC 24 2110886670 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.2223485179 Oct 02 10:42:56 PM UTC 24 Oct 02 10:43:07 PM UTC 24 2111723369 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1050951632 Oct 02 10:42:51 PM UTC 24 Oct 02 10:43:07 PM UTC 24 3296029257 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1576689456 Oct 02 10:42:58 PM UTC 24 Oct 02 10:43:07 PM UTC 24 2446254823 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2182507289 Oct 02 10:42:59 PM UTC 24 Oct 02 10:43:08 PM UTC 24 2493247576 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.355429776 Oct 02 10:42:58 PM UTC 24 Oct 02 10:43:09 PM UTC 24 2060043328 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.4205384100 Oct 02 10:42:58 PM UTC 24 Oct 02 10:43:10 PM UTC 24 2611956693 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3403367392 Oct 02 10:42:54 PM UTC 24 Oct 02 10:43:11 PM UTC 24 9058970194 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.3758846950 Oct 02 10:43:04 PM UTC 24 Oct 02 10:43:12 PM UTC 24 2476079212 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3283156091 Oct 02 10:43:07 PM UTC 24 Oct 02 10:43:12 PM UTC 24 2626981628 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1172386154 Oct 02 10:43:08 PM UTC 24 Oct 02 10:43:13 PM UTC 24 3303001402 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.4125565673 Oct 02 10:42:48 PM UTC 24 Oct 02 10:43:15 PM UTC 24 8847835823 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.2901164868 Oct 02 10:43:07 PM UTC 24 Oct 02 10:43:16 PM UTC 24 2508076248 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3509094176 Oct 02 10:43:03 PM UTC 24 Oct 02 10:43:16 PM UTC 24 13564752201 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2980679650 Oct 02 10:43:13 PM UTC 24 Oct 02 10:43:16 PM UTC 24 2094598074 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3532319574 Oct 02 10:42:40 PM UTC 24 Oct 02 10:43:16 PM UTC 24 320082946992 ps
T152 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1816429709 Oct 02 10:43:07 PM UTC 24 Oct 02 10:43:17 PM UTC 24 3050515118 ps
T153 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3638318834 Oct 02 10:43:03 PM UTC 24 Oct 02 10:43:17 PM UTC 24 6422094088 ps
T154 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.4118416439 Oct 02 10:43:06 PM UTC 24 Oct 02 10:43:18 PM UTC 24 2173659349 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.960040165 Oct 02 10:42:00 PM UTC 24 Oct 02 10:43:18 PM UTC 24 17802583475 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.2029531301 Oct 02 10:43:03 PM UTC 24 Oct 02 10:43:20 PM UTC 24 3235355807 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.1728587691 Oct 02 10:43:15 PM UTC 24 Oct 02 10:43:20 PM UTC 24 2089746326 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.3839319103 Oct 02 10:43:09 PM UTC 24 Oct 02 10:43:20 PM UTC 24 3088775946 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.942978773 Oct 02 10:43:13 PM UTC 24 Oct 02 10:43:21 PM UTC 24 2108868150 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3653442310 Oct 02 10:43:16 PM UTC 24 Oct 02 10:43:21 PM UTC 24 2532445008 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3368998805 Oct 02 10:43:14 PM UTC 24 Oct 02 10:43:22 PM UTC 24 2478601990 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.948899315 Oct 02 10:43:18 PM UTC 24 Oct 02 10:43:22 PM UTC 24 6341368533 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.4036754815 Oct 02 10:43:19 PM UTC 24 Oct 02 10:43:23 PM UTC 24 3333897035 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.4175406455 Oct 02 10:43:09 PM UTC 24 Oct 02 10:43:23 PM UTC 24 2004874528996 ps
T199 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.3356410726 Oct 02 10:43:22 PM UTC 24 Oct 02 10:43:25 PM UTC 24 2265802914 ps
T200 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2369299475 Oct 02 10:43:22 PM UTC 24 Oct 02 10:43:25 PM UTC 24 2158945839 ps
T201 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3529050889 Oct 02 10:43:18 PM UTC 24 Oct 02 10:43:26 PM UTC 24 3661262179 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1929234343 Oct 02 10:43:22 PM UTC 24 Oct 02 10:43:26 PM UTC 24 2472451022 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.1644775622 Oct 02 10:43:16 PM UTC 24 Oct 02 10:43:27 PM UTC 24 2614840227 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.701130212 Oct 02 10:43:21 PM UTC 24 Oct 02 10:43:27 PM UTC 24 6179925856 ps
T91 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4171944323 Oct 02 10:42:40 PM UTC 24 Oct 02 10:43:28 PM UTC 24 28087647397 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.4124062237 Oct 02 10:43:23 PM UTC 24 Oct 02 10:43:28 PM UTC 24 2518726971 ps
T92 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.4175393866 Oct 02 10:42:33 PM UTC 24 Oct 02 10:43:29 PM UTC 24 32374465568 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2056667701 Oct 02 10:43:25 PM UTC 24 Oct 02 10:43:29 PM UTC 24 3579898160 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3924195791 Oct 02 10:42:55 PM UTC 24 Oct 02 10:43:29 PM UTC 24 6721552682 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.681322076 Oct 02 10:43:23 PM UTC 24 Oct 02 10:43:30 PM UTC 24 2620882691 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1330772585 Oct 02 10:43:25 PM UTC 24 Oct 02 10:43:30 PM UTC 24 2751132494 ps
T323 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.378527983 Oct 02 10:43:11 PM UTC 24 Oct 02 10:43:30 PM UTC 24 6120460176 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.4084475834 Oct 02 10:43:27 PM UTC 24 Oct 02 10:43:31 PM UTC 24 2029452743 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.90493559 Oct 02 10:43:28 PM UTC 24 Oct 02 10:43:32 PM UTC 24 2129091827 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.2329473007 Oct 02 10:43:28 PM UTC 24 Oct 02 10:43:32 PM UTC 24 2489391311 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.1924000161 Oct 02 10:43:30 PM UTC 24 Oct 02 10:43:33 PM UTC 24 2529429569 ps
T491 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3202647801 Oct 02 10:43:29 PM UTC 24 Oct 02 10:43:33 PM UTC 24 2183297575 ps
T492 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.419148046 Oct 02 10:44:01 PM UTC 24 Oct 02 10:44:10 PM UTC 24 2010212038 ps
T493 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1614785829 Oct 02 10:43:31 PM UTC 24 Oct 02 10:43:34 PM UTC 24 3229264181 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.386096636 Oct 02 10:43:21 PM UTC 24 Oct 02 10:43:34 PM UTC 24 13720201739 ps
T243 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3518497879 Oct 02 10:43:24 PM UTC 24 Oct 02 10:43:34 PM UTC 24 3580017743 ps
T149 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2188816661 Oct 02 10:43:31 PM UTC 24 Oct 02 10:43:35 PM UTC 24 3538938296 ps
T244 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.4197663895 Oct 02 10:41:50 PM UTC 24 Oct 02 10:43:38 PM UTC 24 76211836742 ps
T245 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.90109212 Oct 02 10:43:34 PM UTC 24 Oct 02 10:43:39 PM UTC 24 2472391228 ps
T191 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.2944386738 Oct 02 10:43:26 PM UTC 24 Oct 02 10:43:39 PM UTC 24 5249360462 ps
T189 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.908946817 Oct 02 10:43:32 PM UTC 24 Oct 02 10:43:39 PM UTC 24 3009501663 ps
T246 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1901901401 Oct 02 10:43:27 PM UTC 24 Oct 02 10:43:39 PM UTC 24 16609893301 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_02/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2783107924 Oct 02 10:41:29 PM UTC 24 Oct 02 10:43:40 PM UTC 24 107811021181 ps