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Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 96 30 66 68.75 30
Automatically Generated Cross Bins 96 30 66 68.75 30
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cross_combo3

Element holes
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[0]] * [auto[1]] -- -- 2
[auto[1]] [auto[0]] [auto[1]] [auto[1]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[0]] * * * [auto[1]] -- -- 8
[auto[1]] [auto[1]] [auto[1]] [auto[0]] * * [auto[1]] -- -- 4
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] * [auto[1]] -- -- 2


Uncovered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [auto[0]] [auto[1]] [auto[0]] [auto[1]] [auto[1]] [auto[1]] 0 1 1
[auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[1]] [auto[0]] [auto[1]] 0 1 1


Covered bins
cp_combo3_h2lcp_key0_in_selcp_key1_in_selcp_key2_in_selcp_pwrb_in_selcp_ac_present_selcp_interruptCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 40 1 T21 1 T97 2 T92 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 20 1 T34 1 T43 1 T372 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 49 1 T42 2 T97 1 T40 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 29 1 T34 2 T96 1 T244 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 49 1 T34 1 T42 1 T97 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 22 1 T96 1 T168 1 T259 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 41 1 T42 2 T97 2 T41 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 27 1 T96 2 T244 1 T43 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 45 1 T97 1 T172 1 T107 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 24 1 T34 2 T96 1 T168 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 36 1 T21 1 T97 1 T40 4
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 28 1 T40 5 T283 1 T284 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 30 1 T21 1 T258 1 T254 2
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 20 1 T34 1 T244 3 T168 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 37 1 T21 1 T92 1 T172 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 19 1 T244 1 T168 1 T284 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 48 1 T21 1 T40 4 T41 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 43 1 T34 2 T96 2 T43 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 34 1 T41 1 T43 1 T255 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 23 1 T92 2 T43 1 T284 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 45 1 T21 2 T42 1 T41 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 23 1 T168 1 T259 1 T257 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 74 1 T21 1 T43 1 T172 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 51 1 T244 1 T43 2 T168 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 40 1 T13 1 T42 1 T43 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 22 1 T42 1 T168 1 T259 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 41 1 T13 1 T21 1 T42 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 51 1 T13 4 T34 2 T244 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 22 1 T97 1 T43 1 T172 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 45 1 T34 1 T96 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 62 1 T97 1 T92 1 T43 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 57 1 T92 4 T168 1 T257 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 52 1 T97 1 T41 1 T43 3
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 19 1 T43 1 T283 1 T284 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 47 1 T97 2 T93 1 T43 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 27 1 T34 1 T96 1 T244 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 29 1 T21 1 T96 1 T97 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 31 1 T34 1 T244 1 T43 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 31 1 T21 1 T42 1 T172 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 31 1 T42 7 T96 1 T43 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 43 1 T21 2 T97 1 T41 3
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 40 1 T244 3 T41 5 T168 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 37 1 T21 1 T41 2 T172 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 28 1 T96 1 T244 1 T168 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 37 1 T21 2 T43 1 T294 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 22 1 T96 1 T244 2 T259 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 52 1 T97 1 T41 2 T44 8
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 61 1 T34 1 T41 2 T43 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 46 1 T21 2 T43 2 T172 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 29 1 T34 1 T283 1 T113 2
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 61 1 T97 1 T92 2 T244 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 42 1 T34 1 T96 1 T92 3
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 33 1 T172 2 T258 1 T257 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 35 1 T96 2 T244 1 T43 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 57 1 T93 1 T172 1 T266 9
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 79 1 T34 2 T93 10 T43 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 47 1 T13 1 T42 1 T43 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 40 1 T259 1 T283 1 T113 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 75 1 T13 1 T21 1 T41 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 79 1 T13 7 T96 3 T41 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 40 1 T97 2 T258 1 T262 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 26 1 T42 2 T41 3 T283 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 134 1 T21 5 T97 4 T43 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 137 1 T34 1 T96 7 T244 4
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 2 1 T257 2 - - - -
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 21 1 T43 3 T372 1 T376 5


User Defined Cross Bins for cross_combo3

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded

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