Unified Coverage Report :: Group Instance : sysrst_ctrl_key_invert_ctl_cg_(1)

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Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	12	1			T421	5		T315	7
auto[0]	auto[1]	13	1			T421	7		T315	6
auto[1]	auto[0]	8	1			T421	5		T315	3
auto[1]	auto[1]	7	1			T421	3		T315	4

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Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	8	1			T421	2		T315	6
auto[0]	auto[1]	8	1			T421	6		T315	2
auto[1]	auto[0]	9	1			T421	4		T315	5
auto[1]	auto[1]	15	1			T421	8		T315	7

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Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	9	1			T421	6		T315	3
auto[0]	auto[1]	9	1			T421	6		T315	3
auto[1]	auto[0]	8	1			T421	4		T315	4
auto[1]	auto[1]	14	1			T421	4		T315	10

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Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	7	1			T421	5		T315	2
auto[0]	auto[1]	10	1			T421	6		T315	4
auto[1]	auto[0]	12	1			T421	5		T315	7
auto[1]	auto[1]	11	1			T421	4		T315	7

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Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	10	1			T421	5		T315	5
auto[0]	auto[1]	8	1			T421	3		T315	5
auto[1]	auto[0]	14	1			T421	8		T315	6
auto[1]	auto[1]	8	1			T421	4		T315	4

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Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	11	1			T421	3		T315	8
auto[0]	auto[1]	9	1			T421	6		T315	3
auto[1]	auto[0]	8	1			T421	4		T315	4
auto[1]	auto[1]	12	1			T421	7		T315	5

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Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	11	1			T421	5		T315	6
auto[0]	auto[1]	10	1			T421	5		T315	5
auto[1]	auto[0]	7	1			T421	5		T315	2
auto[1]	auto[1]	12	1			T421	5		T315	7

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Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	12	1			T421	5		T315	7
auto[0]	auto[1]	10	1			T421	6		T315	4
auto[1]	auto[0]	9	1			T421	5		T315	4
auto[1]	auto[1]	9	1			T421	4		T315	5

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Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	17	1			T421	10		T315	7
auto[1]	auto[1]	23	1			T421	10		T315	13

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

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Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	16	1			T421	8		T315	8
auto[0]	auto[1]	6	1			T421	3		T315	3
auto[1]	auto[0]	6	1			T421	3		T315	3
auto[1]	auto[1]	12	1			T421	6		T315	6

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Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	15	1			T421	4		T315	11
auto[1]	auto[1]	25	1			T421	16		T315	9

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded