Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1812

1

T32

4

T58

8

T37

12

auto[1]

640

1

T52

9

T37

12

T53

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1879

1

T32

4

T58

6

T52

9

auto[1]

573

1

T58

2

T38

4

T88

4

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1910

1

T32

3

T58

8

T52

9

auto[1]

542

1

T32

1

T37

9

T41

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1937

1

T32

3

T58

8

T52

5

auto[1]

515

1

T32

1

T52

4

T37

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2175

1

T32

4

T58

6

T52

9

auto[1]

277

1

T58

2

T37

3

T38

7

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2207

1

T32

3

T58

8

T52

9

auto[1]

245

1

T32

1

T37

21

T38

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T32

4

T58

6

T52

9

auto[1]

274

1

T58

2

T38

15

T89

20

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2108

1

T32

4

T58

6

T52

9

auto[1]

344

1

T58

2

T37

12

T38

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2268

1

T32

3

T58

8

T52

9

auto[1]

184

1

T32

1

T38

2

T88

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1916

1

T32

4

T58

8

T52

4

auto[1]

536

1

T52

5

T37

9

T53

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	713	1			T52	9		T53	1		T41	8
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	60	1			T397	6		T395	14		T413	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	28	1			T38	2		T414	5		T398	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	42	1			T284	2		T415	3		T395	10
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	118	1			T42	24		T39	6		T106	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	33	1			T39	3		T279	8		T414	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T39	2		T416	1		T156	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	13	1			T279	7		T414	3		T280	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	47	1			T39	3		T282	1		T284	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	32	1			T38	7		T414	6		T397	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	11	1			T283	2		T155	1		T404	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T417	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	46	1			T38	2		T398	1		T280	5
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	18	1			T40	2		T106	2		T418	2
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	9	1			T301	5		T419	2		T420	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	35	1			T37	4		T40	6		T415	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T37	2		T283	6		T421	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	18	1			T32	1		T281	7		T422	6
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T423	3		T424	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	51	1			T37	8		T283	22		T281	6
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	4	1			T423	3		T425	1		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	10	1			T89	1		T281	4		T423	5
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	46	1			T38	6		T89	20		T120	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	3	1			T40	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	2	1			T421	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T395	3		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	11	1			T106	5		T426	6		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T422	4		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

126

1

T37

4

T42

12

T109

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

133

1

T40

3

T137

10

T283

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

73

1

T52

5

T306

5

T283

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

91

1

T38

7

T89

10

T281

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

58

1

T52

4

T89

10

T39

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T37

4

T427

6

T418

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T53

1

T38

6

T292

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

117

1

T89

1

T285

10

T303

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

46

1

T37

4

T428

7

T305

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

48

1

T37

2

T279

8

T287

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T428

4

T429

1

T312

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T32

1

T41

8

T109

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T285

4

T292

2

T427

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T389

4

T427

3

T421

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T137

2

T397

7

T430

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

71

1

T42

12

T40

2

T283

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

89

1

T38

2

T293

3

T288

18

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T38

2

T39

3

T306

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T306

3

T284

3

T392

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T293

4

T389

6

T114

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T137

3

T388

4

T115

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

19

1

T112

2

T393

2

T249

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T388

1

T393

1

T114

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

105

1

T302

5

T39

6

T293

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T39

2

T431

3

T432

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T137

5

T391

3

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T392

1

T432

3

T251

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T304

1

T98

2

T433

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

15

1

T291

3

T121

2

T148

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T111

2

T289

2

T430

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T306

1

T429

1

T148

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded