Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_invert_ctl_cg	100.00	1	100	1	64	64
sysrst_ctrl_key_invert_ctl_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T17

13

T25

11

T26

10

auto[1]

624

1

T17

7

T25

9

T26

10

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634

1

T17

10

T25

8

T26

10

auto[1]

646

1

T17

10

T25

12

T26

10

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T17

9

T25

11

T26

12

auto[1]

631

1

T17

11

T25

9

T26

8

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T17

10

T25

12

T26

14

auto[1]

631

1

T17

10

T25

8

T26

6

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

656

1

T17

8

T25

9

T26

12

auto[1]

624

1

T17

12

T25

11

T26

8

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T17

10

T25

8

T26

7

auto[1]

647

1

T17

10

T25

12

T26

13

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T17

11

T25

8

T26

10

auto[1]

629

1

T17

9

T25

12

T26

10

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T17

8

T25

12

T26

12

auto[1]

618

1

T17

12

T25

8

T26

8

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

635

1

T17

8

T25

12

T26

7

auto[1]

645

1

T17

12

T25

8

T26

13

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653

1

T17

13

T25

12

T26

8

auto[1]

627

1

T17

7

T25

8

T26

12

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T17

11

T25

16

T26

5

auto[1]

633

1

T17

9

T25

4

T26

15

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T17

9

T25

11

T26

10

auto[1]

618

1

T17

11

T25

9

T26

10

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679

1

T17

9

T25

9

T26

7

auto[1]

601

1

T17

11

T25

11

T26

13

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

634

1

T17

10

T25

8

T26

10

auto[1]

646

1

T17

10

T25

12

T26

10

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T17

12

T25

7

T26

10

auto[1]

664

1

T17

8

T25

13

T26

10

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T17

11

T25

12

T26

10

auto[1]

632

1

T17

9

T25

8

T26

10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

657

1

T17

9

T25

12

T26

8

auto[1]

623

1

T17

11

T25

8

T26

12

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T17

13

T25

11

T26

11

auto[1]

682

1

T17

7

T25

9

T26

9

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

632

1

T17

10

T25

11

T26

12

auto[1]

648

1

T17

10

T25

9

T26

8

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T17

11

T25

5

T26

14

auto[1]

639

1

T17

9

T25

15

T26

6

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

597

1

T17

10

T25

13

T26

6

auto[1]

683

1

T17

10

T25

7

T26

14

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T17

9

T25

8

T26

9

auto[1]

676

1

T17

11

T25

12

T26

11

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

638

1

T17

11

T25

12

T26

10

auto[1]

642

1

T17

9

T25

8

T26

10

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

662

1

T17

9

T25

11

T26

10

auto[1]

618

1

T17

11

T25

9

T26

10

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

313

1

T17

8

T25

6

T26

7

auto[0]

auto[1]

303

1

T17

4

T25

1

T26

3

auto[1]

auto[0]

336

1

T17

1

T25

5

T26

5

auto[1]

auto[1]

328

1

T17

7

T25

8

T26

5

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

329

1

T17

8

T25

9

T26

8

auto[0]

auto[1]

319

1

T17

3

T25

3

T26

2

auto[1]

auto[0]

320

1

T17

2

T25

3

T26

6

auto[1]

auto[1]

312

1

T17

7

T25

5

T26

4

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

322

1

T17

4

T25

6

T26

7

auto[0]

auto[1]

335

1

T17

5

T25

6

T26

1

auto[1]

auto[0]

334

1

T17

4

T25

3

T26

5

auto[1]

auto[1]

289

1

T17

7

T25

5

T26

7

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

281

1

T17

7

T25

5

T26

6

auto[0]

auto[1]

317

1

T17

6

T25

6

T26

5

auto[1]

auto[0]

352

1

T17

3

T25

3

T26

1

auto[1]

auto[1]

330

1

T17

4

T25

6

T26

8

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

301

1

T17

5

T25

4

T26

5

auto[0]

auto[1]

331

1

T17

5

T25

7

T26

7

auto[1]

auto[0]

350

1

T17

6

T25

4

T26

5

auto[1]

auto[1]

298

1

T17

4

T25

5

T26

3

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

311

1

T17

4

T25

3

T26

7

auto[0]

auto[1]

330

1

T17

7

T25

2

T26

7

auto[1]

auto[0]

351

1

T17

4

T25

9

T26

5

auto[1]

auto[1]

288

1

T17

5

T25

6

T26

1

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

293

1

T17

6

T25

5

T26

3

auto[0]

auto[1]

311

1

T17

3

T25

3

T26

6

auto[1]

auto[0]

360

1

T17

7

T25

7

T26

5

auto[1]

auto[1]

316

1

T17

4

T25

5

T26

6

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

307

1

T17

6

T25

9

T26

2

auto[0]

auto[1]

331

1

T17

5

T25

3

T26

8

auto[1]

auto[0]

340

1

T17

5

T25

7

T26

3

auto[1]

auto[1]

302

1

T17

4

T25

1

T26

7

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

346

1

T17

7

T25

5

T26

4

auto[0]

auto[1]

333

1

T17

2

T25

4

T26

3

auto[1]

auto[0]

310

1

T17

6

T25

6

T26

6

auto[1]

auto[1]

291

1

T17

5

T25

5

T26

7

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

634

1

T17

10

T25

8

T26

10

auto[1]

auto[1]

646

1

T17

10

T25

12

T26

10

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

289

1

T17

4

T25

8

T26

3

auto[0]

auto[1]

308

1

T17

6

T25

5

T26

3

auto[1]

auto[0]

346

1

T17

4

T25

4

T26

4

auto[1]

auto[1]

337

1

T17

6

T25

3

T26

10

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

662

1

T17

9

T25

11

T26

10

auto[1]

auto[1]

618

1

T17

11

T25

9

T26

10

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T204	9
auto[1]	11	1			T204	11

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T204	8
auto[1]	12	1			T204	12

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T204	12
auto[1]	8	1			T204	8

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	7	1			T204	7
auto[1]	13	1			T204	13

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T204	9
auto[1]	11	1			T204	11

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	13	1			T204	13
auto[1]	7	1			T204	7

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T204	10
auto[1]	10	1			T204	10

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T204	11
auto[1]	9	1			T204	9

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	7	1			T204	7
auto[1]	13	1			T204	13

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T204	10
auto[1]	10	1			T204	10

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T204	12
auto[1]	8	1			T204	8

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T204	8
auto[1]	12	1			T204	12

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	6	1			T204	6
auto[1]	14	1			T204	14

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T204	8
auto[1]	12	1			T204	12

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T204	8
auto[1]	12	1			T204	12

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	9	1			T204	9
auto[1]	11	1			T204	11

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T204	11
auto[1]	9	1			T204	9

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	7	1			T204	7
auto[1]	13	1			T204	13

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T204	12
auto[1]	8	1			T204	8

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	11	1			T204	11
auto[1]	9	1			T204	9

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T204	12
auto[1]	8	1			T204	8

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	10	1			T204	10
auto[1]	10	1			T204	10

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	12	1			T204	12
auto[1]	8	1			T204	8

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	8	1			T204	8
auto[1]	12	1			T204	12

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in	cfg.vif.key0_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	5	1			T204	5
auto[0]	auto[1]	3	1			T204	3
auto[1]	auto[0]	7	1			T204	7
auto[1]	auto[1]	5	1			T204	5

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	3	1			T204	3
auto[0]	auto[1]	6	1			T204	6
auto[1]	auto[0]	4	1			T204	4
auto[1]	auto[1]	7	1			T204	7

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	5	1			T204	5
auto[0]	auto[1]	6	1			T204	6
auto[1]	auto[0]	4	1			T204	4
auto[1]	auto[1]	5	1			T204	5

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	5	1			T204	5
auto[0]	auto[1]	2	1			T204	2
auto[1]	auto[0]	8	1			T204	8
auto[1]	auto[1]	5	1			T204	5

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T204	8
auto[0]	auto[1]	4	1			T204	4
auto[1]	auto[0]	2	1			T204	2
auto[1]	auto[1]	6	1			T204	6

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T204	8
auto[0]	auto[1]	3	1			T204	3
auto[1]	auto[0]	3	1			T204	3
auto[1]	auto[1]	6	1			T204	6

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	4	1			T204	4
auto[0]	auto[1]	6	1			T204	6
auto[1]	auto[0]	6	1			T204	6
auto[1]	auto[1]	4	1			T204	4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	6	1			T204	6
auto[0]	auto[1]	6	1			T204	6
auto[1]	auto[0]	6	1			T204	6
auto[1]	auto[1]	2	1			T204	2

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	2	1			T204	2
auto[0]	auto[1]	4	1			T204	4
auto[1]	auto[0]	7	1			T204	7
auto[1]	auto[1]	7	1			T204	7

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T204	8
auto[1]	auto[1]	12	1			T204	12

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	6	1			T204	6
auto[0]	auto[1]	6	1			T204	6
auto[1]	auto[0]	1	1			T204	1
auto[1]	auto[1]	7	1			T204	7

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	STATUS		TEST	COUNT
auto[0]	auto[0]	8	1			T204	8
auto[1]	auto[1]	12	1			T204	12

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded