Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

707

1

T15

9

T80

11

T83

9

auto[1]

673

1

T15

11

T80

9

T83

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

331

1

T15

4

T80

5

T83

6

from_0to1

334

1

T15

4

T80

6

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T15

7

T80

6

T83

10

auto[1]

712

1

T15

13

T80

14

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

708

1

T15

9

T80

12

T83

12

auto[1]

672

1

T15

11

T80

8

T83

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T83

1

T207

2

T345

2

auto[0]

from_1to0

auto[0]

auto[1]

46

1

T83

2

T453

1

T278

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T80

3

T345

1

T454

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T15

2

T201

2

T278

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T84

3

T207

1

T201

3

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T15

1

T80

1

T83

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T80

2

T83

2

T181

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T15

1

T80

2

T207

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T15

1

T84

2

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T83

2

T84

1

T207

1

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T80

1

T83

1

T84

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T15

1

T80

1

T84

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T83

1

T207

1

T201

1

auto[1]

from_0to1

auto[0]

auto[1]

48

1

T15

1

T80

1

T84

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T15

1

T83

1

T207

2

auto[1]

from_0to1

auto[1]

auto[1]

37

1

T278

2

T343

2

T345

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

705

1

T15

10

T80

9

T83

10

auto[1]

675

1

T15

10

T80

11

T83

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

345

1

T15

5

T80

5

T83

8

from_0to1

338

1

T15

5

T80

5

T83

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T15

10

T80

9

T83

11

auto[1]

669

1

T15

10

T80

11

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T15

9

T80

10

T83

14

auto[1]

705

1

T15

11

T80

10

T83

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T80

1

T453

2

T343

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T84

2

T207

1

T453

1

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T80

1

T83

2

T84

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T83

1

T207

1

T201

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T15

1

T83

2

T84

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T15

1

T83

1

T84

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T15

1

T80

1

T83

2

auto[0]

from_0to1

auto[1]

auto[1]

40

1

T84

1

T453

1

T278

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T15

2

T80

1

T83

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T15

2

T83

2

T207

2

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T15

1

T453

1

T278

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T80

2

T83

2

T84

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T80

1

T83

2

T207

1

auto[1]

from_0to1

auto[0]

auto[1]

35

1

T80

1

T84

1

T201

1

auto[1]

from_0to1

auto[1]

auto[0]

43

1

T15

1

T80

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T15

1

T80

1

T84

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

683

1

T15

10

T80

13

T83

11

auto[1]

697

1

T15

10

T80

7

T83

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

323

1

T15

5

T80

3

T83

5

from_0to1

311

1

T15

5

T80

2

T83

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T15

11

T80

12

T83

12

auto[1]

694

1

T15

9

T80

8

T83

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T15

8

T80

11

T83

10

auto[1]

694

1

T15

12

T80

9

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T15

1

T80

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

37

1

T207

1

T343

1

T295

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T80

1

T84

2

T201

1

auto[0]

from_1to0

auto[1]

auto[1]

38

1

T15

2

T83

1

T207

1

auto[0]

from_0to1

auto[0]

auto[0]

43

1

T453

1

T295

1

T454

1

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T15

1

T83

2

T207

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T15

1

T83

1

T84

1

auto[0]

from_0to1

auto[1]

auto[1]

47

1

T80

1

T84

2

T201

1

auto[1]

from_1to0

auto[0]

auto[0]

47

1

T15

1

T83

2

T84

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T15

1

T83

1

T84

1

auto[1]

from_1to0

auto[1]

auto[0]

31

1

T84

1

T201

1

T453

1

auto[1]

from_1to0

auto[1]

auto[1]

47

1

T80

1

T207

1

T278

1

auto[1]

from_0to1

auto[0]

auto[0]

26

1

T84

1

T343

1

T295

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T15

1

T80

1

T84

1

auto[1]

from_0to1

auto[1]

auto[0]

42

1

T343

1

T345

2

T295

1

auto[1]

from_0to1

auto[1]

auto[1]

42

1

T15

2

T83

1

T207

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

701

1

T15

11

T80

12

T83

9

auto[1]

679

1

T15

9

T80

8

T83

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

309

1

T15

3

T80

3

T83

4

from_0to1

313

1

T15

3

T80

3

T83

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

692

1

T15

12

T80

12

T83

11

auto[1]

688

1

T15

8

T80

8

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710

1

T15

10

T80

11

T83

14

auto[1]

670

1

T15

10

T80

9

T83

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

31

1

T15

1

T80

1

T83

3

auto[0]

from_1to0

auto[0]

auto[1]

28

1

T84

2

T295

1

T146

1

auto[0]

from_1to0

auto[1]

auto[0]

36

1

T278

1

T454

1

T181

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T80

1

T207

2

T453

3

auto[0]

from_0to1

auto[0]

auto[0]

47

1

T80

1

T207

1

T201

2

auto[0]

from_0to1

auto[0]

auto[1]

36

1

T15

2

T207

1

T295

1

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T80

1

T83

1

T201

1

auto[0]

from_0to1

auto[1]

auto[1]

34

1

T83

1

T84

1

T207

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T80

1

T83

1

T278

1

auto[1]

from_1to0

auto[0]

auto[1]

37

1

T15

2

T84

2

T207

2

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T84

1

T278

1

T343

2

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T201

2

T453

1

T343

3

auto[1]

from_0to1

auto[0]

auto[0]

34

1

T15

1

T83

1

T278

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T80

1

T84

1

T453

1

auto[1]

from_0to1

auto[1]

auto[0]

37

1

T84

1

T453

1

T295

1

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T83

1

T84

3

T146

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675

1

T15

7

T80

12

T83

10

auto[1]

705

1

T15

13

T80

8

T83

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

325

1

T15

5

T80

5

T83

7

from_0to1

320

1

T15

6

T80

4

T83

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699

1

T15

10

T80

9

T83

11

auto[1]

681

1

T15

10

T80

11

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

715

1

T15

12

T80

15

T83

10

auto[1]

665

1

T15

8

T80

5

T83

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T80

2

T278

1

T345

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T15

1

T80

1

T207

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T84

2

T201

1

T278

1

auto[0]

from_1to0

auto[1]

auto[1]

35

1

T83

3

T207

1

T201

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T15

1

T80

1

T83

2

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T80

1

T201

1

T278

2

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T15

1

T80

2

T84

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T15

1

T83

1

T84

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T80

1

T84

2

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

44

1

T15

1

T83

3

T84

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T15

2

T80

1

T84

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T15

1

T83

1

T207

1

auto[1]

from_0to1

auto[0]

auto[0]

35

1

T83

2

T84

1

T207

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T83

1

T207

1

T201

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T15

1

T83

1

T201

2

auto[1]

from_0to1

auto[1]

auto[1]

39

1

T15

2

T84

2

T453

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

711

1

T15

9

T80

10

T83

11

auto[1]

669

1

T15

11

T80

10

T83

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

330

1

T15

4

T80

5

T83

6

from_0to1

328

1

T15

3

T80

5

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721

1

T15

12

T80

11

T83

10

auto[1]

659

1

T15

8

T80

9

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T15

8

T80

13

T83

11

auto[1]

671

1

T15

12

T80

7

T83

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T15

1

T80

2

T83

3

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T84

2

T201

2

T453

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T83

2

T207

1

T201

3

auto[0]

from_1to0

auto[1]

auto[1]

43

1

T201

1

T453

1

T278

1

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T80

1

T201

1

T453

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T80

1

T83

1

T201

2

auto[0]

from_0to1

auto[1]

auto[0]

32

1

T80

1

T83

1

T84

1

auto[0]

from_0to1

auto[1]

auto[1]

42

1

T84

1

T207

2

T201

2

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T15

1

T201

1

T146

1

auto[1]

from_1to0

auto[0]

auto[1]

38

1

T207

1

T278

1

T345

3

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T15

1

T80

3

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T15

1

T207

1

T278

1

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T80

1

T83

1

T207

1

auto[1]

from_0to1

auto[0]

auto[1]

40

1

T15

2

T207

1

T201

1

auto[1]

from_0to1

auto[1]

auto[0]

48

1

T83

1

T84

1

T201

1

auto[1]

from_0to1

auto[1]

auto[1]

34

1

T15

1

T80

1

T83

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T15

7

T80

9

T83

8

auto[1]

715

1

T15

13

T80

11

T83

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

318

1

T15

1

T80

4

T83

5

from_0to1

308

1

T15

2

T80

4

T83

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

725

1

T15

8

T80

13

T83

11

auto[1]

655

1

T15

12

T80

7

T83

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

709

1

T15

12

T80

10

T83

11

auto[1]

671

1

T15

8

T80

10

T83

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T207

2

T201

2

T453

1

auto[0]

from_1to0

auto[0]

auto[1]

43

1

T80

2

T207

1

T201

2

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T83

1

T84

1

T207

1

auto[0]

from_1to0

auto[1]

auto[1]

30

1

T84

1

T295

2

T215

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T80

1

T207

1

T278

1

auto[0]

from_0to1

auto[0]

auto[1]

45

1

T80

1

T83

2

T84

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T83

1

T343

2

T146

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T15

1

T84

2

T453

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T83

2

T84

3

T201

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T80

2

T207

1

T453

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T15

1

T83

1

T201

1

auto[1]

from_1to0

auto[1]

auto[1]

30

1

T83

1

T343

1

T215

1

auto[1]

from_0to1

auto[0]

auto[0]

49

1

T80

1

T84

2

T207

3

auto[1]

from_0to1

auto[0]

auto[1]

46

1

T15

1

T80

1

T83

2

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T201

1

T453

1

T345

1

auto[1]

from_0to1

auto[1]

auto[1]

26

1

T83

1

T207

1

T201

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

715

1

T15

14

T80

12

T83

10

auto[1]

665

1

T15

6

T80

8

T83

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

310

1

T15

5

T80

7

T83

4

from_0to1

322

1

T15

5

T80

6

T83

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712

1

T15

13

T80

10

T83

10

auto[1]

668

1

T15

7

T80

10

T83

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713

1

T15

9

T80

9

T83

5

auto[1]

667

1

T15

11

T80

11

T83

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T15

1

T80

1

T207

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T15

1

T80

2

T201

1

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T80

1

T83

2

T84

3

auto[0]

from_1to0

auto[1]

auto[1]

37

1

T15

1

T83

1

T295

1

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T15

3

T80

1

T453

3

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T80

1

T83

1

T207

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T80

3

T278

1

T345

3

auto[0]

from_0to1

auto[1]

auto[1]

24

1

T84

1

T453

1

T278

1

auto[1]

from_1to0

auto[0]

auto[0]

34

1

T207

1

T201

1

T453

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T15

1

T80

2

T83

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T15

1

T278

1

T343

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T80

1

T84

1

T207

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T15

1

T83

1

T84

1

auto[1]

from_0to1

auto[0]

auto[1]

37

1

T15

1

T83

2

T207

1

auto[1]

from_0to1

auto[1]

auto[0]

41

1

T201

1

T453

1

T343

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T80

1

T83

1

T84

2