Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144685	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

113811

1

T1

5

T4

6

T2

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136572	1			T1	4		T4	18		T2	10
values[0x0]	60383	1			T1	5		T4	1		T2	5
values[0x1]	61541	1			T1	2		T2	1		T12	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116461	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

142035

1

T1

5

T4

9

T2

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	763	1			T15	1		T5	3		T329	3
valid_sources[0x01]	805	1			T81	2		T10	4		T314	1
valid_sources[0x02]	850	1			T12	7		T3	1		T81	1
valid_sources[0x03]	963	1			T15	1		T85	1		T207	1
valid_sources[0x04]	942	1			T54	1		T329	1		T32	6
valid_sources[0x05]	799	1			T15	1		T329	1		T47	2
valid_sources[0x06]	1723	1			T18	32		T453	1		T76	1
valid_sources[0x07]	842	1			T15	1		T444	1		T208	1
valid_sources[0x08]	887	1			T81	1		T65	1		T54	1
valid_sources[0x09]	666	1			T25	1		T73	1		T329	1
valid_sources[0x0a]	966	1			T54	1		T91	30		T329	1
valid_sources[0x0b]	767	1			T329	1		T208	2		T307	1
valid_sources[0x0c]	907	1			T58	4		T75	2		T334	2
valid_sources[0x0d]	880	1			T17	1		T3	2		T81	1
valid_sources[0x0e]	861	1			T15	1		T17	1		T81	1
valid_sources[0x0f]	927	1			T81	2		T85	2		T49	6
valid_sources[0x10]	840	1			T80	1		T82	2		T329	1
valid_sources[0x11]	785	1			T14	5		T15	2		T81	2
valid_sources[0x12]	787	1			T15	1		T17	1		T329	1
valid_sources[0x13]	789	1			T17	1		T3	1		T54	1
valid_sources[0x14]	927	1			T17	1		T82	3		T90	10
valid_sources[0x15]	824	1			T15	1		T73	1		T85	3
valid_sources[0x16]	895	1			T17	2		T80	1		T444	1
valid_sources[0x17]	990	1			T17	1		T23	3		T25	1
valid_sources[0x18]	898	1			T12	2		T15	1		T80	1
valid_sources[0x19]	695	1			T80	1		T54	1		T329	1
valid_sources[0x1a]	1313	1			T15	1		T81	1		T329	5
valid_sources[0x1b]	1112	1			T15	1		T17	1		T62	1
valid_sources[0x1c]	998	1			T85	1		T307	3		T59	1
valid_sources[0x1d]	1651	1			T54	1		T84	122		T329	3
valid_sources[0x1e]	957	1			T4	1		T15	1		T3	2
valid_sources[0x1f]	764	1			T80	2		T201	3		T307	1
valid_sources[0x20]	671	1			T16	1		T82	2		T444	1
valid_sources[0x21]	2039	1			T4	1		T86	1		T207	1
valid_sources[0x22]	837	1			T25	1		T58	1		T334	1
valid_sources[0x23]	887	1			T15	2		T25	2		T81	2
valid_sources[0x24]	838	1			T17	1		T82	1		T329	2
valid_sources[0x25]	691	1			T15	2		T81	1		T207	1
valid_sources[0x26]	1033	1			T16	1		T314	1		T329	1
valid_sources[0x27]	1297	1			T15	1		T16	2		T81	1
valid_sources[0x28]	812	1			T15	1		T329	1		T208	1
valid_sources[0x29]	865	1			T16	1		T329	1		T207	1
valid_sources[0x2a]	806	1			T207	1		T208	1		T197	1
valid_sources[0x2b]	906	1			T25	1		T58	2		T52	2
valid_sources[0x2c]	861	1			T80	1		T7	1		T90	4
valid_sources[0x2d]	2197	1			T80	1		T55	1		T329	1
valid_sources[0x2e]	847	1			T329	1		T85	4		T207	1
valid_sources[0x2f]	966	1			T17	1		T329	1		T85	1
valid_sources[0x30]	900	1			T25	1		T207	1		T197	1
valid_sources[0x31]	825	1			T15	1		T16	1		T3	2
valid_sources[0x32]	2057	1			T15	4		T81	1		T56	1
valid_sources[0x33]	718	1			T4	1		T15	2		T329	1
valid_sources[0x34]	876	1			T15	2		T80	1		T85	1
valid_sources[0x35]	835	1			T3	2		T25	1		T6	11
valid_sources[0x36]	1392	1			T3	1		T329	1		T85	5
valid_sources[0x37]	964	1			T12	12		T15	1		T3	1
valid_sources[0x38]	844	1			T5	4		T80	1		T81	3
valid_sources[0x39]	907	1			T27	3		T80	2		T81	1
valid_sources[0x3a]	759	1			T69	3		T80	1		T85	5
valid_sources[0x3b]	934	1			T17	1		T25	1		T90	5
valid_sources[0x3c]	783	1			T80	2		T85	5		T201	1
valid_sources[0x3d]	1456	1			T15	1		T329	1		T207	1
valid_sources[0x3e]	909	1			T15	1		T16	1		T65	1
valid_sources[0x3f]	1330	1			T2	3		T81	1		T314	1
valid_sources[0x40]	1115	1			T3	1		T25	1		T314	1
valid_sources[0x41]	977	1			T15	1		T80	2		T9	2
valid_sources[0x42]	814	1			T15	1		T3	1		T25	1
valid_sources[0x43]	786	1			T15	1		T81	2		T314	1
valid_sources[0x44]	1255	1			T4	1		T25	1		T329	3
valid_sources[0x45]	1802	1			T80	1		T11	3		T85	1
valid_sources[0x46]	832	1			T81	1		T86	1		T32	16
valid_sources[0x47]	764	1			T15	1		T3	1		T62	1
valid_sources[0x48]	813	1			T1	11		T15	2		T17	1
valid_sources[0x49]	815	1			T15	1		T3	1		T25	1
valid_sources[0x4a]	820	1			T15	1		T17	1		T82	1
valid_sources[0x4b]	763	1			T25	2		T81	1		T82	3
valid_sources[0x4c]	965	1			T3	1		T81	2		T85	1
valid_sources[0x4d]	1189	1			T62	1		T90	1		T54	1
valid_sources[0x4e]	901	1			T15	2		T3	1		T81	1
valid_sources[0x4f]	867	1			T65	1		T329	4		T197	1
valid_sources[0x50]	1449	1			T3	2		T73	14		T207	1
valid_sources[0x51]	717	1			T80	2		T197	1		T307	1
valid_sources[0x52]	988	1			T15	1		T3	1		T80	1
valid_sources[0x53]	954	1			T73	1		T197	2		T201	1
valid_sources[0x54]	977	1			T15	2		T81	2		T64	22
valid_sources[0x55]	1082	1			T15	1		T23	1		T170	1
valid_sources[0x56]	855	1			T82	3		T30	11		T329	2
valid_sources[0x57]	1040	1			T14	7		T16	1		T56	2
valid_sources[0x58]	837	1			T15	2		T329	1		T86	1
valid_sources[0x59]	909	1			T15	1		T80	1		T329	1
valid_sources[0x5a]	954	1			T329	1		T307	1		T58	3
valid_sources[0x5b]	942	1			T15	2		T81	1		T82	1
valid_sources[0x5c]	911	1			T15	1		T81	1		T55	2
valid_sources[0x5d]	799	1			T15	1		T80	2		T81	1
valid_sources[0x5e]	970	1			T80	2		T82	1		T73	1
valid_sources[0x5f]	1051	1			T80	3		T81	1		T329	3
valid_sources[0x60]	918	1			T81	1		T329	1		T85	3
valid_sources[0x61]	1305	1			T15	1		T32	19		T58	5
valid_sources[0x62]	2343	1			T11	1		T329	1		T32	6
valid_sources[0x63]	1198	1			T2	1		T15	1		T81	1
valid_sources[0x64]	782	1			T81	1		T329	2		T32	6
valid_sources[0x65]	1067	1			T25	2		T80	2		T207	1
valid_sources[0x66]	719	1			T329	1		T207	2		T32	4
valid_sources[0x67]	1648	1			T54	1		T11	1		T329	2
valid_sources[0x68]	826	1			T329	1		T47	1		T207	2
valid_sources[0x69]	807	1			T17	2		T25	1		T56	1
valid_sources[0x6a]	734	1			T90	5		T314	1		T329	1
valid_sources[0x6b]	832	1			T17	1		T25	1		T80	2
valid_sources[0x6c]	840	1			T4	1		T329	1		T86	1
valid_sources[0x6d]	832	1			T4	1		T80	1		T81	1
valid_sources[0x6e]	747	1			T64	20		T54	1		T55	1
valid_sources[0x6f]	987	1			T4	2		T17	1		T3	1
valid_sources[0x70]	969	1			T4	2		T81	1		T329	1
valid_sources[0x71]	820	1			T27	10		T80	1		T81	1
valid_sources[0x72]	1159	1			T15	1		T90	2		T86	1
valid_sources[0x73]	725	1			T15	2		T25	1		T80	1
valid_sources[0x74]	852	1			T81	1		T90	3		T329	1
valid_sources[0x75]	831	1			T3	2		T90	24		T329	1
valid_sources[0x76]	746	1			T27	3		T329	2		T85	6
valid_sources[0x77]	1052	1			T63	5		T80	1		T314	1
valid_sources[0x78]	1201	1			T80	1		T81	1		T64	24
valid_sources[0x79]	851	1			T4	1		T15	1		T17	1
valid_sources[0x7a]	950	1			T17	2		T334	1		T52	3
valid_sources[0x7b]	933	1			T81	1		T87	1		T201	2
valid_sources[0x7c]	817	1			T15	1		T80	1		T81	1
valid_sources[0x7d]	913	1			T15	1		T23	1		T25	1
valid_sources[0x7e]	979	1			T3	1		T90	25		T329	1
valid_sources[0x7f]	971	1			T90	12		T314	1		T329	1
valid_sources[0x80]	2691	1			T80	1		T329	3		T86	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61637

1

T1

3

T4

6

T2

4

values[0x0]

all_enables

biggest_size

30093

1

T1

2

T2

3

T12

8

values[0x1]

all_enables

biggest_size

22081

1

T12

6

T14

3

T15

6