Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1004924884	12575	0	0
auto_block_debounce_ctl_rd_A	1004924884	1468	0	0
auto_block_out_ctl_rd_A	1004924884	2272	0	0
com_det_ctl_0_rd_A	1004924884	3332	0	0
com_det_ctl_1_rd_A	1004924884	3618	0	0
com_det_ctl_2_rd_A	1004924884	3481	0	0
com_det_ctl_3_rd_A	1004924884	3705	0	0
com_out_ctl_0_rd_A	1004924884	4035	0	0
com_out_ctl_1_rd_A	1004924884	4216	0	0
com_out_ctl_2_rd_A	1004924884	3882	0	0
com_out_ctl_3_rd_A	1004924884	4228	0	0
com_pre_det_ctl_0_rd_A	1004924884	1257	0	0
com_pre_det_ctl_1_rd_A	1004924884	1312	0	0
com_pre_det_ctl_2_rd_A	1004924884	1289	0	0
com_pre_det_ctl_3_rd_A	1004924884	1375	0	0
com_pre_sel_ctl_0_rd_A	1004924884	4440	0	0
com_pre_sel_ctl_1_rd_A	1004924884	4527	0	0
com_pre_sel_ctl_2_rd_A	1004924884	4189	0	0
com_pre_sel_ctl_3_rd_A	1004924884	4228	0	0
com_sel_ctl_0_rd_A	1004924884	4369	0	0
com_sel_ctl_1_rd_A	1004924884	4256	0	0
com_sel_ctl_2_rd_A	1004924884	4367	0	0
com_sel_ctl_3_rd_A	1004924884	4295	0	0
ec_rst_ctl_rd_A	1004924884	2174	0	0
intr_enable_rd_A	1004924884	1644	0	0
key_intr_ctl_rd_A	1004924884	3942	0	0
key_intr_debounce_ctl_rd_A	1004924884	1238	0	0
key_invert_ctl_rd_A	1004924884	5131	0	0
pin_allowed_ctl_rd_A	1004924884	5089	0	0
pin_out_ctl_rd_A	1004924884	3583	0	0
pin_out_value_rd_A	1004924884	3886	0	0
regwen_rd_A	1004924884	1432	0	0
ulp_ac_debounce_ctl_rd_A	1004924884	1451	0	0
ulp_ctl_rd_A	1004924884	1374	0	0
ulp_lid_debounce_ctl_rd_A	1004924884	1323	0	0
ulp_pwrb_debounce_ctl_rd_A	1004924884	1317	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	12575	0	0
T9	59046	0	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T64	430906	7	0	0
T65	259395	0	0	0
T68	0	16	0	0
T73	239840	0	0	0
T84	13999	0	0	0
T85	0	1	0	0
T90	284485	7	0	0
T91	41328	0	0	0
T130	0	3	0	0
T220	0	7	0	0
T226	0	12	0	0
T329	0	4	0	0
T334	0	4	0	0
T335	0	3	0	0
T336	202368	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1468	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	20	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	121687	0	0	0
T28	0	2	0	0
T29	59042	0	0	0
T60	0	16	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T85	0	10	0	0
T130	0	12	0	0
T180	0	14	0	0
T329	0	23	0	0
T334	0	23	0	0
T337	0	43	0	0
T338	0	17	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	2272	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	11	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	121687	0	0	0
T28	0	20	0	0
T29	59042	0	0	0
T60	0	10	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T85	0	21	0	0
T130	0	21	0	0
T180	0	9	0	0
T329	0	36	0	0
T334	0	6	0	0
T337	0	49	0	0
T338	0	14	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3332	0	0
T31	983901	0	0	0
T41	0	75	0	0
T47	276667	0	0	0
T53	0	52	0	0
T58	0	25	0	0
T74	37301	0	0	0
T85	188932	19	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	15	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	66	0	0
T292	0	78	0	0
T302	0	37	0	0
T329	406326	25	0	0
T337	0	29	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3618	0	0
T31	983901	0	0	0
T41	0	64	0	0
T47	276667	0	0	0
T53	0	70	0	0
T58	0	38	0	0
T74	37301	0	0	0
T85	188932	26	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	17	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	63	0	0
T302	0	40	0	0
T329	406326	20	0	0
T334	0	4	0	0
T337	0	44	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3481	0	0
T31	983901	0	0	0
T41	0	75	0	0
T47	276667	0	0	0
T53	0	96	0	0
T58	0	50	0	0
T74	37301	0	0	0
T85	188932	16	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	14	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	78	0	0
T302	0	48	0	0
T329	406326	28	0	0
T334	0	12	0	0
T337	0	35	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3705	0	0
T31	983901	0	0	0
T41	0	66	0	0
T47	276667	0	0	0
T53	0	55	0	0
T58	0	44	0	0
T74	37301	0	0	0
T85	188932	10	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	25	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	69	0	0
T302	0	38	0	0
T329	406326	11	0	0
T334	0	6	0	0
T337	0	43	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4035	0	0
T31	983901	0	0	0
T41	0	76	0	0
T47	276667	0	0	0
T53	0	89	0	0
T58	0	49	0	0
T74	37301	0	0	0
T85	188932	13	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	5	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	60	0	0
T302	0	32	0	0
T329	406326	18	0	0
T334	0	8	0	0
T337	0	45	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4216	0	0
T31	983901	0	0	0
T41	0	71	0	0
T47	276667	0	0	0
T53	0	67	0	0
T58	0	45	0	0
T74	37301	0	0	0
T85	188932	24	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	35	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	53	0	0
T302	0	73	0	0
T329	406326	27	0	0
T334	0	7	0	0
T337	0	36	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3882	0	0
T31	983901	0	0	0
T41	0	51	0	0
T47	276667	0	0	0
T53	0	67	0	0
T58	0	29	0	0
T74	37301	0	0	0
T85	188932	31	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	19	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	76	0	0
T302	0	26	0	0
T329	406326	24	0	0
T334	0	7	0	0
T337	0	42	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4228	0	0
T31	983901	0	0	0
T41	0	60	0	0
T47	276667	0	0	0
T53	0	50	0	0
T58	0	43	0	0
T74	37301	0	0	0
T85	188932	19	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	14	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	84	0	0
T302	0	46	0	0
T329	406326	13	0	0
T334	0	12	0	0
T337	0	42	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1257	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	26	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	7	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	41	0	0
T329	406326	20	0	0
T334	0	15	0	0
T337	0	26	0	0
T339	0	14	0	0
T340	0	26	0	0
T341	0	14	0	0
T342	0	9	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1312	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	15	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	25	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	31	0	0
T329	406326	9	0	0
T334	0	3	0	0
T337	0	32	0	0
T339	0	23	0	0
T340	0	24	0	0
T341	0	21	0	0
T342	0	21	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1289	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	5	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	21	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	28	0	0
T329	406326	18	0	0
T334	0	7	0	0
T337	0	42	0	0
T339	0	28	0	0
T340	0	35	0	0
T341	0	11	0	0
T342	0	41	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1375	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	14	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	17	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	43	0	0
T329	406326	23	0	0
T334	0	12	0	0
T337	0	47	0	0
T339	0	29	0	0
T340	0	41	0	0
T341	0	8	0	0
T342	0	22	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4440	0	0
T31	983901	0	0	0
T41	0	78	0	0
T47	276667	0	0	0
T53	0	45	0	0
T58	0	40	0	0
T74	37301	0	0	0
T85	188932	30	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	20	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	67	0	0
T302	0	23	0	0
T329	406326	10	0	0
T334	0	8	0	0
T337	0	45	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4527	0	0
T31	983901	0	0	0
T41	0	97	0	0
T47	276667	0	0	0
T53	0	60	0	0
T58	0	40	0	0
T74	37301	0	0	0
T85	188932	19	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	18	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	86	0	0
T302	0	32	0	0
T329	406326	16	0	0
T334	0	15	0	0
T337	0	21	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4189	0	0
T31	983901	0	0	0
T41	0	76	0	0
T47	276667	0	0	0
T53	0	54	0	0
T58	0	45	0	0
T74	37301	0	0	0
T85	188932	21	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	19	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	89	0	0
T302	0	33	0	0
T329	406326	24	0	0
T334	0	9	0	0
T337	0	35	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4228	0	0
T31	983901	0	0	0
T41	0	50	0	0
T47	276667	0	0	0
T53	0	69	0	0
T58	0	49	0	0
T74	37301	0	0	0
T85	188932	15	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	17	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	79	0	0
T302	0	44	0	0
T329	406326	21	0	0
T334	0	14	0	0
T337	0	39	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4369	0	0
T31	983901	0	0	0
T41	0	58	0	0
T47	276667	0	0	0
T53	0	70	0	0
T58	0	35	0	0
T74	37301	0	0	0
T85	188932	22	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	19	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	66	0	0
T302	0	55	0	0
T329	406326	10	0	0
T334	0	6	0	0
T337	0	43	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4256	0	0
T31	983901	0	0	0
T41	0	74	0	0
T47	276667	0	0	0
T53	0	72	0	0
T58	0	31	0	0
T74	37301	0	0	0
T85	188932	24	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	18	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	70	0	0
T302	0	43	0	0
T329	406326	29	0	0
T334	0	23	0	0
T337	0	34	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4367	0	0
T31	983901	0	0	0
T41	0	65	0	0
T47	276667	0	0	0
T53	0	81	0	0
T58	0	43	0	0
T74	37301	0	0	0
T85	188932	15	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	25	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	82	0	0
T302	0	50	0	0
T329	406326	10	0	0
T334	0	22	0	0
T337	0	29	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4295	0	0
T31	983901	0	0	0
T41	0	88	0	0
T47	276667	0	0	0
T53	0	85	0	0
T58	0	39	0	0
T74	37301	0	0	0
T85	188932	15	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	22	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T285	0	65	0	0
T302	0	54	0	0
T329	406326	17	0	0
T334	0	16	0	0
T337	0	23	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	2174	0	0
T31	983901	0	0	0
T41	0	24	0	0
T47	276667	0	0	0
T53	0	5	0	0
T58	0	7	0	0
T74	37301	0	0	0
T85	188932	24	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	20	0	0
T141	0	7	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T236	0	2	0	0
T329	406326	22	0	0
T334	0	8	0	0
T343	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1644	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	19	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T124	0	7	0	0
T130	0	24	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T233	0	7	0	0
T242	0	27	0	0
T329	406326	11	0	0
T334	0	14	0	0
T337	0	36	0	0
T339	0	14	0	0
T340	0	41	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3942	0	0
T5	47208	3	0	0
T6	62486	0	0	0
T25	121687	0	0	0
T27	128256	0	0	0
T29	59042	0	0	0
T44	0	2	0	0
T46	0	3	0	0
T49	0	1	0	0
T50	0	4	0	0
T69	95170	0	0	0
T70	214377	0	0	0
T80	243298	0	0	0
T81	347457	0	0	0
T85	0	11	0	0
T130	0	8	0	0
T170	99037	0	0	0
T329	0	18	0	0
T334	0	19	0	0
T337	0	34	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1238	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	21	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	35	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	44	0	0
T329	406326	13	0	0
T334	0	1	0	0
T337	0	54	0	0
T339	0	21	0	0
T340	0	14	0	0
T341	0	29	0	0
T342	0	32	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	5131	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T78	0	67	0	0
T79	0	62	0	0
T85	188932	20	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	10	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T209	0	74	0	0
T214	0	23	0	0
T329	406326	21	0	0
T334	0	13	0	0
T337	0	38	0	0
T344	0	27	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	5089	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T15	251146	38	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T29	59042	0	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T84	0	65	0	0
T85	0	19	0	0
T130	0	11	0	0
T146	0	68	0	0
T201	0	82	0	0
T329	0	21	0	0
T334	0	14	0	0
T343	0	72	0	0
T345	0	78	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3583	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T15	251146	26	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T29	59042	0	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T84	0	84	0	0
T85	0	23	0	0
T130	0	18	0	0
T146	0	62	0	0
T201	0	75	0	0
T329	0	20	0	0
T334	0	19	0	0
T343	0	61	0	0
T345	0	67	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	3886	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T15	251146	34	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T29	59042	0	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T84	0	77	0	0
T85	0	23	0	0
T130	0	8	0	0
T146	0	79	0	0
T201	0	56	0	0
T329	0	13	0	0
T334	0	11	0	0
T343	0	78	0	0
T345	0	76	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1432	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	27	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T130	0	16	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T242	0	58	0	0
T329	406326	17	0	0
T334	0	16	0	0
T337	0	26	0	0
T339	0	18	0	0
T340	0	45	0	0
T341	0	28	0	0
T342	0	22	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1451	0	0
T10	222413	1	0	0
T11	108918	0	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T56	308848	0	0	0
T74	37301	0	0	0
T85	188932	28	0	0
T93	0	10	0	0
T130	0	26	0	0
T147	0	11	0	0
T296	0	10	0	0
T314	201069	0	0	0
T329	406326	11	0	0
T334	0	14	0	0
T337	0	32	0	0
T346	0	4	0	0
T347	47035	0	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1374	0	0
T10	222413	5	0	0
T11	108918	0	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T56	308848	0	0	0
T74	37301	0	0	0
T85	188932	23	0	0
T93	0	8	0	0
T130	0	27	0	0
T147	0	17	0	0
T296	0	1	0	0
T314	201069	0	0	0
T329	406326	21	0	0
T334	0	3	0	0
T337	0	25	0	0
T346	0	1	0	0
T347	47035	0	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1323	0	0
T10	222413	2	0	0
T11	108918	0	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T56	308848	0	0	0
T74	37301	0	0	0
T85	188932	22	0	0
T93	0	16	0	0
T130	0	9	0	0
T135	0	6	0	0
T147	0	9	0	0
T296	0	3	0	0
T314	201069	0	0	0
T329	406326	12	0	0
T334	0	15	0	0
T337	0	46	0	0
T347	47035	0	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1317	0	0
T31	983901	0	0	0
T47	276667	0	0	0
T74	37301	0	0	0
T85	188932	16	0	0
T86	250594	0	0	0
T87	53434	0	0	0
T93	0	11	0	0
T130	0	23	0	0
T135	0	9	0	0
T205	100943	0	0	0
T206	216217	0	0	0
T207	120893	0	0	0
T296	0	2	0	0
T329	406326	22	0	0
T334	0	5	0	0
T337	0	22	0	0
T339	0	8	0	0
T346	0	4	0	0