Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.70	96.99	88.57			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.39	95.92	86.96			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T14 T18 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T14 T18 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T14 T18 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T14 T18 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T14 T18 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T14 T18 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T14 T18 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T12,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T12,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T3,T24,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T3,T24,T10
1	1	Covered	T3,T24,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T24,T10
1	-	Covered	T3,T24,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T24,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T24,T10
1	1	Covered	T3,T24,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T18
0	0	1	Covered	T1,T14,T18
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T18
0	0	1	Covered	T1,T14,T18
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	98834674	0	0
DstReqKnown_A	211395816	188935620	0	0
SrcAckBusyChk_A	2147483647	105270	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	98834674	0	0
T1	60473	488	0	0
T2	71662	0	0	0
T3	41382	0	0	0
T4	102900	0	0	0
T5	94416	0	0	0
T6	0	511	0	0
T7	0	1423	0	0
T8	55420	0	0	0
T9	0	335	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1929	0	0
T15	251146	0	0	0
T16	537750	7434	0	0
T17	707376	0	0	0
T18	612399	0	0	0
T23	674424	0	0	0
T24	442869	3995	0	0
T25	243374	0	0	0
T28	0	9616	0	0
T29	118084	339	0	0
T30	0	512	0	0
T31	0	8741	0	0
T32	0	344	0	0
T52	0	2463	0	0
T54	0	10632	0	0
T55	0	422	0	0
T56	0	10986	0	0
T57	0	3865	0	0
T58	0	283	0	0
T59	0	12467	0	0
T60	0	6034	0	0
T61	0	851	0	0
T62	193788	0	0	0
T63	159556	0	0	0
T64	430906	0	0	0
T65	259395	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211395816	188935620	0	0
T1	16422	2822	0	0
T2	23154	9554	0	0
T4	14280	680	0	0
T12	17918	4318	0	0
T13	14348	748	0	0
T14	15368	1768	0	0
T15	17068	3468	0	0
T16	24344	10744	0	0
T17	16694	3094	0	0
T18	60724	47124	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	105270	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T3	41382	0	0	0
T4	102900	0	0	0
T5	94416	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	55420	0	0	0
T9	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	537750	9	0	0
T17	707376	0	0	0
T18	612399	0	0	0
T23	674424	0	0	0
T24	442869	21	0	0
T25	243374	0	0	0
T28	0	6	0	0
T29	118084	1	0	0
T30	0	1	0	0
T31	0	21	0	0
T32	0	1	0	0
T52	0	6	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	7	0	0
T57	0	7	0	0
T58	0	1	0	0
T59	0	8	0	0
T60	0	7	0	0
T61	0	8	0	0
T62	193788	0	0	0
T63	159556	0	0	0
T64	430906	0	0	0
T65	259395	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2056082	2054382	0	0
T2	2436508	2434570	0	0
T4	3498600	3495370	0	0
T12	2241144	2239444	0	0
T13	7037728	7035858	0	0
T14	7456472	7453684	0	0
T15	8538964	8536448	0	0
T16	6094500	6091950	0	0
T17	8016928	8013766	0	0
T18	6940522	6937598	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T3 T10 T11 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T3 T10 T11 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T3 T10 T11 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T3 T10 T11 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T3 T10 T11 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T2 T3 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T3 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T31,T34,T35
1	-	Covered	T3,T10,T11

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T10,T11

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T3,T10,T11
0	0	1	Covered	T3,T10,T11
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T3,T10,T11
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	920801	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1065	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	920801	0	0
T3	20691	306	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1936	0	0
T11	0	689	0	0
T25	121687	0	0	0
T27	128256	0	0	0
T29	59042	0	0	0
T31	0	475	0	0
T32	0	357	0	0
T37	0	1310	0	0
T53	0	1960	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	353	0	0
T67	0	113	0	0
T68	0	352	0	0
T69	95170	0	0	0
T70	214377	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1065	0	0
T3	20691	2	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	121687	0	0	0
T27	128256	0	0	0
T29	59042	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	0	3	0	0
T53	0	1	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	95170	0	0	0
T70	214377	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T14 T23 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T14 T23 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T14 T23 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T14 T23 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T14 T23 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T14 T23 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T14 T23 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T23

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T14,T23
1	1	Covered	T1,T14,T23

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T23

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T23
1	1	Covered	T1,T14,T23

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T23
0	0	1	Covered	T1,T14,T23
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T23
0	0	1	Covered	T1,T14,T23
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1711393	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1883	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1711393	0	0
T1	60473	454	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	492	0	0
T7	0	1411	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1925	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	0	1403	0	0
T24	0	260	0	0
T29	0	331	0	0
T30	0	508	0	0
T63	0	438	0	0
T65	0	1434	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1883	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	0	1	0	0
T24	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T18 T3 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T18 T3 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T18 T3 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T18 T3 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T18 T3 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T18 T3 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T18 T3 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1063745	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1101	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1063745	0	0
T3	20691	432	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1969	0	0
T11	0	696	0	0
T18	204133	4783	0	0
T23	337212	0	0	0
T24	0	260	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	481	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	357	0	0
T67	0	117	0	0
T69	95170	0	0	0
T71	0	3995	0	0
T72	0	706	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1101	0	0
T3	20691	3	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	204133	3	0	0
T23	337212	0	0	0
T24	0	1	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	1	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	95170	0	0	0
T71	0	2	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T18 T3 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T18 T3 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T18 T3 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T18 T3 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T18 T3 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T18 T3 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T18 T3 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1095776	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1121	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1095776	0	0
T3	20691	426	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1962	0	0
T11	0	684	0	0
T18	204133	4761	0	0
T23	337212	0	0	0
T24	0	252	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	479	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	355	0	0
T67	0	115	0	0
T69	95170	0	0	0
T71	0	3991	0	0
T72	0	686	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1121	0	0
T3	20691	3	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	204133	3	0	0
T23	337212	0	0	0
T24	0	1	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	1	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	95170	0	0	0
T71	0	2	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T18 T3 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T18 T3 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T18 T3 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T18 T3 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T18 T3 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T18 T3 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T18 T3 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T3,T24
1	1	Covered	T18,T3,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T18,T3,T24
0	0	1	Covered	T18,T3,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1030134	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1079	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1030134	0	0
T3	20691	420	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1943	0	0
T11	0	674	0	0
T18	204133	4749	0	0
T23	337212	0	0	0
T24	0	244	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	477	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	353	0	0
T67	0	113	0	0
T69	95170	0	0	0
T71	0	3987	0	0
T72	0	677	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1079	0	0
T3	20691	3	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T18	204133	3	0	0
T23	337212	0	0	0
T24	0	1	0	0
T25	121687	0	0	0
T29	59042	0	0	0
T31	0	1	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	1	0	0
T67	0	1	0	0
T69	95170	0	0	0
T71	0	2	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T17 T25 T26 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T17 T25 T26 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T17 T25 T26 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T17 T25 T26 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T17 T25 T26 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T17 T25 T26 
135        1/1                txn_bits_q <= '0;
           Tests:       T17 T25 T26 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T17,T25,T26

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T17,T25,T26
1	1	Covered	T17,T25,T26

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T17,T25,T26

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T25,T26
1	1	Covered	T17,T25,T26

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T17,T25,T26
0	0	1	Covered	T17,T25,T26
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T17,T25,T26
0	0	1	Covered	T17,T25,T26
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	2227771	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	2266	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	2227771	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T17	235792	33120	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	121687	18069	0	0
T26	0	17475	0	0
T29	59042	0	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T69	95170	0	0	0
T73	0	34818	0	0
T74	0	5081	0	0
T75	0	35503	0	0
T76	0	34927	0	0
T77	0	8281	0	0
T78	0	32042	0	0
T79	0	2359	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	2266	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T17	235792	20	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	121687	20	0	0
T26	0	20	0	0
T29	59042	0	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T69	95170	0	0	0
T73	0	20	0	0
T74	0	20	0	0
T75	0	20	0	0
T76	0	20	0	0
T77	0	20	0	0
T78	0	20	0	0
T79	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T12 T15 T17 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T12 T15 T17 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T12 T15 T17 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T12 T15 T17 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T12 T15 T17 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T12 T15 T17 
135        1/1                txn_bits_q <= '0;
           Tests:       T12 T15 T17 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T12,T15,T17

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T12,T15,T17
1	1	Covered	T12,T15,T17

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T12,T15,T17

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T15,T17
1	1	Covered	T12,T15,T17

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T12,T15,T17
0	0	1	Covered	T12,T15,T17
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T12,T15,T17
0	0	1	Covered	T12,T15,T17
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	4114420	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	4309	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4114420	0	0
T3	20691	0	0	0
T12	65916	7737	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	36555	0	0
T16	179250	0	0	0
T17	235792	1915	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	0	968	0	0
T26	0	744	0	0
T27	0	16427	0	0
T62	96894	0	0	0
T80	0	33588	0	0
T81	0	31621	0	0
T82	0	7333	0	0
T83	0	17040	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4309	0	0
T3	20691	0	0	0
T12	65916	20	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	20	0	0
T16	179250	0	0	0
T17	235792	1	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	20	0	0
T62	96894	0	0	0
T80	0	20	0	0
T81	0	40	0	0
T82	0	20	0	0
T83	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T12 T14 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T12 T14 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T12 T14 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T12 T14 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T12 T14 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T12 T14 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T12 T14 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T12,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T12,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T12,T14
0	0	1	Covered	T1,T12,T14
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T12,T14
0	0	1	Covered	T1,T12,T14
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	4955752	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	5221	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4955752	0	0
T1	60473	500	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	520	0	0
T12	65916	8151	0	0
T13	206992	0	0	0
T14	219308	1933	0	0
T15	251146	36921	0	0
T16	179250	0	0	0
T17	235792	1917	0	0
T18	204133	0	0	0
T23	0	1413	0	0
T25	0	976	0	0
T29	0	356	0	0
T63	0	440	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	5221	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	1	0	0
T12	65916	20	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	20	0	0
T16	179250	0	0	0
T17	235792	1	0	0
T18	204133	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T29	0	1	0	0
T63	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T12 T15 T27 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T12 T15 T27 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T12 T15 T27 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T12 T15 T27 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T12 T15 T27 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T12 T15 T27 
135        1/1                txn_bits_q <= '0;
           Tests:       T12 T15 T27 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T12,T15,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T12,T15,T27
1	1	Covered	T12,T15,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T12,T15,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T15,T27
1	1	Covered	T12,T15,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T12,T15,T27
0	0	1	Covered	T12,T15,T27
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T12,T15,T27
0	0	1	Covered	T12,T15,T27
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	4049847	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	4265	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4049847	0	0
T3	20691	0	0	0
T12	65916	7946	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	36717	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T27	0	16615	0	0
T62	96894	0	0	0
T80	0	33734	0	0
T81	0	31891	0	0
T82	0	7550	0	0
T83	0	17174	0	0
T84	0	1437	0	0
T85	0	8924	0	0
T86	0	32604	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	4265	0	0
T3	20691	0	0	0
T12	65916	20	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	20	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T27	0	20	0	0
T62	96894	0	0	0
T80	0	20	0	0
T81	0	40	0	0
T82	0	20	0	0
T83	0	20	0	0
T84	0	20	0	0
T85	0	20	0	0
T86	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T2 T5 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T2 T5 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T2 T5 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T2 T5 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T2 T5 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T2 T5 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T2 T5 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T24
1	1	Covered	T2,T5,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T24
1	1	Covered	T2,T5,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T24
0	0	1	Covered	T2,T5,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T24
0	0	1	Covered	T2,T5,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1019946	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1069	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1019946	0	0
T2	71662	374	0	0
T3	20691	0	0	0
T5	0	231	0	0
T8	0	374	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	5722	0	0
T31	0	11355	0	0
T43	0	206	0	0
T44	0	1452	0	0
T46	0	206	0	0
T47	0	1940	0	0
T49	0	999	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1069	0	0
T2	71662	1	0	0
T3	20691	0	0	0
T5	0	1	0	0
T8	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	0	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	28	0	0
T31	0	28	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T2 T14 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T2 T14 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T2 T14 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T2 T14 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T2 T14 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T2 T14 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T2 T14 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T14
1	1	Covered	T1,T2,T14

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T14
0	0	1	Covered	T1,T2,T14
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1704834	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1891	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1704834	0	0
T1	60473	444	0	0
T2	71662	372	0	0
T4	102900	0	0	0
T5	0	219	0	0
T6	0	490	0	0
T7	0	1408	0	0
T8	0	372	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1923	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	406	0	0
T29	0	321	0	0
T30	0	506	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1891	0	0
T1	60473	1	0	0
T2	71662	1	0	0
T4	102900	0	0	0
T5	0	1	0	0
T6	0	1	0	0
T7	0	1	0	0
T8	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T16 T28 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T16 T28 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T16 T28 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T16 T28 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T16 T28 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T16 T28 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T16 T28 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T16,T28,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T16,T28,T24
1	1	Covered	T16,T28,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T16,T28,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T28,T24
1	1	Covered	T16,T28,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T16,T28,T24
0	0	1	Covered	T16,T28,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T16,T28,T24
0	0	1	Covered	T16,T28,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1217828	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1268	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1217828	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	4972	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	444	0	0
T25	121687	0	0	0
T28	0	4822	0	0
T29	59042	0	0	0
T31	0	962	0	0
T54	0	6024	0	0
T56	0	6220	0	0
T57	0	2168	0	0
T59	0	7676	0	0
T60	0	3507	0	0
T61	0	520	0	0
T62	96894	0	0	0
T63	79778	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1268	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	6	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	2	0	0
T25	121687	0	0	0
T28	0	3	0	0
T29	59042	0	0	0
T31	0	2	0	0
T54	0	4	0	0
T56	0	4	0	0
T57	0	4	0	0
T59	0	5	0	0
T60	0	4	0	0
T61	0	5	0	0
T62	96894	0	0	0
T63	79778	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T16 T28 T24 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T16 T28 T24 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T16 T28 T24 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T16 T28 T24 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T16 T28 T24 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T16 T28 T24 
135        1/1                txn_bits_q <= '0;
           Tests:       T16 T28 T24 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T16,T28,T24

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T16,T28,T24
1	1	Covered	T16,T28,T24

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T16,T28,T24

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T28,T24
1	1	Covered	T16,T28,T24

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T16,T28,T24
0	0	1	Covered	T16,T28,T24
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T16,T28,T24
0	0	1	Covered	T16,T28,T24
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1137363	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1179	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1137363	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	2462	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	254	0	0
T25	121687	0	0	0
T28	0	4794	0	0
T29	59042	0	0	0
T31	0	481	0	0
T54	0	4608	0	0
T56	0	4766	0	0
T57	0	1697	0	0
T59	0	4791	0	0
T60	0	2527	0	0
T61	0	331	0	0
T62	96894	0	0	0
T63	79778	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1179	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T16	179250	3	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	1	0	0
T25	121687	0	0	0
T28	0	3	0	0
T29	59042	0	0	0
T31	0	1	0	0
T54	0	3	0	0
T56	0	3	0	0
T57	0	3	0	0
T59	0	3	0	0
T60	0	3	0	0
T61	0	3	0	0
T62	96894	0	0	0
T63	79778	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T14 T29 T30 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T14 T29 T30 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T14 T29 T30 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T14 T29 T30 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T14 T29 T30 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T14 T29 T30 
135        1/1                txn_bits_q <= '0;
           Tests:       T14 T29 T30 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T14,T29,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T14,T29,T30
1	1	Covered	T14,T29,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T14,T29,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T29,T30
1	1	Covered	T14,T29,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T14,T29,T30
0	0	1	Covered	T14,T29,T30
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T14,T29,T30
0	0	1	Covered	T14,T29,T30
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6281064	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	6666	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6281064	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T14	219308	1937	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	2292	0	0
T29	0	367	0	0
T30	0	520	0	0
T31	0	4547	0	0
T32	0	24210	0	0
T37	0	25741	0	0
T55	0	463	0	0
T58	0	21935	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T87	0	418	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6666	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	11	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	11	0	0
T32	0	57	0	0
T37	0	62	0	0
T55	0	1	0	0
T58	0	55	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T87	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6365351	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	6780	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6365351	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2272	0	0
T31	0	4541	0	0
T32	0	23976	0	0
T37	0	24655	0	0
T38	0	30788	0	0
T39	0	25712	0	0
T42	0	31565	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	20781	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	41237	0	0
T89	0	31564	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6780	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	57	0	0
T37	0	60	0	0
T38	0	70	0	0
T39	0	65	0	0
T42	0	76	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	55	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	51	0	0
T89	0	74	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6543501	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	6962	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6543501	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2255	0	0
T31	0	4541	0	0
T32	0	21158	0	0
T37	0	22407	0	0
T38	0	29208	0	0
T39	0	29198	0	0
T42	0	30331	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	18157	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	61869	0	0
T89	0	24923	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6962	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	51	0	0
T37	0	54	0	0
T38	0	67	0	0
T39	0	76	0	0
T42	0	76	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	51	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	76	0	0
T89	0	59	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6371737	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	6924	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6371737	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2275	0	0
T31	0	4541	0	0
T32	0	23532	0	0
T37	0	24159	0	0
T38	0	32018	0	0
T39	0	28188	0	0
T42	0	21909	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	18516	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	61559	0	0
T89	0	29565	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6924	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	57	0	0
T37	0	60	0	0
T38	0	74	0	0
T39	0	75	0	0
T42	0	56	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	55	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	76	0	0
T89	0	71	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T14 T29 T30 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T14 T29 T30 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T14 T29 T30 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T14 T29 T30 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T14 T29 T30 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T14 T29 T30 
135        1/1                txn_bits_q <= '0;
           Tests:       T14 T29 T30 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T14,T29,T30

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T14,T29,T30
1	1	Covered	T14,T29,T30

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T14,T29,T30

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T29,T30
1	1	Covered	T14,T29,T30

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T14,T29,T30
0	0	1	Covered	T14,T29,T30
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T14,T29,T30
0	0	1	Covered	T14,T29,T30
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1251682	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1309	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1251682	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T14	219308	1935	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	1715	0	0
T29	0	358	0	0
T30	0	518	0	0
T31	0	3688	0	0
T32	0	358	0	0
T37	0	1795	0	0
T55	0	454	0	0
T58	0	345	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T87	0	404	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1309	0	0
T3	20691	0	0	0
T5	47208	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T23	337212	0	0	0
T24	0	9	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T55	0	1	0	0
T58	0	1	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T87	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1301667	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1352	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1301667	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1689	0	0
T31	0	3682	0	0
T32	0	348	0	0
T37	0	1755	0	0
T38	0	1578	0	0
T39	0	2538	0	0
T42	0	2484	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	303	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	693	0	0
T89	0	3771	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1352	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	7	0	0
T42	0	6	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T89	0	9	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1268275	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1323	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1268275	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1727	0	0
T31	0	3682	0	0
T32	0	338	0	0
T37	0	1715	0	0
T38	0	1538	0	0
T39	0	2294	0	0
T42	0	2270	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	243	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	683	0	0
T89	0	3681	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1323	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	7	0	0
T42	0	6	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T89	0	9	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1277594	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1341	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1277594	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1712	0	0
T31	0	3682	0	0
T32	0	328	0	0
T37	0	1675	0	0
T38	0	1498	0	0
T39	0	2330	0	0
T42	0	2446	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	313	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	673	0	0
T89	0	3591	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1341	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	7	0	0
T42	0	6	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T89	0	9	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T14 T29 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T14 T29 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T14 T29 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T14 T29 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T14 T29 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T14 T29 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T14 T29 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6747477	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	7165	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6747477	0	0
T1	60473	497	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	514	0	0
T7	0	1428	0	0
T9	0	337	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1931	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	2178	0	0
T29	0	348	0	0
T30	0	514	0	0
T31	0	4511	0	0
T55	0	431	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	7165	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	11	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	11	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6731575	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	7187	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6731575	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2189	0	0
T31	0	4505	0	0
T32	0	24084	0	0
T37	0	24751	0	0
T38	0	30904	0	0
T41	0	868	0	0
T52	0	2511	0	0
T53	0	3976	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	21365	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	41333	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	7187	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	57	0	0
T37	0	60	0	0
T38	0	70	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	55	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	51	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	7062195	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	7472	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	7062195	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2178	0	0
T31	0	4505	0	0
T32	0	21254	0	0
T37	0	22491	0	0
T38	0	29318	0	0
T41	0	820	0	0
T52	0	2499	0	0
T53	0	3959	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	18831	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	62015	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	7472	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	51	0	0
T37	0	54	0	0
T38	0	67	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	51	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	76	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	6844817	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	7405	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	6844817	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	2160	0	0
T31	0	4505	0	0
T32	0	23640	0	0
T37	0	24255	0	0
T38	0	32142	0	0
T41	0	769	0	0
T52	0	2487	0	0
T53	0	3934	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	19072	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	61705	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	7405	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	11	0	0
T31	0	11	0	0
T32	0	57	0	0
T37	0	60	0	0
T38	0	74	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	55	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	76	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T14 T29 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T14 T29 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T14 T29 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T14 T29 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T14 T29 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T14 T29 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T14 T29 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1662660	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1803	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1662660	0	0
T1	60473	488	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	511	0	0
T7	0	1423	0	0
T9	0	335	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1929	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	1675	0	0
T29	0	339	0	0
T30	0	512	0	0
T31	0	3652	0	0
T55	0	422	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1803	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	9	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	9	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1717665	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1835	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1717665	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1622	0	0
T31	0	3646	0	0
T32	0	344	0	0
T37	0	1739	0	0
T38	0	1562	0	0
T41	0	816	0	0
T52	0	2463	0	0
T53	0	3910	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	283	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	689	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1835	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1680857	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1820	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1680857	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1668	0	0
T31	0	3646	0	0
T32	0	334	0	0
T37	0	1699	0	0
T38	0	1522	0	0
T41	0	871	0	0
T52	0	2451	0	0
T53	0	3880	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	345	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	679	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1820	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1690295	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1832	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1690295	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1574	0	0
T31	0	3646	0	0
T32	0	324	0	0
T37	0	1659	0	0
T38	0	1482	0	0
T41	0	827	0	0
T52	0	2439	0	0
T53	0	3864	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	293	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	669	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1832	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T1 T14 T29 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T1 T14 T29 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T1 T14 T29 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T1 T14 T29 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T1 T14 T29 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T1 T14 T29 
135        1/1                txn_bits_q <= '0;
           Tests:       T1 T14 T29 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T29
1	1	Covered	T1,T14,T29

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T14,T29
0	0	1	Covered	T1,T14,T29
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1731970	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1854	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1731970	0	0
T1	60473	475	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	504	0	0
T7	0	1421	0	0
T9	0	330	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1927	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	1623	0	0
T29	0	333	0	0
T30	0	510	0	0
T31	0	3634	0	0
T55	0	417	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1854	0	0
T1	60473	1	0	0
T2	71662	0	0	0
T4	102900	0	0	0
T6	0	1	0	0
T7	0	1	0	0
T9	0	1	0	0
T12	65916	0	0	0
T13	206992	0	0	0
T14	219308	1	0	0
T15	251146	0	0	0
T16	179250	0	0	0
T17	235792	0	0	0
T18	204133	0	0	0
T24	0	9	0	0
T29	0	1	0	0
T30	0	1	0	0
T31	0	9	0	0
T55	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1674493	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1801	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1674493	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1620	0	0
T31	0	3628	0	0
T32	0	342	0	0
T37	0	1731	0	0
T38	0	1554	0	0
T41	0	770	0	0
T52	0	2415	0	0
T53	0	3824	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	267	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	687	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1801	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1699729	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1840	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1699729	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1616	0	0
T31	0	3628	0	0
T32	0	332	0	0
T37	0	1691	0	0
T38	0	1514	0	0
T41	0	814	0	0
T52	0	2403	0	0
T53	0	3799	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	334	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	677	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1840	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T24 T31 T32 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T24 T31 T32 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T24 T31 T32 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T24 T31 T32 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T24 T31 T32 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T24 T31 T32 
135        1/1                txn_bits_q <= '0;
           Tests:       T24 T31 T32 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T24,T31,T32
1	1	Covered	T24,T31,T32

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T24,T31,T32
0	0	1	Covered	T24,T31,T32
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1658998	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1826	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1658998	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	1565	0	0
T31	0	3628	0	0
T32	0	322	0	0
T37	0	1651	0	0
T38	0	1474	0	0
T41	0	871	0	0
T52	0	2391	0	0
T53	0	3783	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	286	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	667	0	0
T90	284485	0	0	0
T91	41328	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1826	0	0
T8	55420	0	0	0
T9	59046	0	0	0
T24	442869	9	0	0
T31	0	9	0	0
T32	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T41	0	5	0	0
T52	0	6	0	0
T53	0	2	0	0
T54	349379	0	0	0
T55	75363	0	0	0
T58	0	1	0	0
T64	430906	0	0	0
T65	259395	0	0	0
T84	13999	0	0	0
T88	0	1	0	0
T90	284485	0	0	0
T91	41328	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

64                      
65         1/1            assign src_req = src_we_i | src_re_i;
           Tests:       T3 T24 T10 
66                      
67                        // busy indication back-pressures upstream if the register is accessed
68                        // again.  The busy indication is also used as a "commit" indication for
69                        // resolving software and hardware write conflicts
70                        always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71         1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
72         1/1                src_busy_q <= '0;
           Tests:       T1 T4 T2 
73         1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
74         1/1                src_busy_q <= 1'b1;
           Tests:       T3 T24 T10 
75         1/1              end else if (src_ack) begin
           Tests:       T1 T4 T2 
76         1/1                src_busy_q <= 1'b0;
           Tests:       T3 T24 T10 
77                          end
                        MISSING_ELSE
78                        end
79                      
80                        // A src_ack should only be sent if there was a src_req.
81                        // src_busy_q asserts whenever there is a src_req.  By association,
82                        // whenever src_ack is seen, then src_busy must be high.
83                        `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84                      
85         1/1            assign src_busy_o = src_busy_q;
           Tests:       T1 T4 T2 
86                      
87                        // src_q acts as both the write holding register and the software read back
88                        // register.
89                        // When software performs a write, the write data is captured in src_q for
90                        // CDC purposes.  When not performing a write, the src_q reflects the most recent
91                        // hardware value. For registers with no hardware access, this is simply the
92                        // the value programmed by software (or in the case R1C, W1C etc) the value after
93                        // the operation. For registers with hardware access, this reflects a potentially
94                        // delayed version of the real value, as the software facing updates lag real
95                        // time updates.
96                        //
97                        // To resolve software and hardware conflicts, the process is as follows:
98                        // When software issues a write, this module asserts "busy".  While busy,
99                        // src_q does not take on destination value updates.  Since the
100                       // logic has committed to updating based on software command, there is an irreversible
101                       // window from which hardware writes are ignored.  Once the busy window completes,
102                       // the cdc portion then begins sampling once more.
103                       //
104                       // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105                       // software is always prioritized.  The main difference is the conflict resolution window
106                       // is now larger instead of just one destination clock cycle.
107                     
108                       logic busy;
109        1/1            assign busy = src_busy_q & !src_ack;
           Tests:       T1 T4 T2 
110                     
111                       // This is the current destination value
112                       logic [DataWidth-1:0] dst_qs;
113                       logic src_update;
114                       always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115        1/1              if (!rst_src_ni) begin
           Tests:       T1 T4 T2 
116        1/1                src_q <= ResetVal;
           Tests:       T1 T4 T2 
117        1/1                txn_bits_q <= '0;
           Tests:       T1 T4 T2 
118        1/1              end else if (src_req) begin
           Tests:       T1 T4 T2 
119                           // See assertion below
120                           // At the beginning of a software initiated transaction, the following
121                           // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122                           // change for the duration of the synchronization operation.
123        1/1                src_q <= src_wd_i & BitMask;
           Tests:       T3 T24 T10 
124        1/1                txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
           Tests:       T3 T24 T10 
125        1/1              end else if (src_busy_q && src_ack || src_update && !busy) begin
           Tests:       T1 T4 T2 
126                           // sample data whenever a busy transaction finishes OR
127                           // when an update pulse is seen.
128                           // TODO: We should add a cover group to test different sync timings
129                           // between src_ack and src_update. ie. there can be 3 scenarios:
130                           // 1. update one cycle before ack
131                           // 2. ack one cycle before update
132                           // 3. update / ack on the same cycle
133                           // During all 3 cases the read data should be correct
134        1/1                src_q <= dst_qs;
           Tests:       T3 T24 T10 
135        1/1                txn_bits_q <= '0;
           Tests:       T3 T24 T10 
136                         end
                        MISSING_ELSE
137                       end
138                     
139                       // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140                       // (decoded from address) is busy. So this creates a situation in the current design where
141                       // src_req_i and busy can never be high at the same time.
142                       // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143                       // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144                       // condition cannot be met.
145                       // Thus we add an assertion here to ensure the condition is always satisfied.
146                       `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147                     
148                       // reserved bits are not used
149                       logic unused_wd;
150        1/1            assign unused_wd = ^src_wd_i;
           Tests:       T1 T4 T2 
151                     
152                       // src_q is always updated in the clk_src domain.
153                       // when performing an update to the destination domain, it is guaranteed
154                       // to not change by protocol.
155        1/1            assign src_qs_o = src_q;
           Tests:       T1 T4 T2 
156        1/1            assign dst_wd_o = src_q;
           Tests:       T1 T4 T2 
157                     
158                       ////////////////////////////
159                       // CDC handling
160                       ////////////////////////////
161                     
162                       logic dst_req_from_src;
163                       logic dst_req;
164                     
165                     
166                       // the software transaction is pulse synced across the domain.
167                       // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168                       prim_pulse_sync u_src_to_dst_req (
169                         .clk_src_i,
170                         .rst_src_ni,
171                         .clk_dst_i,
172                         .rst_dst_ni,
173                         .src_pulse_i(src_req),
174                         .dst_pulse_o(dst_req_from_src)
175                       );
176                     
177                       prim_reg_cdc_arb #(
178                         .DataWidth(DataWidth),
179                         .ResetVal(ResetVal),
180                         .DstWrReq(DstWrReq)
181                       ) u_arb (
182                         .clk_src_i,
183                         .rst_src_ni,
184                         .clk_dst_i,
185                         .rst_dst_ni,
186                         .src_ack_o(src_ack),
187                         .src_update_o(src_update),
188                         .dst_req_i(dst_req_from_src),
189                         .dst_req_o(dst_req),
190                         .dst_update_i,
191                         .dst_ds_i,
192                         .dst_qs_i,
193                         .dst_qs_o(dst_qs)
194                       );
195                     
196                     
197                       // Each is valid only when destination request pulse is high; this is important in not propagating
198                       // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199                       // reset.
200        1/1            assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
           Tests:       T1 T4 T2 

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T3,T24,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T3,T24,T10
1	1	Covered	T3,T24,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T24,T10
1	-	Covered	T3,T24,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T3,T24,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T24,T10
1	1	Covered	T3,T24,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

71             if (!rst_src_ni) begin
               -1-  
72               src_busy_q <= '0;
                 ==>
73             end else if (src_req) begin
                        -2-  
74               src_busy_q <= 1'b1;
                 ==>
75             end else if (src_ack) begin
                        -3-  
76               src_busy_q <= 1'b0;
                 ==>
77             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T3,T24,T10
0	0	1	Covered	T3,T24,T10
0	0	0	Covered	T1,T4,T2

115            if (!rst_src_ni) begin
               -1-  
116              src_q <= ResetVal;
                 ==>
117              txn_bits_q <= '0;
118            end else if (src_req) begin
                        -2-  
119              // See assertion below
120              // At the beginning of a software initiated transaction, the following
121              // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122              // change for the duration of the synchronization operation.
123              src_q <= src_wd_i & BitMask;
                 ==>
124              txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125            end else if (src_busy_q && src_ack || src_update && !busy) begin
                        -3-  
126              // sample data whenever a busy transaction finishes OR
127              // when an update pulse is seen.
128              // TODO: We should add a cover group to test different sync timings
129              // between src_ack and src_update. ie. there can be 3 scenarios:
130              // 1. update one cycle before ack
131              // 2. ack one cycle before update
132              // 3. update / ack on the same cycle
133              // During all 3 cases the read data should be correct
134              src_q <= dst_qs;
                 ==>
135              txn_bits_q <= '0;
136            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T3,T24,T10
0	0	1	Covered	T3,T24,T10
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1004924884	1021462	0	0
DstReqKnown_A	6217524	5556930	0	0
SrcAckBusyChk_A	1004924884	1056	0	0
SrcBusyKnown_A	1004924884	1004507440	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1021462	0	0
T3	20691	589	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	3430	0	0
T11	0	1643	0	0
T24	0	731	0	0
T25	121687	0	0	0
T27	128256	0	0	0
T29	59042	0	0	0
T31	0	1552	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	834	0	0
T67	0	274	0	0
T68	0	713	0	0
T69	95170	0	0	0
T70	214377	0	0	0
T92	0	1803	0	0
T93	0	3293	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6217524	5556930	0	0
T1	483	83	0	0
T2	681	281	0	0
T4	420	20	0	0
T12	527	127	0	0
T13	422	22	0	0
T14	452	52	0	0
T15	502	102	0	0
T16	716	316	0	0
T17	491	91	0	0
T18	1786	1386	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1056	0	0
T3	20691	4	0	0
T5	47208	0	0	0
T6	62486	0	0	0
T10	0	2	0	0
T11	0	2	0	0
T24	0	4	0	0
T25	121687	0	0	0
T27	128256	0	0	0
T29	59042	0	0	0
T31	0	4	0	0
T62	96894	0	0	0
T63	79778	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	95170	0	0	0
T70	214377	0	0	0
T92	0	2	0	0
T93	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1004924884	1004507440	0	0
T1	60473	60423	0	0
T2	71662	71605	0	0
T4	102900	102805	0	0
T12	65916	65866	0	0
T13	206992	206937	0	0
T14	219308	219226	0	0
T15	251146	251072	0	0
T16	179250	179175	0	0
T17	235792	235699	0	0
T18	204133	204047	0	0