| T167 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3370882034 |
|
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Oct 09 07:17:23 AM UTC 24 |
Oct 09 07:17:34 AM UTC 24 |
10888199284 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.351823568 |
|
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Oct 09 07:17:21 AM UTC 24 |
Oct 09 07:17:34 AM UTC 24 |
5416826024 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.4016756014 |
|
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Oct 09 07:17:26 AM UTC 24 |
Oct 09 07:17:34 AM UTC 24 |
2461704476 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.226593027 |
|
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Oct 09 07:17:24 AM UTC 24 |
Oct 09 07:17:35 AM UTC 24 |
2112336001 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.3708709474 |
|
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Oct 09 07:16:55 AM UTC 24 |
Oct 09 07:17:37 AM UTC 24 |
55720693592 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3769502127 |
|
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Oct 09 07:16:31 AM UTC 24 |
Oct 09 07:17:37 AM UTC 24 |
74318203300 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.3180751778 |
|
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Oct 09 07:17:59 AM UTC 24 |
Oct 09 07:18:02 AM UTC 24 |
2276886521 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.1839010462 |
|
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Oct 09 07:17:28 AM UTC 24 |
Oct 09 07:17:39 AM UTC 24 |
2612559528 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3253060821 |
|
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Oct 09 07:16:12 AM UTC 24 |
Oct 09 07:17:39 AM UTC 24 |
49476390543 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3417461573 |
|
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Oct 09 07:17:28 AM UTC 24 |
Oct 09 07:17:41 AM UTC 24 |
2510348860 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.3914424466 |
|
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Oct 09 07:17:37 AM UTC 24 |
Oct 09 07:17:41 AM UTC 24 |
2128466608 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2976512898 |
|
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Oct 09 07:17:36 AM UTC 24 |
Oct 09 07:17:41 AM UTC 24 |
2028727815 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.279794597 |
|
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Oct 09 07:17:35 AM UTC 24 |
Oct 09 07:17:43 AM UTC 24 |
8198965946 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.2245913422 |
|
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Oct 09 07:17:35 AM UTC 24 |
Oct 09 07:17:43 AM UTC 24 |
9919683879 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.712458166 |
|
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Oct 09 07:17:38 AM UTC 24 |
Oct 09 07:17:44 AM UTC 24 |
2500358052 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2875602836 |
|
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Oct 09 07:17:41 AM UTC 24 |
Oct 09 07:17:44 AM UTC 24 |
8933307965 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.3979154294 |
|
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Oct 09 07:16:37 AM UTC 24 |
Oct 09 07:17:45 AM UTC 24 |
11776683939 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3189552298 |
|
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Oct 09 07:17:38 AM UTC 24 |
Oct 09 07:17:45 AM UTC 24 |
2244125548 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1766839553 |
|
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Oct 09 07:17:32 AM UTC 24 |
Oct 09 07:17:47 AM UTC 24 |
6702187905 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.1807129471 |
|
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Oct 09 07:14:54 AM UTC 24 |
Oct 09 07:17:48 AM UTC 24 |
116235470186 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2006286925 |
|
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Oct 09 07:17:41 AM UTC 24 |
Oct 09 07:17:49 AM UTC 24 |
3769621278 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.2484994683 |
|
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Oct 09 07:17:40 AM UTC 24 |
Oct 09 07:17:49 AM UTC 24 |
2614843603 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1853125144 |
|
|
Oct 09 07:17:46 AM UTC 24 |
Oct 09 07:17:49 AM UTC 24 |
2144096650 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.3611187104 |
|
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Oct 09 07:17:29 AM UTC 24 |
Oct 09 07:17:50 AM UTC 24 |
3562068152 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.2340798120 |
|
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Oct 09 07:17:39 AM UTC 24 |
Oct 09 07:17:51 AM UTC 24 |
2514155129 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.2163161311 |
|
|
Oct 09 07:18:02 AM UTC 24 |
Oct 09 07:18:05 AM UTC 24 |
3501505716 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3582325301 |
|
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Oct 09 07:17:40 AM UTC 24 |
Oct 09 07:17:51 AM UTC 24 |
2588066541 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.4215831911 |
|
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Oct 09 07:17:34 AM UTC 24 |
Oct 09 07:17:52 AM UTC 24 |
3699963633 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.3933285821 |
|
|
Oct 09 07:17:48 AM UTC 24 |
Oct 09 07:17:53 AM UTC 24 |
2475026446 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1409744421 |
|
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Oct 09 07:17:46 AM UTC 24 |
Oct 09 07:17:55 AM UTC 24 |
2014268558 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.1917254297 |
|
|
Oct 09 07:17:44 AM UTC 24 |
Oct 09 07:17:55 AM UTC 24 |
4166298738 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.662755541 |
|
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Oct 09 07:17:50 AM UTC 24 |
Oct 09 07:17:56 AM UTC 24 |
2632251438 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3234813319 |
|
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Oct 09 07:17:52 AM UTC 24 |
Oct 09 07:17:56 AM UTC 24 |
5817318519 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.563099313 |
|
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Oct 09 07:17:51 AM UTC 24 |
Oct 09 07:17:58 AM UTC 24 |
2470741098 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.3465253685 |
|
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Oct 09 07:17:49 AM UTC 24 |
Oct 09 07:17:58 AM UTC 24 |
2267994154 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.311915337 |
|
|
Oct 09 07:17:49 AM UTC 24 |
Oct 09 07:17:58 AM UTC 24 |
2508180623 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.544056169 |
|
|
Oct 09 07:17:45 AM UTC 24 |
Oct 09 07:17:59 AM UTC 24 |
39779183166 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.402489342 |
|
|
Oct 09 07:17:54 AM UTC 24 |
Oct 09 07:17:59 AM UTC 24 |
11644561632 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1323655421 |
|
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Oct 09 07:17:56 AM UTC 24 |
Oct 09 07:18:00 AM UTC 24 |
2148519304 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2499821253 |
|
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Oct 09 07:17:51 AM UTC 24 |
Oct 09 07:18:01 AM UTC 24 |
3525368469 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3807401786 |
|
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Oct 09 07:17:56 AM UTC 24 |
Oct 09 07:18:05 AM UTC 24 |
2011633143 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.3523660342 |
|
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Oct 09 07:17:59 AM UTC 24 |
Oct 09 07:18:07 AM UTC 24 |
2511351611 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3546862206 |
|
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Oct 09 07:17:44 AM UTC 24 |
Oct 09 07:18:10 AM UTC 24 |
26098414071 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.4156937941 |
|
|
Oct 09 07:17:58 AM UTC 24 |
Oct 09 07:18:10 AM UTC 24 |
2466038574 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2326120529 |
|
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Oct 09 07:18:00 AM UTC 24 |
Oct 09 07:18:11 AM UTC 24 |
3754300332 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.3920170130 |
|
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Oct 09 07:18:08 AM UTC 24 |
Oct 09 07:18:12 AM UTC 24 |
2039449357 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3741119222 |
|
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Oct 09 07:18:00 AM UTC 24 |
Oct 09 07:18:12 AM UTC 24 |
3936338112 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.411530956 |
|
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Oct 09 07:17:59 AM UTC 24 |
Oct 09 07:18:12 AM UTC 24 |
2612727805 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.3916587405 |
|
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Oct 09 07:18:11 AM UTC 24 |
Oct 09 07:18:13 AM UTC 24 |
2503528176 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.854977468 |
|
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Oct 09 07:17:21 AM UTC 24 |
Oct 09 07:18:16 AM UTC 24 |
81631221559 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.3199069458 |
|
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Oct 09 07:18:12 AM UTC 24 |
Oct 09 07:18:16 AM UTC 24 |
2061327519 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.90037865 |
|
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Oct 09 07:18:13 AM UTC 24 |
Oct 09 07:18:17 AM UTC 24 |
3387181913 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2456963851 |
|
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Oct 09 07:18:13 AM UTC 24 |
Oct 09 07:18:18 AM UTC 24 |
2639682834 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2794762194 |
|
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Oct 09 07:18:14 AM UTC 24 |
Oct 09 07:18:19 AM UTC 24 |
3447392234 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.113148515 |
|
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Oct 09 07:18:05 AM UTC 24 |
Oct 09 07:18:20 AM UTC 24 |
3343239204 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.3531196276 |
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Oct 09 07:14:25 AM UTC 24 |
Oct 09 07:18:21 AM UTC 24 |
159428579389 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4068631413 |
|
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Oct 09 07:18:16 AM UTC 24 |
Oct 09 07:18:22 AM UTC 24 |
6712459340 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2301309759 |
|
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Oct 09 07:18:11 AM UTC 24 |
Oct 09 07:18:22 AM UTC 24 |
2110039941 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1099061471 |
|
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Oct 09 07:18:01 AM UTC 24 |
Oct 09 07:18:23 AM UTC 24 |
733056747631 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.448230173 |
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Oct 09 07:18:18 AM UTC 24 |
Oct 09 07:18:25 AM UTC 24 |
2418934048 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3196832581 |
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Oct 09 07:18:22 AM UTC 24 |
Oct 09 07:18:25 AM UTC 24 |
2133713457 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1785476785 |
|
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Oct 09 07:18:21 AM UTC 24 |
Oct 09 07:18:26 AM UTC 24 |
2517866611 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3316129642 |
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Oct 09 07:18:13 AM UTC 24 |
Oct 09 07:18:27 AM UTC 24 |
2514996343 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.3858620726 |
|
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Oct 09 07:18:20 AM UTC 24 |
Oct 09 07:18:27 AM UTC 24 |
2118575709 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2962805475 |
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Oct 09 07:18:23 AM UTC 24 |
Oct 09 07:18:28 AM UTC 24 |
2526069448 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.988126588 |
|
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Oct 09 07:18:18 AM UTC 24 |
Oct 09 07:18:30 AM UTC 24 |
7038645983 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1588153856 |
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Oct 09 07:18:03 AM UTC 24 |
Oct 09 07:18:31 AM UTC 24 |
150987182479 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1707386981 |
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Oct 09 07:18:19 AM UTC 24 |
Oct 09 07:18:31 AM UTC 24 |
15125287687 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.155676520 |
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Oct 09 07:18:20 AM UTC 24 |
Oct 09 07:18:31 AM UTC 24 |
2012430187 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.970769028 |
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Oct 09 07:18:26 AM UTC 24 |
Oct 09 07:18:32 AM UTC 24 |
3128735675 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2969930132 |
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Oct 09 07:18:27 AM UTC 24 |
Oct 09 07:18:32 AM UTC 24 |
10691545314 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.230276698 |
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Oct 09 07:18:28 AM UTC 24 |
Oct 09 07:18:35 AM UTC 24 |
4148918516 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.1898163899 |
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Oct 09 07:18:24 AM UTC 24 |
Oct 09 07:18:37 AM UTC 24 |
2610321546 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2845748139 |
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Oct 09 07:17:52 AM UTC 24 |
Oct 09 07:18:39 AM UTC 24 |
368558289371 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1831763587 |
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Oct 09 07:18:33 AM UTC 24 |
Oct 09 07:18:39 AM UTC 24 |
2116095926 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.1450542174 |
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Oct 09 07:18:28 AM UTC 24 |
Oct 09 07:19:10 AM UTC 24 |
25434831363 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2707763736 |
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Oct 09 07:17:52 AM UTC 24 |
Oct 09 07:18:41 AM UTC 24 |
51292392476 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.486772983 |
|
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Oct 09 07:18:26 AM UTC 24 |
Oct 09 07:18:42 AM UTC 24 |
3234754295 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.1233007067 |
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Oct 09 07:15:03 AM UTC 24 |
Oct 09 07:18:43 AM UTC 24 |
76988466026 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2561593940 |
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Oct 09 07:18:31 AM UTC 24 |
Oct 09 07:18:43 AM UTC 24 |
2013669562 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2821905088 |
|
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Oct 09 07:18:38 AM UTC 24 |
Oct 09 07:18:43 AM UTC 24 |
2634762583 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.3076386382 |
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Oct 09 07:18:33 AM UTC 24 |
Oct 09 07:18:44 AM UTC 24 |
2183247899 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2601790009 |
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Oct 09 07:18:07 AM UTC 24 |
Oct 09 07:18:45 AM UTC 24 |
12539254344 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.4042181766 |
|
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Oct 09 07:18:33 AM UTC 24 |
Oct 09 07:18:47 AM UTC 24 |
2460699382 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.3824377836 |
|
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Oct 09 07:18:39 AM UTC 24 |
Oct 09 07:18:48 AM UTC 24 |
3230325245 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.4103415437 |
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Oct 09 07:17:08 AM UTC 24 |
Oct 09 07:18:48 AM UTC 24 |
129188053854 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.851615886 |
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Oct 09 07:18:36 AM UTC 24 |
Oct 09 07:18:48 AM UTC 24 |
2513630781 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2591324312 |
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Oct 09 07:15:50 AM UTC 24 |
Oct 09 07:18:48 AM UTC 24 |
121261016338 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.225969606 |
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Oct 09 07:17:34 AM UTC 24 |
Oct 09 07:18:49 AM UTC 24 |
24079665325 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.1473248776 |
|
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Oct 09 07:18:46 AM UTC 24 |
Oct 09 07:18:50 AM UTC 24 |
2023214742 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.500165057 |
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Oct 09 07:18:31 AM UTC 24 |
Oct 09 07:18:53 AM UTC 24 |
15538568954 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2847380240 |
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Oct 09 07:18:44 AM UTC 24 |
Oct 09 07:18:53 AM UTC 24 |
3040445868 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3911206892 |
|
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Oct 09 07:18:51 AM UTC 24 |
Oct 09 07:18:55 AM UTC 24 |
3037645938 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.751488524 |
|
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Oct 09 07:18:49 AM UTC 24 |
Oct 09 07:18:55 AM UTC 24 |
2632830499 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.472315273 |
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Oct 09 07:18:49 AM UTC 24 |
Oct 09 07:18:55 AM UTC 24 |
2257561134 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1563433680 |
|
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Oct 09 07:18:41 AM UTC 24 |
Oct 09 07:18:55 AM UTC 24 |
5539343127 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.1337315768 |
|
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Oct 09 07:18:51 AM UTC 24 |
Oct 09 07:18:56 AM UTC 24 |
3525859531 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1767439193 |
|
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Oct 09 07:18:49 AM UTC 24 |
Oct 09 07:18:57 AM UTC 24 |
2458643642 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.2868910395 |
|
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Oct 09 07:18:49 AM UTC 24 |
Oct 09 07:18:58 AM UTC 24 |
2520594229 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2539620763 |
|
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Oct 09 07:18:45 AM UTC 24 |
Oct 09 07:18:59 AM UTC 24 |
11843340981 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.974351835 |
|
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Oct 09 07:18:48 AM UTC 24 |
Oct 09 07:18:59 AM UTC 24 |
2110261355 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3099221474 |
|
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Oct 09 07:18:56 AM UTC 24 |
Oct 09 07:19:02 AM UTC 24 |
2022616184 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3331790480 |
|
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Oct 09 07:17:53 AM UTC 24 |
Oct 09 07:19:02 AM UTC 24 |
23080364067 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2170198756 |
|
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Oct 09 07:18:59 AM UTC 24 |
Oct 09 07:19:04 AM UTC 24 |
2469130899 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.994371208 |
|
|
Oct 09 07:19:00 AM UTC 24 |
Oct 09 07:19:04 AM UTC 24 |
2162871715 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.1956328668 |
|
|
Oct 09 07:18:57 AM UTC 24 |
Oct 09 07:19:09 AM UTC 24 |
2112677699 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1705812536 |
|
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Oct 09 07:17:42 AM UTC 24 |
Oct 09 07:19:07 AM UTC 24 |
181081536999 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.4123469894 |
|
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Oct 09 07:19:03 AM UTC 24 |
Oct 09 07:19:08 AM UTC 24 |
2635001422 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1379797243 |
|
|
Oct 09 07:18:56 AM UTC 24 |
Oct 09 07:19:08 AM UTC 24 |
3139162524 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3131605510 |
|
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Oct 09 07:14:42 AM UTC 24 |
Oct 09 07:19:08 AM UTC 24 |
83736705648 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.639334213 |
|
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Oct 09 07:18:45 AM UTC 24 |
Oct 09 07:19:09 AM UTC 24 |
4710104027 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1236647662 |
|
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Oct 09 07:18:56 AM UTC 24 |
Oct 09 07:19:09 AM UTC 24 |
5606401440 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1093358482 |
|
|
Oct 09 07:19:05 AM UTC 24 |
Oct 09 07:19:10 AM UTC 24 |
3161936566 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1843979641 |
|
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Oct 09 07:19:07 AM UTC 24 |
Oct 09 07:19:11 AM UTC 24 |
5608316840 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2620523674 |
|
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Oct 09 07:19:03 AM UTC 24 |
Oct 09 07:19:14 AM UTC 24 |
4662964019 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3809114269 |
|
|
Oct 09 07:19:10 AM UTC 24 |
Oct 09 07:19:14 AM UTC 24 |
2030714256 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.4002611474 |
|
|
Oct 09 07:19:10 AM UTC 24 |
Oct 09 07:19:15 AM UTC 24 |
2464282674 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2260621142 |
|
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Oct 09 07:18:54 AM UTC 24 |
Oct 09 07:19:15 AM UTC 24 |
103124949163 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.176674511 |
|
|
Oct 09 07:19:01 AM UTC 24 |
Oct 09 07:19:15 AM UTC 24 |
2510928355 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1281576959 |
|
|
Oct 09 07:19:11 AM UTC 24 |
Oct 09 07:19:16 AM UTC 24 |
2630758390 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.394826916 |
|
|
Oct 09 07:18:56 AM UTC 24 |
Oct 09 07:19:19 AM UTC 24 |
10954332684 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.784695711 |
|
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Oct 09 07:19:11 AM UTC 24 |
Oct 09 07:19:20 AM UTC 24 |
2513154359 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1237955022 |
|
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Oct 09 07:19:10 AM UTC 24 |
Oct 09 07:19:21 AM UTC 24 |
2113410804 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2534867533 |
|
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Oct 09 07:19:11 AM UTC 24 |
Oct 09 07:19:22 AM UTC 24 |
2056820923 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2131059683 |
|
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Oct 09 07:19:15 AM UTC 24 |
Oct 09 07:19:22 AM UTC 24 |
3352957370 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.2542300886 |
|
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Oct 09 07:19:17 AM UTC 24 |
Oct 09 07:19:24 AM UTC 24 |
3053515428 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.4012601824 |
|
|
Oct 09 07:19:10 AM UTC 24 |
Oct 09 07:19:24 AM UTC 24 |
7742130705 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2579826951 |
|
|
Oct 09 07:19:22 AM UTC 24 |
Oct 09 07:19:25 AM UTC 24 |
2093146560 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2329711961 |
|
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Oct 09 07:17:11 AM UTC 24 |
Oct 09 07:19:25 AM UTC 24 |
626542188607 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1977265680 |
|
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Oct 09 07:18:31 AM UTC 24 |
Oct 09 07:19:26 AM UTC 24 |
194411859123 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.1712133232 |
|
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Oct 09 07:19:23 AM UTC 24 |
Oct 09 07:19:26 AM UTC 24 |
2180085476 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1489713006 |
|
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Oct 09 07:19:20 AM UTC 24 |
Oct 09 07:19:27 AM UTC 24 |
20841608780 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3345556657 |
|
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Oct 09 07:19:23 AM UTC 24 |
Oct 09 07:19:27 AM UTC 24 |
2481981152 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2805059688 |
|
|
Oct 09 07:19:16 AM UTC 24 |
Oct 09 07:19:27 AM UTC 24 |
3008213739 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1080784220 |
|
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Oct 09 07:20:02 AM UTC 24 |
Oct 09 07:20:06 AM UTC 24 |
2932271470 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.319423412 |
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Oct 09 07:17:33 AM UTC 24 |
Oct 09 07:19:29 AM UTC 24 |
89810809529 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.947273338 |
|
|
Oct 09 07:19:26 AM UTC 24 |
Oct 09 07:19:30 AM UTC 24 |
2622112612 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.664901681 |
|
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Oct 09 07:20:05 AM UTC 24 |
Oct 09 07:20:09 AM UTC 24 |
2112256481 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3667106835 |
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Oct 09 07:19:27 AM UTC 24 |
Oct 09 07:19:31 AM UTC 24 |
3646092018 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.457693915 |
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Oct 09 07:19:24 AM UTC 24 |
Oct 09 07:19:31 AM UTC 24 |
2170270801 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1788613620 |
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Oct 09 07:16:22 AM UTC 24 |
Oct 09 07:19:32 AM UTC 24 |
218017736443 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.1490001180 |
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Oct 09 07:19:26 AM UTC 24 |
Oct 09 07:19:34 AM UTC 24 |
2516641340 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1063999362 |
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Oct 09 07:19:28 AM UTC 24 |
Oct 09 07:19:34 AM UTC 24 |
5469704701 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.2560646024 |
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Oct 09 07:19:31 AM UTC 24 |
Oct 09 07:19:35 AM UTC 24 |
2044573804 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.2848901879 |
|
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Oct 09 07:19:07 AM UTC 24 |
Oct 09 07:19:35 AM UTC 24 |
70573843618 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1677618203 |
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Oct 09 07:16:11 AM UTC 24 |
Oct 09 07:19:35 AM UTC 24 |
147798688871 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2771769380 |
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Oct 09 07:19:14 AM UTC 24 |
Oct 09 07:19:37 AM UTC 24 |
4829142049 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.3394581999 |
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Oct 09 07:15:23 AM UTC 24 |
Oct 09 07:19:38 AM UTC 24 |
128349270974 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.4217967807 |
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Oct 09 07:19:35 AM UTC 24 |
Oct 09 07:19:41 AM UTC 24 |
2518954712 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.1005328550 |
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Oct 09 07:19:27 AM UTC 24 |
Oct 09 07:19:42 AM UTC 24 |
4611273939 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1800695948 |
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Oct 09 07:19:36 AM UTC 24 |
Oct 09 07:19:42 AM UTC 24 |
3337058066 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3998962037 |
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Oct 09 07:19:27 AM UTC 24 |
Oct 09 07:19:43 AM UTC 24 |
3167259025 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1380984866 |
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Oct 09 07:19:32 AM UTC 24 |
Oct 09 07:19:43 AM UTC 24 |
2109824953 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2836780092 |
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Oct 09 07:14:54 AM UTC 24 |
Oct 09 07:19:43 AM UTC 24 |
92023975944 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1875116208 |
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Oct 09 07:19:38 AM UTC 24 |
Oct 09 07:19:44 AM UTC 24 |
3281824817 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.308099874 |
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Oct 09 07:19:33 AM UTC 24 |
Oct 09 07:19:44 AM UTC 24 |
2023170912 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2457496958 |
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Oct 09 07:19:32 AM UTC 24 |
Oct 09 07:19:47 AM UTC 24 |
2459733999 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.500942796 |
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Oct 09 07:19:43 AM UTC 24 |
Oct 09 07:19:48 AM UTC 24 |
2029986294 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3980722031 |
|
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Oct 09 07:19:35 AM UTC 24 |
Oct 09 07:19:48 AM UTC 24 |
2608332760 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2913915130 |
|
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Oct 09 07:19:44 AM UTC 24 |
Oct 09 07:19:48 AM UTC 24 |
2133499765 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.2061715437 |
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Oct 09 07:19:45 AM UTC 24 |
Oct 09 07:19:50 AM UTC 24 |
2030193318 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.1027141375 |
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Oct 09 07:19:36 AM UTC 24 |
Oct 09 07:19:50 AM UTC 24 |
8189540601 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.1543501761 |
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Oct 09 07:19:44 AM UTC 24 |
Oct 09 07:19:51 AM UTC 24 |
2468524861 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1455343253 |
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Oct 09 07:19:48 AM UTC 24 |
Oct 09 07:19:52 AM UTC 24 |
3610690146 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.470429910 |
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Oct 09 07:19:48 AM UTC 24 |
Oct 09 07:19:52 AM UTC 24 |
8949121899 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3840123287 |
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Oct 09 07:19:38 AM UTC 24 |
Oct 09 07:19:53 AM UTC 24 |
70294696573 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2376475200 |
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Oct 09 07:19:29 AM UTC 24 |
Oct 09 07:19:54 AM UTC 24 |
130007609679 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3958865764 |
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Oct 09 07:19:51 AM UTC 24 |
Oct 09 07:19:54 AM UTC 24 |
3008613160 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.966505694 |
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Oct 09 07:19:45 AM UTC 24 |
Oct 09 07:19:56 AM UTC 24 |
2508621244 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.676597705 |
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Oct 09 07:19:53 AM UTC 24 |
Oct 09 07:19:57 AM UTC 24 |
2036591934 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2282541968 |
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Oct 09 07:18:01 AM UTC 24 |
Oct 09 07:19:57 AM UTC 24 |
137914926269 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1744116524 |
|
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Oct 09 07:19:45 AM UTC 24 |
Oct 09 07:19:58 AM UTC 24 |
2610789078 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.2450751845 |
|
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Oct 09 07:19:54 AM UTC 24 |
Oct 09 07:19:59 AM UTC 24 |
2497327693 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3297005388 |
|
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Oct 09 07:19:41 AM UTC 24 |
Oct 09 07:20:01 AM UTC 24 |
9191676622 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.4232902125 |
|
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Oct 09 07:19:57 AM UTC 24 |
Oct 09 07:20:02 AM UTC 24 |
2627131896 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.2890430897 |
|
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Oct 09 07:19:16 AM UTC 24 |
Oct 09 07:20:02 AM UTC 24 |
107589593501 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2760829707 |
|
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Oct 09 07:19:29 AM UTC 24 |
Oct 09 07:20:02 AM UTC 24 |
1085220752703 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.1967038016 |
|
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Oct 09 07:19:54 AM UTC 24 |
Oct 09 07:20:03 AM UTC 24 |
2237825999 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.2210567865 |
|
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Oct 09 07:15:53 AM UTC 24 |
Oct 09 07:20:03 AM UTC 24 |
86672223505 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2168486262 |
|
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Oct 09 07:19:59 AM UTC 24 |
Oct 09 07:20:03 AM UTC 24 |
5189029025 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2538762023 |
|
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Oct 09 07:19:58 AM UTC 24 |
Oct 09 07:20:03 AM UTC 24 |
3541383476 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2177339339 |
|
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Oct 09 07:19:53 AM UTC 24 |
Oct 09 07:20:04 AM UTC 24 |
2109049244 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2721528050 |
|
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Oct 09 07:18:56 AM UTC 24 |
Oct 09 07:20:05 AM UTC 24 |
150104891494 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.748536621 |
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Oct 09 07:19:50 AM UTC 24 |
Oct 09 07:20:05 AM UTC 24 |
43895383848 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.1561402030 |
|
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Oct 09 07:19:55 AM UTC 24 |
Oct 09 07:20:06 AM UTC 24 |
2508944214 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.719423210 |
|
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Oct 09 07:20:54 AM UTC 24 |
Oct 09 07:20:58 AM UTC 24 |
2160139235 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1463814098 |
|
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Oct 09 07:19:58 AM UTC 24 |
Oct 09 07:20:06 AM UTC 24 |
3152267626 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3609840119 |
|
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Oct 09 07:19:48 AM UTC 24 |
Oct 09 07:20:07 AM UTC 24 |
4863337089 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2804325686 |
|
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Oct 09 07:20:05 AM UTC 24 |
Oct 09 07:20:07 AM UTC 24 |
2190027259 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3127375196 |
|
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Oct 09 07:19:52 AM UTC 24 |
Oct 09 07:20:09 AM UTC 24 |
5971712783 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2327645026 |
|
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Oct 09 07:20:05 AM UTC 24 |
Oct 09 07:20:10 AM UTC 24 |
2487232935 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3710769375 |
|
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Oct 09 07:20:06 AM UTC 24 |
Oct 09 07:20:10 AM UTC 24 |
2647496906 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.4225994841 |
|
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Oct 09 07:20:03 AM UTC 24 |
Oct 09 07:20:11 AM UTC 24 |
2008106145 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.2188125797 |
|
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Oct 09 07:20:07 AM UTC 24 |
Oct 09 07:20:13 AM UTC 24 |
4379626553 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.405816685 |
|
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Oct 09 07:19:36 AM UTC 24 |
Oct 09 07:20:14 AM UTC 24 |
101251268679 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3622896430 |
|
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Oct 09 07:20:06 AM UTC 24 |
Oct 09 07:20:14 AM UTC 24 |
3147730306 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1102492631 |
|
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Oct 09 07:20:07 AM UTC 24 |
Oct 09 07:20:14 AM UTC 24 |
3221505498 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1988214893 |
|
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Oct 09 07:19:52 AM UTC 24 |
Oct 09 07:20:15 AM UTC 24 |
16444321433 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2833721457 |
|
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Oct 09 07:20:11 AM UTC 24 |
Oct 09 07:20:16 AM UTC 24 |
2124738159 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.2312990552 |
|
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Oct 09 07:20:05 AM UTC 24 |
Oct 09 07:20:16 AM UTC 24 |
2511549610 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3752128327 |
|
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Oct 09 07:20:03 AM UTC 24 |
Oct 09 07:20:16 AM UTC 24 |
9353039320 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3627178054 |
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Oct 09 07:20:11 AM UTC 24 |
Oct 09 07:20:17 AM UTC 24 |
2017266872 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.4057906936 |
|
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Oct 09 07:20:14 AM UTC 24 |
Oct 09 07:20:18 AM UTC 24 |
2051281485 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1006897712 |
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Oct 09 07:20:07 AM UTC 24 |
Oct 09 07:20:19 AM UTC 24 |
7221171463 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.248089349 |
|
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Oct 09 07:20:12 AM UTC 24 |
Oct 09 07:20:20 AM UTC 24 |
2470241903 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2693263935 |
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Oct 09 07:20:10 AM UTC 24 |
Oct 09 07:20:22 AM UTC 24 |
5832321160 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3431877169 |
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Oct 09 07:20:16 AM UTC 24 |
Oct 09 07:20:23 AM UTC 24 |
2551222306 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1290635752 |
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Oct 09 07:20:17 AM UTC 24 |
Oct 09 07:20:23 AM UTC 24 |
4936010956 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.2273217175 |
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Oct 09 07:20:20 AM UTC 24 |
Oct 09 07:20:24 AM UTC 24 |
2053098543 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.4193272975 |
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Oct 09 07:20:14 AM UTC 24 |
Oct 09 07:20:24 AM UTC 24 |
2509321371 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2808712270 |
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Oct 09 07:19:17 AM UTC 24 |
Oct 09 07:20:26 AM UTC 24 |
45926885341 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.2423952593 |
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Oct 09 07:19:43 AM UTC 24 |
Oct 09 07:20:26 AM UTC 24 |
11744973637 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.1186389087 |
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Oct 09 07:20:16 AM UTC 24 |
Oct 09 07:20:28 AM UTC 24 |
3341544954 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.3893862841 |
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Oct 09 07:20:23 AM UTC 24 |
Oct 09 07:20:28 AM UTC 24 |
2126968929 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.121706541 |
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Oct 09 07:20:20 AM UTC 24 |
Oct 09 07:20:28 AM UTC 24 |
6672874860 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.1066999221 |
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Oct 09 07:20:24 AM UTC 24 |
Oct 09 07:20:28 AM UTC 24 |
2230901370 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.207365032 |
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Oct 09 07:20:15 AM UTC 24 |
Oct 09 07:20:29 AM UTC 24 |
2610241949 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.72758160 |
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Oct 09 07:16:23 AM UTC 24 |
Oct 09 07:20:30 AM UTC 24 |
96474963244 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.3668254544 |
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Oct 09 07:15:31 AM UTC 24 |
Oct 09 07:20:31 AM UTC 24 |
96198169374 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2517258313 |
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Oct 09 07:20:15 AM UTC 24 |
Oct 09 07:20:32 AM UTC 24 |
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| T129 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.647491934 |
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Oct 09 07:20:27 AM UTC 24 |
Oct 09 07:20:32 AM UTC 24 |
4757660657 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.622580797 |
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Oct 09 07:19:21 AM UTC 24 |
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129184487340 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.2960279687 |
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Oct 09 07:20:24 AM UTC 24 |
Oct 09 07:20:33 AM UTC 24 |
2444832097 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3808014292 |
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Oct 09 07:18:29 AM UTC 24 |
Oct 09 07:20:34 AM UTC 24 |
67425646423 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.3858537850 |
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Oct 09 07:20:32 AM UTC 24 |
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2123865731 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.2099463362 |
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Oct 09 07:20:34 AM UTC 24 |
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2545022862 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.659717657 |
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Oct 09 07:20:24 AM UTC 24 |
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2611839733 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.3103747052 |
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Oct 09 07:20:19 AM UTC 24 |
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| T192 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1918031201 |
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Oct 09 07:20:29 AM UTC 24 |
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| T633 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.1098571839 |
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Oct 09 07:20:31 AM UTC 24 |
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| T634 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3100498504 |
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Oct 09 07:20:29 AM UTC 24 |
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13709933991 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.3072136573 |
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Oct 09 07:20:24 AM UTC 24 |
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| T397 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3110884254 |
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Oct 09 07:15:25 AM UTC 24 |
Oct 09 07:20:39 AM UTC 24 |
96614746356 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2344235443 |
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Oct 09 07:20:35 AM UTC 24 |
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| T637 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.3375054948 |
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Oct 09 07:20:34 AM UTC 24 |
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| T301 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.4027106796 |
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Oct 09 07:16:33 AM UTC 24 |
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| T638 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3533389938 |
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Oct 09 07:20:38 AM UTC 24 |
Oct 09 07:20:42 AM UTC 24 |
8876804347 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2912307995 |
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Oct 09 07:20:37 AM UTC 24 |
Oct 09 07:20:42 AM UTC 24 |
3493074909 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.375047988 |
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Oct 09 07:20:34 AM UTC 24 |
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2211257563 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2038988196 |
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Oct 09 07:20:41 AM UTC 24 |
Oct 09 07:20:43 AM UTC 24 |
2125773754 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1445235515 |
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Oct 09 07:20:30 AM UTC 24 |
Oct 09 07:20:44 AM UTC 24 |
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| T642 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.562640648 |
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Oct 09 07:20:37 AM UTC 24 |
Oct 09 07:20:44 AM UTC 24 |
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| T643 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3954563192 |
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Oct 09 07:20:42 AM UTC 24 |
Oct 09 07:20:47 AM UTC 24 |
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| T644 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.272108453 |
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Oct 09 07:20:44 AM UTC 24 |
Oct 09 07:20:49 AM UTC 24 |
2749618161 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.810714462 |
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Oct 09 07:20:43 AM UTC 24 |
Oct 09 07:20:49 AM UTC 24 |
2539081880 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1570392708 |
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Oct 09 07:20:41 AM UTC 24 |
Oct 09 07:20:50 AM UTC 24 |
2113439417 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.350973557 |
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Oct 09 07:20:43 AM UTC 24 |
Oct 09 07:20:51 AM UTC 24 |
2616172241 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.827700917 |
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Oct 09 07:20:44 AM UTC 24 |
Oct 09 07:20:54 AM UTC 24 |
4528487711 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1547496568 |
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Oct 09 07:20:44 AM UTC 24 |
Oct 09 07:20:54 AM UTC 24 |
3311090139 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.19659285 |
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Oct 09 07:20:38 AM UTC 24 |
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3729731911 ps |