| T651 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.4122022497 |
|
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Oct 09 07:20:52 AM UTC 24 |
Oct 09 07:20:56 AM UTC 24 |
2024697043 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2606421173 |
|
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Oct 09 07:20:42 AM UTC 24 |
Oct 09 07:20:57 AM UTC 24 |
2466535619 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.1085081579 |
|
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Oct 09 07:20:03 AM UTC 24 |
Oct 09 07:20:57 AM UTC 24 |
132454508872 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.660545285 |
|
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Oct 09 07:20:39 AM UTC 24 |
Oct 09 07:20:58 AM UTC 24 |
6783619990 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.3670094987 |
|
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Oct 09 07:20:48 AM UTC 24 |
Oct 09 07:20:58 AM UTC 24 |
6015637587 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1065874302 |
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Oct 09 07:21:53 AM UTC 24 |
Oct 09 07:22:03 AM UTC 24 |
2013584268 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.718725518 |
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Oct 09 07:20:02 AM UTC 24 |
Oct 09 07:20:59 AM UTC 24 |
29335991551 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2794694530 |
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Oct 09 07:20:56 AM UTC 24 |
Oct 09 07:21:01 AM UTC 24 |
2535248635 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3787059640 |
|
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Oct 09 07:20:39 AM UTC 24 |
Oct 09 07:21:02 AM UTC 24 |
22863157868 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3718397543 |
|
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Oct 09 07:20:58 AM UTC 24 |
Oct 09 07:21:04 AM UTC 24 |
2609900305 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.949029097 |
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Oct 09 07:20:59 AM UTC 24 |
Oct 09 07:21:05 AM UTC 24 |
8446408744 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.4139730393 |
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Oct 09 07:20:56 AM UTC 24 |
Oct 09 07:21:05 AM UTC 24 |
2208976994 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.4280116042 |
|
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Oct 09 07:20:58 AM UTC 24 |
Oct 09 07:21:06 AM UTC 24 |
2620249007 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.3712950614 |
|
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Oct 09 07:20:55 AM UTC 24 |
Oct 09 07:21:10 AM UTC 24 |
2458346802 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3674377678 |
|
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Oct 09 07:20:51 AM UTC 24 |
Oct 09 07:21:10 AM UTC 24 |
9751603253 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.2324284611 |
|
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Oct 09 07:21:06 AM UTC 24 |
Oct 09 07:21:11 AM UTC 24 |
2050086171 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2347581436 |
|
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Oct 09 07:21:06 AM UTC 24 |
Oct 09 07:21:11 AM UTC 24 |
2124730326 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.3228247871 |
|
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Oct 09 07:21:00 AM UTC 24 |
Oct 09 07:21:12 AM UTC 24 |
3535582311 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1814625444 |
|
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Oct 09 07:20:59 AM UTC 24 |
Oct 09 07:21:13 AM UTC 24 |
3057224684 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.2894324987 |
|
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Oct 09 07:21:12 AM UTC 24 |
Oct 09 07:21:14 AM UTC 24 |
2793439304 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1843052904 |
|
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Oct 09 07:18:55 AM UTC 24 |
Oct 09 07:21:15 AM UTC 24 |
45343792062 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1236894365 |
|
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Oct 09 07:21:03 AM UTC 24 |
Oct 09 07:21:16 AM UTC 24 |
3143499163 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2042282836 |
|
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Oct 09 07:20:18 AM UTC 24 |
Oct 09 07:21:16 AM UTC 24 |
71721707620 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1502689988 |
|
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Oct 09 07:21:12 AM UTC 24 |
Oct 09 07:21:17 AM UTC 24 |
2531443264 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3717797831 |
|
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Oct 09 07:21:07 AM UTC 24 |
Oct 09 07:21:20 AM UTC 24 |
2469146940 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.4129100281 |
|
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Oct 09 07:21:16 AM UTC 24 |
Oct 09 07:21:20 AM UTC 24 |
5291054060 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2516478528 |
|
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Oct 09 07:21:13 AM UTC 24 |
Oct 09 07:21:21 AM UTC 24 |
3533778927 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2613966877 |
|
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Oct 09 07:21:11 AM UTC 24 |
Oct 09 07:21:22 AM UTC 24 |
2115607590 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.890531777 |
|
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Oct 09 07:18:18 AM UTC 24 |
Oct 09 07:21:24 AM UTC 24 |
59805088416 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.412208747 |
|
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Oct 09 07:18:42 AM UTC 24 |
Oct 09 07:21:28 AM UTC 24 |
102608526917 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2704111031 |
|
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Oct 09 07:21:18 AM UTC 24 |
Oct 09 07:21:28 AM UTC 24 |
13742126599 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.1070542679 |
|
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Oct 09 07:21:22 AM UTC 24 |
Oct 09 07:21:30 AM UTC 24 |
2117559568 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1792381179 |
|
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Oct 09 07:21:21 AM UTC 24 |
Oct 09 07:21:31 AM UTC 24 |
2013614454 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2627954651 |
|
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Oct 09 07:21:12 AM UTC 24 |
Oct 09 07:21:31 AM UTC 24 |
3607882832 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3865921572 |
|
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Oct 09 07:21:14 AM UTC 24 |
Oct 09 07:21:31 AM UTC 24 |
852573463503 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1775255812 |
|
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Oct 09 07:17:07 AM UTC 24 |
Oct 09 07:21:33 AM UTC 24 |
212733222417 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.3097064725 |
|
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Oct 09 07:21:28 AM UTC 24 |
Oct 09 07:21:34 AM UTC 24 |
3511799740 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.1589480282 |
|
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Oct 09 07:21:18 AM UTC 24 |
Oct 09 07:21:34 AM UTC 24 |
3568819353 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1979696120 |
|
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Oct 09 07:21:28 AM UTC 24 |
Oct 09 07:21:34 AM UTC 24 |
2620111524 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.3838971434 |
|
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Oct 09 07:21:23 AM UTC 24 |
Oct 09 07:21:34 AM UTC 24 |
2141082084 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3180755421 |
|
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Oct 09 07:16:45 AM UTC 24 |
Oct 09 07:21:35 AM UTC 24 |
108933808454 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1274673375 |
|
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Oct 09 07:21:32 AM UTC 24 |
Oct 09 07:21:35 AM UTC 24 |
2848272578 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2231796794 |
|
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Oct 09 07:20:51 AM UTC 24 |
Oct 09 07:21:35 AM UTC 24 |
12510036655 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.2482847896 |
|
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Oct 09 07:21:22 AM UTC 24 |
Oct 09 07:21:36 AM UTC 24 |
2483459154 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.1662441957 |
|
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Oct 09 07:21:24 AM UTC 24 |
Oct 09 07:21:37 AM UTC 24 |
2508769159 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.861169734 |
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Oct 09 07:20:59 AM UTC 24 |
Oct 09 07:21:38 AM UTC 24 |
41437222504 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3939296385 |
|
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Oct 09 07:20:30 AM UTC 24 |
Oct 09 07:21:41 AM UTC 24 |
104698509563 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.2779211756 |
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Oct 09 07:21:37 AM UTC 24 |
Oct 09 07:21:41 AM UTC 24 |
2223296227 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2816476496 |
|
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Oct 09 07:21:32 AM UTC 24 |
Oct 09 07:21:42 AM UTC 24 |
5519965389 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.851864956 |
|
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Oct 09 07:18:44 AM UTC 24 |
Oct 09 07:21:44 AM UTC 24 |
73150275409 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1872261541 |
|
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Oct 09 07:20:51 AM UTC 24 |
Oct 09 07:21:44 AM UTC 24 |
23839160099 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3797247946 |
|
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Oct 09 07:21:38 AM UTC 24 |
Oct 09 07:21:44 AM UTC 24 |
3069756324 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.1160378340 |
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Oct 09 07:21:35 AM UTC 24 |
Oct 09 07:21:45 AM UTC 24 |
2109827199 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.3478115473 |
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Oct 09 07:21:37 AM UTC 24 |
Oct 09 07:21:45 AM UTC 24 |
2513171761 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.2441672955 |
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Oct 09 07:21:35 AM UTC 24 |
Oct 09 07:21:46 AM UTC 24 |
2013277862 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1481258736 |
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Oct 09 07:21:41 AM UTC 24 |
Oct 09 07:21:46 AM UTC 24 |
7033502214 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.428717368 |
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Oct 09 07:21:30 AM UTC 24 |
Oct 09 07:21:47 AM UTC 24 |
3612365306 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3469488236 |
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Oct 09 07:21:37 AM UTC 24 |
Oct 09 07:21:49 AM UTC 24 |
2611780782 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.1833040517 |
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Oct 09 07:21:43 AM UTC 24 |
Oct 09 07:21:49 AM UTC 24 |
3917864729 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.970307071 |
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Oct 09 07:21:35 AM UTC 24 |
Oct 09 07:21:49 AM UTC 24 |
4296259052 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.1088339647 |
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Oct 09 07:21:47 AM UTC 24 |
Oct 09 07:21:50 AM UTC 24 |
2125160243 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.1925380941 |
|
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Oct 09 07:21:35 AM UTC 24 |
Oct 09 07:21:51 AM UTC 24 |
2471292173 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2398638146 |
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Oct 09 07:20:29 AM UTC 24 |
Oct 09 07:21:51 AM UTC 24 |
24830494601 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.2794408984 |
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Oct 09 07:21:48 AM UTC 24 |
Oct 09 07:21:51 AM UTC 24 |
2080090398 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.2539700852 |
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Oct 09 07:21:46 AM UTC 24 |
Oct 09 07:21:51 AM UTC 24 |
2018233910 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.863813401 |
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Oct 09 07:21:49 AM UTC 24 |
Oct 09 07:21:52 AM UTC 24 |
2739484575 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2486774898 |
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Oct 09 07:21:56 AM UTC 24 |
Oct 09 07:22:00 AM UTC 24 |
2641521550 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.456578341 |
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Oct 09 07:19:28 AM UTC 24 |
Oct 09 07:21:52 AM UTC 24 |
152644621396 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.801580830 |
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Oct 09 07:21:48 AM UTC 24 |
Oct 09 07:21:53 AM UTC 24 |
2530869530 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.539715042 |
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Oct 09 07:21:39 AM UTC 24 |
Oct 09 07:21:53 AM UTC 24 |
3218211343 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1817331236 |
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Oct 09 07:21:50 AM UTC 24 |
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3558538091 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.445257601 |
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Oct 09 07:21:53 AM UTC 24 |
Oct 09 07:21:55 AM UTC 24 |
3539115533 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3839377296 |
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Oct 09 07:21:54 AM UTC 24 |
Oct 09 07:21:58 AM UTC 24 |
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| T193 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1632737943 |
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Oct 09 07:21:45 AM UTC 24 |
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15868091685 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.1753036629 |
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Oct 09 07:21:53 AM UTC 24 |
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7060910366 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.1931031564 |
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Oct 09 07:21:47 AM UTC 24 |
Oct 09 07:21:59 AM UTC 24 |
2465832943 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.1297216465 |
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Oct 09 07:21:35 AM UTC 24 |
Oct 09 07:22:00 AM UTC 24 |
12513537463 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.2175895845 |
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Oct 09 07:21:55 AM UTC 24 |
Oct 09 07:22:03 AM UTC 24 |
2510321177 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1034796736 |
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Oct 09 07:22:01 AM UTC 24 |
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2889220228 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.4221321028 |
|
|
Oct 09 07:22:00 AM UTC 24 |
Oct 09 07:22:04 AM UTC 24 |
3824737740 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2159001709 |
|
|
Oct 09 07:21:16 AM UTC 24 |
Oct 09 07:22:04 AM UTC 24 |
24841631622 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.3278062666 |
|
|
Oct 09 07:21:54 AM UTC 24 |
Oct 09 07:22:05 AM UTC 24 |
2113439175 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.466768805 |
|
|
Oct 09 07:22:00 AM UTC 24 |
Oct 09 07:22:05 AM UTC 24 |
5467793541 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3732829138 |
|
|
Oct 09 07:21:50 AM UTC 24 |
Oct 09 07:22:06 AM UTC 24 |
3428775795 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2171327636 |
|
|
Oct 09 07:19:28 AM UTC 24 |
Oct 09 07:23:06 AM UTC 24 |
135544246275 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.1191929907 |
|
|
Oct 09 07:20:29 AM UTC 24 |
Oct 09 07:22:07 AM UTC 24 |
155505401435 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.1561480576 |
|
|
Oct 09 07:21:54 AM UTC 24 |
Oct 09 07:22:07 AM UTC 24 |
2128981875 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.408067919 |
|
|
Oct 09 07:21:53 AM UTC 24 |
Oct 09 07:22:08 AM UTC 24 |
22401271043 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.4142203652 |
|
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Oct 09 07:22:06 AM UTC 24 |
Oct 09 07:22:09 AM UTC 24 |
2506897121 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.944852067 |
|
|
Oct 09 07:22:06 AM UTC 24 |
Oct 09 07:22:09 AM UTC 24 |
2260983294 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.2367382055 |
|
|
Oct 09 07:22:04 AM UTC 24 |
Oct 09 07:22:09 AM UTC 24 |
2035274862 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.54029027 |
|
|
Oct 09 07:22:06 AM UTC 24 |
Oct 09 07:22:11 AM UTC 24 |
2527478452 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1302216705 |
|
|
Oct 09 07:22:07 AM UTC 24 |
Oct 09 07:22:12 AM UTC 24 |
2635708892 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3631407251 |
|
|
Oct 09 07:22:08 AM UTC 24 |
Oct 09 07:22:12 AM UTC 24 |
3142143057 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.2450549726 |
|
|
Oct 09 07:22:13 AM UTC 24 |
Oct 09 07:22:16 AM UTC 24 |
2494064634 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.2104559069 |
|
|
Oct 09 07:22:06 AM UTC 24 |
Oct 09 07:22:19 AM UTC 24 |
2112635441 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2698019679 |
|
|
Oct 09 07:22:08 AM UTC 24 |
Oct 09 07:22:19 AM UTC 24 |
3534215193 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1530255963 |
|
|
Oct 09 07:22:03 AM UTC 24 |
Oct 09 07:22:19 AM UTC 24 |
1246365405683 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.394829633 |
|
|
Oct 09 07:22:09 AM UTC 24 |
Oct 09 07:22:19 AM UTC 24 |
3900575917 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1063421380 |
|
|
Oct 09 07:22:08 AM UTC 24 |
Oct 09 07:22:21 AM UTC 24 |
5993632266 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.3356009701 |
|
|
Oct 09 07:14:24 AM UTC 24 |
Oct 09 07:22:22 AM UTC 24 |
121581679857 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1778404838 |
|
|
Oct 09 07:22:12 AM UTC 24 |
Oct 09 07:22:23 AM UTC 24 |
2009555822 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3104169294 |
|
|
Oct 09 07:22:17 AM UTC 24 |
Oct 09 07:22:24 AM UTC 24 |
2077790027 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2488437733 |
|
|
Oct 09 07:22:09 AM UTC 24 |
Oct 09 07:22:24 AM UTC 24 |
10861198409 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.3076987440 |
|
|
Oct 09 07:22:13 AM UTC 24 |
Oct 09 07:22:24 AM UTC 24 |
2110312836 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.2207307735 |
|
|
Oct 09 07:22:50 AM UTC 24 |
Oct 09 07:23:04 AM UTC 24 |
2449517532 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.3937261024 |
|
|
Oct 09 07:22:20 AM UTC 24 |
Oct 09 07:22:25 AM UTC 24 |
2535960442 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1705326838 |
|
|
Oct 09 07:22:20 AM UTC 24 |
Oct 09 07:22:26 AM UTC 24 |
2629398059 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4122969647 |
|
|
Oct 09 07:22:22 AM UTC 24 |
Oct 09 07:22:30 AM UTC 24 |
8807019756 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3248566287 |
|
|
Oct 09 07:22:20 AM UTC 24 |
Oct 09 07:22:30 AM UTC 24 |
2988654353 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.184759564 |
|
|
Oct 09 07:20:00 AM UTC 24 |
Oct 09 07:22:31 AM UTC 24 |
143408176648 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.4270404520 |
|
|
Oct 09 07:20:38 AM UTC 24 |
Oct 09 07:22:31 AM UTC 24 |
70573415014 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.3274360199 |
|
|
Oct 09 07:22:24 AM UTC 24 |
Oct 09 07:22:32 AM UTC 24 |
4545563280 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.3086826463 |
|
|
Oct 09 07:22:28 AM UTC 24 |
Oct 09 07:22:32 AM UTC 24 |
2477944937 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.50897529 |
|
|
Oct 09 07:22:26 AM UTC 24 |
Oct 09 07:22:33 AM UTC 24 |
2116616410 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.156400089 |
|
|
Oct 09 07:22:26 AM UTC 24 |
Oct 09 07:22:33 AM UTC 24 |
2020894439 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.4250145973 |
|
|
Oct 09 07:22:04 AM UTC 24 |
Oct 09 07:22:34 AM UTC 24 |
9677427574 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.542735815 |
|
|
Oct 09 07:22:32 AM UTC 24 |
Oct 09 07:22:36 AM UTC 24 |
2680238109 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1469719809 |
|
|
Oct 09 07:18:40 AM UTC 24 |
Oct 09 07:22:37 AM UTC 24 |
230809193005 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.550478042 |
|
|
Oct 09 07:22:36 AM UTC 24 |
Oct 09 07:22:38 AM UTC 24 |
2720873015 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1436906560 |
|
|
Oct 09 07:22:32 AM UTC 24 |
Oct 09 07:22:39 AM UTC 24 |
2563437952 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2814114407 |
|
|
Oct 09 07:22:20 AM UTC 24 |
Oct 09 07:22:39 AM UTC 24 |
3704414897 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1397148568 |
|
|
Oct 09 07:22:34 AM UTC 24 |
Oct 09 07:22:39 AM UTC 24 |
9342915210 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.513274145 |
|
|
Oct 09 07:22:31 AM UTC 24 |
Oct 09 07:22:40 AM UTC 24 |
2522254494 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.479355095 |
|
|
Oct 09 07:21:32 AM UTC 24 |
Oct 09 07:22:40 AM UTC 24 |
43471132755 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3856187376 |
|
|
Oct 09 07:22:34 AM UTC 24 |
Oct 09 07:22:41 AM UTC 24 |
3530400044 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3388665038 |
|
|
Oct 09 07:22:54 AM UTC 24 |
Oct 09 07:23:05 AM UTC 24 |
3313264964 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.4014592348 |
|
|
Oct 09 07:22:40 AM UTC 24 |
Oct 09 07:22:43 AM UTC 24 |
2526048461 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2209237887 |
|
|
Oct 09 07:22:26 AM UTC 24 |
Oct 09 07:22:43 AM UTC 24 |
4569103795 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.298012076 |
|
|
Oct 09 07:21:42 AM UTC 24 |
Oct 09 07:22:43 AM UTC 24 |
64576230873 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3610446157 |
|
|
Oct 09 07:22:31 AM UTC 24 |
Oct 09 07:22:43 AM UTC 24 |
2125945863 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1025759738 |
|
|
Oct 09 07:22:40 AM UTC 24 |
Oct 09 07:22:45 AM UTC 24 |
2132326324 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2513784230 |
|
|
Oct 09 07:22:41 AM UTC 24 |
Oct 09 07:22:45 AM UTC 24 |
2625491122 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.1586622888 |
|
|
Oct 09 07:20:41 AM UTC 24 |
Oct 09 07:22:46 AM UTC 24 |
198554532451 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.915140887 |
|
|
Oct 09 07:22:38 AM UTC 24 |
Oct 09 07:22:47 AM UTC 24 |
21435320426 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.994325908 |
|
|
Oct 09 07:22:26 AM UTC 24 |
Oct 09 07:22:49 AM UTC 24 |
12646800615 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1682061431 |
|
|
Oct 09 07:22:45 AM UTC 24 |
Oct 09 07:22:50 AM UTC 24 |
5547588637 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3210981851 |
|
|
Oct 09 07:22:40 AM UTC 24 |
Oct 09 07:22:51 AM UTC 24 |
2152773090 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1290075612 |
|
|
Oct 09 07:22:40 AM UTC 24 |
Oct 09 07:22:52 AM UTC 24 |
2011372735 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.4288054186 |
|
|
Oct 09 07:22:48 AM UTC 24 |
Oct 09 07:22:53 AM UTC 24 |
2133664937 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.3543808257 |
|
|
Oct 09 07:22:45 AM UTC 24 |
Oct 09 07:22:53 AM UTC 24 |
3187960988 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3784245457 |
|
|
Oct 09 07:22:50 AM UTC 24 |
Oct 09 07:22:54 AM UTC 24 |
2272293893 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3539483790 |
|
|
Oct 09 07:22:53 AM UTC 24 |
Oct 09 07:22:58 AM UTC 24 |
2632204654 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1350125382 |
|
|
Oct 09 07:22:41 AM UTC 24 |
Oct 09 07:22:59 AM UTC 24 |
2611791014 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3730589046 |
|
|
Oct 09 07:22:48 AM UTC 24 |
Oct 09 07:22:59 AM UTC 24 |
2013550637 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3837723436 |
|
|
Oct 09 07:21:46 AM UTC 24 |
Oct 09 07:23:00 AM UTC 24 |
230673114220 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3555441565 |
|
|
Oct 09 07:22:56 AM UTC 24 |
Oct 09 07:23:01 AM UTC 24 |
6838759793 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.725260893 |
|
|
Oct 09 07:22:43 AM UTC 24 |
Oct 09 07:23:02 AM UTC 24 |
3795980620 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1295489921 |
|
|
Oct 09 07:22:46 AM UTC 24 |
Oct 09 07:23:02 AM UTC 24 |
2716429717 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.84579590 |
|
|
Oct 09 07:22:53 AM UTC 24 |
Oct 09 07:23:07 AM UTC 24 |
2511215365 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4264292446 |
|
|
Oct 09 07:22:54 AM UTC 24 |
Oct 09 07:23:08 AM UTC 24 |
3005410710 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2600193205 |
|
|
Oct 09 07:23:03 AM UTC 24 |
Oct 09 07:23:08 AM UTC 24 |
2135412860 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3063848256 |
|
|
Oct 09 07:23:05 AM UTC 24 |
Oct 09 07:23:09 AM UTC 24 |
2473759024 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.1294558275 |
|
|
Oct 09 07:23:06 AM UTC 24 |
Oct 09 07:23:10 AM UTC 24 |
2049927773 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.4172402168 |
|
|
Oct 09 07:23:03 AM UTC 24 |
Oct 09 07:23:11 AM UTC 24 |
2016662045 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.1834462516 |
|
|
Oct 09 07:22:45 AM UTC 24 |
Oct 09 07:23:13 AM UTC 24 |
66388473284 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1427116208 |
|
|
Oct 09 07:23:10 AM UTC 24 |
Oct 09 07:23:16 AM UTC 24 |
7123220493 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.4250494252 |
|
|
Oct 09 07:22:11 AM UTC 24 |
Oct 09 07:23:16 AM UTC 24 |
76265819987 ps |
| T750 |
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Oct 09 07:23:09 AM UTC 24 |
Oct 09 07:23:18 AM UTC 24 |
5709959843 ps |
| T751 |
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Oct 09 07:23:07 AM UTC 24 |
Oct 09 07:23:18 AM UTC 24 |
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Oct 09 07:23:09 AM UTC 24 |
Oct 09 07:23:18 AM UTC 24 |
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Oct 09 07:23:00 AM UTC 24 |
Oct 09 07:23:21 AM UTC 24 |
3122858884 ps |
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Oct 09 07:23:02 AM UTC 24 |
Oct 09 07:23:21 AM UTC 24 |
9915593306 ps |
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Oct 09 07:21:51 AM UTC 24 |
Oct 09 07:23:21 AM UTC 24 |
63321929357 ps |
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Oct 09 07:23:13 AM UTC 24 |
Oct 09 07:23:23 AM UTC 24 |
3079820683 ps |
| T176 |
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Oct 09 07:22:38 AM UTC 24 |
Oct 09 07:23:24 AM UTC 24 |
856183062635 ps |
| T756 |
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Oct 09 07:23:09 AM UTC 24 |
Oct 09 07:23:25 AM UTC 24 |
3105661657 ps |
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/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.365732862 |
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Oct 09 07:19:05 AM UTC 24 |
Oct 09 07:23:25 AM UTC 24 |
2946727244989 ps |
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Oct 09 07:23:02 AM UTC 24 |
Oct 09 07:23:25 AM UTC 24 |
5457375781 ps |
| T757 |
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Oct 09 07:23:19 AM UTC 24 |
Oct 09 07:23:28 AM UTC 24 |
2014060547 ps |
| T758 |
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Oct 09 07:23:26 AM UTC 24 |
Oct 09 07:23:34 AM UTC 24 |
25650384556 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.985972277 |
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Oct 09 07:23:17 AM UTC 24 |
Oct 09 07:23:38 AM UTC 24 |
6296567675 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1246356408 |
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Oct 09 07:19:51 AM UTC 24 |
Oct 09 07:23:40 AM UTC 24 |
77331950546 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.4174663322 |
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Oct 09 07:23:18 AM UTC 24 |
Oct 09 07:23:44 AM UTC 24 |
7120426856 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.647249906 |
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Oct 09 07:23:22 AM UTC 24 |
Oct 09 07:23:46 AM UTC 24 |
28349328964 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1498786359 |
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Oct 09 07:23:14 AM UTC 24 |
Oct 09 07:23:48 AM UTC 24 |
51112128542 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3302639490 |
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Oct 09 07:23:22 AM UTC 24 |
Oct 09 07:23:50 AM UTC 24 |
22601888809 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.4253839531 |
|
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Oct 09 07:17:20 AM UTC 24 |
Oct 09 07:23:51 AM UTC 24 |
151417838539 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1660458059 |
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Oct 09 07:22:46 AM UTC 24 |
Oct 09 07:23:55 AM UTC 24 |
16041307644 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2878438025 |
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Oct 09 07:23:00 AM UTC 24 |
Oct 09 07:23:56 AM UTC 24 |
27090160638 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.486530967 |
|
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Oct 09 07:22:59 AM UTC 24 |
Oct 09 07:23:57 AM UTC 24 |
80481257312 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3819167458 |
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Oct 09 07:19:08 AM UTC 24 |
Oct 09 07:24:02 AM UTC 24 |
110938789277 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1975442730 |
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Oct 09 07:23:24 AM UTC 24 |
Oct 09 07:24:04 AM UTC 24 |
51194455815 ps |
| T763 |
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Oct 09 07:23:47 AM UTC 24 |
Oct 09 07:24:07 AM UTC 24 |
25602665015 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.1100517283 |
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Oct 09 07:20:07 AM UTC 24 |
Oct 09 07:24:16 AM UTC 24 |
88120620676 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3926504050 |
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Oct 09 07:23:20 AM UTC 24 |
Oct 09 07:24:20 AM UTC 24 |
83598168713 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2131307610 |
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Oct 09 07:23:26 AM UTC 24 |
Oct 09 07:24:26 AM UTC 24 |
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| T766 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.894155930 |
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Oct 09 07:17:55 AM UTC 24 |
Oct 09 07:24:26 AM UTC 24 |
147830562668 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4257181152 |
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Oct 09 07:22:01 AM UTC 24 |
Oct 09 07:24:37 AM UTC 24 |
55747180478 ps |
| T280 |
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Oct 09 07:23:20 AM UTC 24 |
Oct 09 07:24:38 AM UTC 24 |
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| T440 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.333616649 |
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Oct 09 07:23:41 AM UTC 24 |
Oct 09 07:24:38 AM UTC 24 |
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| T429 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2964342390 |
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Oct 09 07:22:01 AM UTC 24 |
Oct 09 07:24:41 AM UTC 24 |
40732875637 ps |
| T768 |
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Oct 09 07:23:39 AM UTC 24 |
Oct 09 07:24:44 AM UTC 24 |
80547847648 ps |
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/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.194045601 |
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Oct 09 07:21:51 AM UTC 24 |
Oct 09 07:24:45 AM UTC 24 |
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Oct 09 07:23:29 AM UTC 24 |
Oct 09 07:24:47 AM UTC 24 |
35643199710 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.4169622421 |
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Oct 09 07:23:35 AM UTC 24 |
Oct 09 07:24:50 AM UTC 24 |
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| T311 |
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Oct 09 07:20:45 AM UTC 24 |
Oct 09 07:24:52 AM UTC 24 |
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| T425 |
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Oct 09 07:23:46 AM UTC 24 |
Oct 09 07:24:55 AM UTC 24 |
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Oct 09 07:24:27 AM UTC 24 |
Oct 09 07:24:56 AM UTC 24 |
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Oct 09 07:19:37 AM UTC 24 |
Oct 09 07:24:56 AM UTC 24 |
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Oct 09 07:24:17 AM UTC 24 |
Oct 09 07:24:59 AM UTC 24 |
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Oct 09 07:23:51 AM UTC 24 |
Oct 09 07:25:01 AM UTC 24 |
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Oct 09 07:23:58 AM UTC 24 |
Oct 09 07:25:01 AM UTC 24 |
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| T441 |
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Oct 09 07:23:57 AM UTC 24 |
Oct 09 07:25:03 AM UTC 24 |
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| T312 |
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Oct 09 07:21:15 AM UTC 24 |
Oct 09 07:25:11 AM UTC 24 |
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Oct 09 07:24:56 AM UTC 24 |
Oct 09 07:25:12 AM UTC 24 |
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Oct 09 07:24:45 AM UTC 24 |
Oct 09 07:25:12 AM UTC 24 |
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Oct 09 07:24:43 AM UTC 24 |
Oct 09 07:25:15 AM UTC 24 |
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Oct 09 07:20:28 AM UTC 24 |
Oct 09 07:25:24 AM UTC 24 |
219012817853 ps |
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Oct 09 07:25:02 AM UTC 24 |
Oct 09 07:25:28 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2292839346 |
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Oct 09 07:18:17 AM UTC 24 |
Oct 09 07:25:29 AM UTC 24 |
156172397173 ps |
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Oct 09 07:17:45 AM UTC 24 |
Oct 09 07:25:29 AM UTC 24 |
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Oct 09 07:21:05 AM UTC 24 |
Oct 09 07:25:33 AM UTC 24 |
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Oct 09 07:24:08 AM UTC 24 |
Oct 09 07:25:37 AM UTC 24 |
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Oct 09 07:24:52 AM UTC 24 |
Oct 09 07:25:37 AM UTC 24 |
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Oct 09 07:24:39 AM UTC 24 |
Oct 09 07:25:43 AM UTC 24 |
31655614259 ps |
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Oct 09 07:24:05 AM UTC 24 |
Oct 09 07:25:44 AM UTC 24 |
116124211987 ps |
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Oct 09 07:25:03 AM UTC 24 |
Oct 09 07:25:46 AM UTC 24 |
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Oct 09 07:20:17 AM UTC 24 |
Oct 09 07:25:46 AM UTC 24 |
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Oct 09 07:20:08 AM UTC 24 |
Oct 09 07:25:46 AM UTC 24 |
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Oct 09 07:23:24 AM UTC 24 |
Oct 09 07:25:50 AM UTC 24 |
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Oct 09 07:22:08 AM UTC 24 |
Oct 09 07:25:52 AM UTC 24 |
73275025701 ps |
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Oct 09 07:24:00 AM UTC 24 |
Oct 09 07:25:59 AM UTC 24 |
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Oct 09 07:24:38 AM UTC 24 |
Oct 09 07:26:00 AM UTC 24 |
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Oct 09 07:24:39 AM UTC 24 |
Oct 09 07:26:05 AM UTC 24 |
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Oct 09 07:23:10 AM UTC 24 |
Oct 09 07:26:15 AM UTC 24 |
59031022923 ps |
| T783 |
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Oct 09 07:23:23 AM UTC 24 |
Oct 09 07:26:28 AM UTC 24 |
64880408587 ps |
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Oct 09 07:23:26 AM UTC 24 |
Oct 09 07:26:30 AM UTC 24 |
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Oct 09 07:21:44 AM UTC 24 |
Oct 09 07:26:35 AM UTC 24 |
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Oct 09 07:24:58 AM UTC 24 |
Oct 09 07:26:36 AM UTC 24 |
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Oct 09 07:24:46 AM UTC 24 |
Oct 09 07:26:45 AM UTC 24 |
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Oct 09 07:23:52 AM UTC 24 |
Oct 09 07:26:50 AM UTC 24 |
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Oct 09 07:22:35 AM UTC 24 |
Oct 09 07:26:58 AM UTC 24 |
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Oct 09 07:24:27 AM UTC 24 |
Oct 09 07:27:04 AM UTC 24 |
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Oct 09 07:24:57 AM UTC 24 |
Oct 09 07:27:15 AM UTC 24 |
107314298474 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1209818852 |
|
|
Oct 09 07:22:24 AM UTC 24 |
Oct 09 07:27:20 AM UTC 24 |
99094057767 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.89283688 |
|
|
Oct 09 07:25:00 AM UTC 24 |
Oct 09 07:27:24 AM UTC 24 |
56854253429 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2126316754 |
|
|
Oct 09 07:22:09 AM UTC 24 |
Oct 09 07:27:46 AM UTC 24 |
118164102758 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4043112539 |
|
|
Oct 09 07:25:02 AM UTC 24 |
Oct 09 07:27:59 AM UTC 24 |
65026441338 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2718682409 |
|
|
Oct 09 07:24:48 AM UTC 24 |
Oct 09 07:28:03 AM UTC 24 |
79645830871 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2344465669 |
|
|
Oct 09 07:17:17 AM UTC 24 |
Oct 09 07:28:07 AM UTC 24 |
210793518805 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.23407987 |
|
|
Oct 09 07:22:24 AM UTC 24 |
Oct 09 07:28:12 AM UTC 24 |
136389171682 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1404453938 |
|
|
Oct 09 07:20:10 AM UTC 24 |
Oct 09 07:28:15 AM UTC 24 |
163588295995 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.3499126217 |
|
|
Oct 09 07:16:46 AM UTC 24 |
Oct 09 07:28:15 AM UTC 24 |
1584295210891 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2228086091 |
|
|
Oct 09 07:24:44 AM UTC 24 |
Oct 09 07:28:47 AM UTC 24 |
78933384432 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2087723499 |
|
|
Oct 09 07:23:49 AM UTC 24 |
Oct 09 07:28:57 AM UTC 24 |
186252194749 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3298849442 |
|
|
Oct 09 07:22:45 AM UTC 24 |
Oct 09 07:29:13 AM UTC 24 |
151635767043 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.15973675 |
|
|
Oct 09 07:23:55 AM UTC 24 |
Oct 09 07:30:22 AM UTC 24 |
138948640386 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2414735867 |
|
|
Oct 09 07:24:51 AM UTC 24 |
Oct 09 07:30:43 AM UTC 24 |
141256818701 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_10_08/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3300736993 |
|
|
Oct 09 07:22:45 AM UTC 24 |
Oct 09 07:35:18 AM UTC 24 |
240603532394 ps |