Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1842

1

T35

2

T60

12

T41

18

auto[1]

524

1

T35

2

T60

2

T41

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1772

1

T60

6

T41

11

T59

2

auto[1]

594

1

T35

4

T60

8

T41

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T35

2

T60

8

T41

8

auto[1]

674

1

T35

2

T60

6

T41

11

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1785

1

T35

2

T60

8

T41

10

auto[1]

581

1

T35

2

T60

6

T41

9

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2137

1

T35

4

T60

14

T41

19

auto[1]

229

1

T43

12

T63

3

T240

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2262

1

T35

4

T60

14

T41

19

auto[1]

104

1

T63

2

T44

1

T240

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2195

1

T35

4

T60

14

T41

19

auto[1]

171

1

T43

4

T63

1

T241

9

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2189

1

T35

4

T60

14

T41

19

auto[1]

177

1

T61

1

T47

5

T241

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2099

1

T35

4

T60

14

T41

19

auto[1]

267

1

T61

2

T63

2

T245

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1827

1

T60

10

T41

18

T42

10

auto[1]

539

1

T35

4

T60

4

T41

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	905	1			T35	4		T60	14		T41	19
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	92	1			T43	8		T63	3		T47	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	78	1			T61	2		T246	2		T368	5
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	30	1			T245	3		T381	2		T382	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	33	1			T61	1		T369	3		T374	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T247	4		T383	1		T377	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	42	1			T384	5		T385	8		T386	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	21	1			T241	8		T384	4		T387	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	53	1			T63	1		T112	4		T364	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	17	1			T43	4		T367	1		T385	8
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	39	1			T241	9		T387	1		T388	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	4	1			T389	1		T390	3		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	24	1			T372	1		T378	9		T391	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T392	1		T393	2		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T247	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	31	1			T44	1		T112	5		T247	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	14	1			T394	1		T380	8		T377	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	8	1			T63	2		T364	1		T372	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	13	1			T47	5		T379	7		T387	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T379	3		T395	1		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	2	1			T396	1		T386	1		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T380	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T385	5		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T378	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

136

1

T47

5

T247

2

T366

11

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

80

1

T108

8

T112

4

T277

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

38

1

T108

1

T61

1

T369

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

161

1

T47

4

T254

6

T248

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T61

2

T270

5

T361

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T46

5

T366

5

T234

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T59

2

T44

1

T361

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

107

1

T41

10

T45

6

T277

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

88

1

T248

5

T364

1

T231

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T63

3

T312

6

T361

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T46

1

T254

2

T247

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T42

3

T261

7

T112

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T60

2

T63

2

T312

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T60

4

T262

8

T236

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T41

1

T277

3

T389

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

65

1

T60

8

T46

10

T245

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

42

1

T241

9

T248

5

T270

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

85

1

T63

1

T246

3

T247

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

12

1

T270

4

T179

1

T397

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T41

8

T42

7

T364

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T398

6

T399

1

T373

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T43

4

T45

5

T263

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T35

2

T361

1

T366

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T43

8

T45

3

T46

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

39

1

T249

4

T255

3

T120

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T35

2

T247

4

T385

11

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T42

2

T400

2

T375

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

31

1

T261

5

T368

3

T401

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T312

2

T179

1

T363

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

24

1

T241

8

T360

1

T120

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T397

2

T402

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded