Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	33.33	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_invert_ctl_cg_(1)	0.00	1	100	1	64	64
sysrst_ctrl_key_invert_ctl_cg_(2)	0.00	1	100	1	64	64
sysrst_ctrl_key_invert_ctl_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	48	0	0.00
Crosses	44	44	0	0.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	2	0	0.00	100	1	1	2
cfg.vif.bat_disable	2	2	0	0.00	100	1	1	2
cfg.vif.key0_in	2	2	0	0.00	100	1	1	2
cfg.vif.key0_out	2	2	0	0.00	100	1	1	2
cfg.vif.key1_in	2	2	0	0.00	100	1	1	2
cfg.vif.key1_out	2	2	0	0.00	100	1	1	2
cfg.vif.key2_in	2	2	0	0.00	100	1	1	2
cfg.vif.key2_out	2	2	0	0.00	100	1	1	2
cfg.vif.lid_open	2	2	0	0.00	100	1	1	2
cfg.vif.pwrb_in	2	2	0	0.00	100	1	1	2
cfg.vif.pwrb_out	2	2	0	0.00	100	1	1	2
cfg.vif.z3_wakeup	2	2	0	0.00	100	1	1	2
cp_ac_present	2	2	0	0.00	100	1	1	2
cp_bat_disable	2	2	0	0.00	100	1	1	2
cp_key0_in	2	2	0	0.00	100	1	1	2
cp_key0_out	2	2	0	0.00	100	1	1	2
cp_key1_in	2	2	0	0.00	100	1	1	2
cp_key1_out	2	2	0	0.00	100	1	1	2
cp_key2_in	2	2	0	0.00	100	1	1	2
cp_key2_out	2	2	0	0.00	100	1	1	2
cp_lid_open	2	2	0	0.00	100	1	1	2
cp_pwrb_in	2	2	0	0.00	100	1	1	2
cp_pwrb_out	2	2	0	0.00	100	1	1	2
cp_z3_wakeup	2	2	0	0.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	4	0	0.00	100	1	1	0
key0_outXval	4	4	0	0.00	100	1	1	0
key1_inXval	4	4	0	0.00	100	1	1	0
key1_outXval	4	4	0	0.00	100	1	1	0
key2_inXval	4	4	0	0.00	100	1	1	0
key2_outXval	4	4	0	0.00	100	1	1	0
pwrb_inXval	4	4	0	0.00	100	1	1	0
pwrb_outXval	4	4	0	0.00	100	1	1	0
ac_presentXval	4	4	0	0.00	100	1	1	0
bat_disableXval	2	2	0	0.00	100	1	1	0
lid_openXval	4	4	0	0.00	100	1	1	0
z3_wakeupXval	2	2	0	0.00	100	1	1	0

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg_(2)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg_(2)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	48	0	0.00
Crosses	44	44	0	0.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg_(2)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	2	0	0.00	100	1	1	2
cfg.vif.bat_disable	2	2	0	0.00	100	1	1	2
cfg.vif.key0_in	2	2	0	0.00	100	1	1	2
cfg.vif.key0_out	2	2	0	0.00	100	1	1	2
cfg.vif.key1_in	2	2	0	0.00	100	1	1	2
cfg.vif.key1_out	2	2	0	0.00	100	1	1	2
cfg.vif.key2_in	2	2	0	0.00	100	1	1	2
cfg.vif.key2_out	2	2	0	0.00	100	1	1	2
cfg.vif.lid_open	2	2	0	0.00	100	1	1	2
cfg.vif.pwrb_in	2	2	0	0.00	100	1	1	2
cfg.vif.pwrb_out	2	2	0	0.00	100	1	1	2
cfg.vif.z3_wakeup	2	2	0	0.00	100	1	1	2
cp_ac_present	2	2	0	0.00	100	1	1	2
cp_bat_disable	2	2	0	0.00	100	1	1	2
cp_key0_in	2	2	0	0.00	100	1	1	2
cp_key0_out	2	2	0	0.00	100	1	1	2
cp_key1_in	2	2	0	0.00	100	1	1	2
cp_key1_out	2	2	0	0.00	100	1	1	2
cp_key2_in	2	2	0	0.00	100	1	1	2
cp_key2_out	2	2	0	0.00	100	1	1	2
cp_lid_open	2	2	0	0.00	100	1	1	2
cp_pwrb_in	2	2	0	0.00	100	1	1	2
cp_pwrb_out	2	2	0	0.00	100	1	1	2
cp_z3_wakeup	2	2	0	0.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg_(2)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	4	0	0.00	100	1	1	0
key0_outXval	4	4	0	0.00	100	1	1	0
key1_inXval	4	4	0	0.00	100	1	1	0
key1_outXval	4	4	0	0.00	100	1	1	0
key2_inXval	4	4	0	0.00	100	1	1	0
key2_outXval	4	4	0	0.00	100	1	1	0
pwrb_inXval	4	4	0	0.00	100	1	1	0
pwrb_outXval	4	4	0	0.00	100	1	1	0
ac_presentXval	4	4	0	0.00	100	1	1	0
bat_disableXval	2	2	0	0.00	100	1	1	0
lid_openXval	4	4	0	0.00	100	1	1	0
z3_wakeupXval	2	2	0	0.00	100	1	1	0

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.ac_present

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.bat_disable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key0_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key0_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key1_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key1_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key2_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key2_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.lid_open

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.pwrb_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.pwrb_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_ac_present

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_bat_disable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key0_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key0_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key1_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key1_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key2_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key2_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_lid_open

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_pwrb_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_pwrb_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_z3_wakeup

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key0_inXval

Uncovered bins

cp_key0_in	cfg.vif.key0_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key0_outXval

Uncovered bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key1_inXval

Uncovered bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key1_outXval

Uncovered bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key2_inXval

Uncovered bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key2_outXval

Uncovered bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for pwrb_inXval

Uncovered bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for pwrb_outXval

Uncovered bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for ac_presentXval

Uncovered bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	2	0	0.00	2
Automatically Generated Cross Bins	2	2	0	0.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Uncovered bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	0	1	1

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for lid_openXval

Uncovered bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	2	0	0.00	2
Automatically Generated Cross Bins	2	2	0	0.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Uncovered bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	0	1	1

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.ac_present

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.bat_disable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key0_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key0_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key1_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key1_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key2_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.key2_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.lid_open

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.pwrb_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.pwrb_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_ac_present

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_bat_disable

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key0_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key0_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key1_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key1_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key2_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_key2_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_lid_open

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_pwrb_in

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_pwrb_out

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_z3_wakeup

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key0_inXval

Uncovered bins

cp_key0_in	cfg.vif.key0_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key0_outXval

Uncovered bins

cp_key0_out	cfg.vif.key0_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key1_inXval

Uncovered bins

cp_key1_in	cfg.vif.key1_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key1_outXval

Uncovered bins

cp_key1_out	cfg.vif.key1_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key2_inXval

Uncovered bins

cp_key2_in	cfg.vif.key2_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for key2_outXval

Uncovered bins

cp_key2_out	cfg.vif.key2_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for pwrb_inXval

Uncovered bins

cp_pwrb_in	cfg.vif.pwrb_in	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for pwrb_outXval

Uncovered bins

cp_pwrb_out	cfg.vif.pwrb_out	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for ac_presentXval

Uncovered bins

cp_ac_present	cfg.vif.ac_present	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	2	0	0.00	2
Automatically Generated Cross Bins	2	2	0	0.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Uncovered bins

cp_bat_disable	cfg.vif.bat_disable	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	0	1	1

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	4	0	0.00	4

Automatically Generated Cross Bins for lid_openXval

Uncovered bins

cp_lid_open	cfg.vif.lid_open	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	4

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	2	0	0.00	2
Automatically Generated Cross Bins	2	2	0	0.00	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Uncovered bins

cp_z3_wakeup	cfg.vif.z3_wakeup	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	0	1	1

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T14

3

T27

10

T28

10

auto[1]

642

1

T14

17

T27

10

T28

10

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T14

9

T27

9

T28

8

auto[1]

642

1

T14

11

T27

11

T28

12

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

630

1

T14

15

T27

4

T28

8

auto[1]

630

1

T14

5

T27

16

T28

12

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

623

1

T14

10

T27

14

T28

8

auto[1]

637

1

T14

10

T27

6

T28

12

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625

1

T14

8

T27

9

T28

8

auto[1]

635

1

T14

12

T27

11

T28

12

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652

1

T14

9

T27

10

T28

15

auto[1]

608

1

T14

11

T27

10

T28

5

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T14

13

T27

10

T28

10

auto[1]

612

1

T14

7

T27

10

T28

10

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

652

1

T14

9

T27

12

T28

6

auto[1]

608

1

T14

11

T27

8

T28

14

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633

1

T14

9

T27

10

T28

10

auto[1]

627

1

T14

11

T27

10

T28

10

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664

1

T14

8

T27

9

T28

12

auto[1]

596

1

T14

12

T27

11

T28

8

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

648

1

T14

10

T27

8

T28

8

auto[1]

612

1

T14

10

T27

12

T28

12

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

643

1

T14

9

T27

9

T28

11

auto[1]

617

1

T14

11

T27

11

T28

9

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

647

1

T14

9

T27

9

T28

11

auto[1]

613

1

T14

11

T27

11

T28

9

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

618

1

T14

9

T27

9

T28

8

auto[1]

642

1

T14

11

T27

11

T28

12

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T14

6

T27

9

T28

12

auto[1]

611

1

T14

14

T27

11

T28

8

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

606

1

T14

15

T27

11

T28

10

auto[1]

654

1

T14

5

T27

9

T28

10

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

665

1

T14

12

T27

10

T28

11

auto[1]

595

1

T14

8

T27

10

T28

9

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

650

1

T14

11

T27

11

T28

12

auto[1]

610

1

T14

9

T27

9

T28

8

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

651

1

T14

12

T27

12

T28

14

auto[1]

609

1

T14

8

T27

8

T28

6

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T14

10

T27

8

T28

10

auto[1]

621

1

T14

10

T27

12

T28

10

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

610

1

T14

9

T27

8

T28

8

auto[1]

650

1

T14

11

T27

12

T28

12

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

649

1

T14

13

T27

10

T28

14

auto[1]

611

1

T14

7

T27

10

T28

6

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

631

1

T14

11

T27

9

T28

10

auto[1]

629

1

T14

9

T27

11

T28

10

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

643

1

T14

9

T27

9

T28

11

auto[1]

617

1

T14

11

T27

11

T28

9

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

316

1

T14

4

T27

2

T28

5

auto[0]

auto[1]

333

1

T14

2

T27

7

T28

7

auto[1]

auto[0]

314

1

T14

11

T27

2

T28

3

auto[1]

auto[1]

297

1

T14

3

T27

9

T28

5

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

291

1

T14

6

T27

8

T28

4

auto[0]

auto[1]

315

1

T14

9

T27

3

T28

6

auto[1]

auto[0]

332

1

T14

4

T27

6

T28

4

auto[1]

auto[1]

322

1

T14

1

T27

3

T28

6

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

315

1

T14

4

T27

2

T28

6

auto[0]

auto[1]

350

1

T14

8

T27

8

T28

5

auto[1]

auto[0]

310

1

T14

4

T27

7

T28

2

auto[1]

auto[1]

285

1

T14

4

T27

3

T28

7

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

321

1

T14

4

T27

3

T28

10

auto[0]

auto[1]

329

1

T14

7

T27

8

T28

2

auto[1]

auto[0]

331

1

T14

5

T27

7

T28

5

auto[1]

auto[1]

279

1

T14

4

T27

2

T28

3

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

334

1

T14

7

T27

5

T28

7

auto[0]

auto[1]

317

1

T14

5

T27

7

T28

7

auto[1]

auto[0]

314

1

T14

6

T27

5

T28

3

auto[1]

auto[1]

295

1

T14

2

T27

3

T28

3

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

330

1

T14

4

T27

4

T28

3

auto[0]

auto[1]

309

1

T14

6

T27

4

T28

7

auto[1]

auto[0]

322

1

T14

5

T27

8

T28

3

auto[1]

auto[1]

299

1

T14

5

T27

4

T28

7

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

340

1

T14

4

T27

5

T28

8

auto[0]

auto[1]

309

1

T14

9

T27

5

T28

6

auto[1]

auto[0]

324

1

T14

4

T27

4

T28

4

auto[1]

auto[1]

287

1

T14

3

T27

6

T28

2

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

323

1

T14

4

T27

4

T28

4

auto[0]

auto[1]

308

1

T14

7

T27

5

T28

6

auto[1]

auto[0]

325

1

T14

6

T27

4

T28

4

auto[1]

auto[1]

304

1

T14

3

T27

7

T28

6

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

326

1

T27

6

T28

6

T88

2

auto[0]

auto[1]

321

1

T14

9

T27

3

T28

5

auto[1]

auto[0]

292

1

T14

3

T27

4

T28

4

auto[1]

auto[1]

321

1

T14

8

T27

7

T28

5

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

618

1

T14

9

T27

9

T28

8

auto[1]

auto[1]

642

1

T14

11

T27

11

T28

12

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

318

1

T14

4

T27

3

T28

5

auto[0]

auto[1]

292

1

T14

5

T27

5

T28

3

auto[1]

auto[0]

315

1

T14

5

T27

7

T28

5

auto[1]

auto[1]

335

1

T14

6

T27

5

T28

7

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

643

1

T14

9

T27

9

T28

11

auto[1]

auto[1]

617

1

T14

11

T27

11

T28

9

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded