Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T4

9

T7

10

T85

12

auto[1]

671

1

T4

11

T7

9

T85

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

314

1

T4

5

T7

6

T85

4

from_0to1

319

1

T4

6

T7

5

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

669

1

T4

11

T7

12

T85

12

auto[1]

670

1

T4

9

T7

7

T85

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

641

1

T4

13

T7

11

T85

11

auto[1]

698

1

T4

7

T7

8

T85

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

37

1

T4

1

T95

2

T69

2

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T85

1

T96

1

T322

1

auto[0]

from_1to0

auto[1]

auto[0]

30

1

T331

1

T321

1

T322

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T7

1

T95

1

T96

2

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T4

2

T7

1

T85

3

auto[0]

from_0to1

auto[0]

auto[1]

30

1

T4

1

T7

2

T85

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T4

1

T7

1

T85

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T94

1

T95

1

T96

1

auto[1]

from_1to0

auto[0]

auto[0]

33

1

T4

1

T7

1

T94

1

auto[1]

from_1to0

auto[0]

auto[1]

50

1

T7

2

T94

2

T95

2

auto[1]

from_1to0

auto[1]

auto[0]

41

1

T4

1

T7

2

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

48

1

T4

2

T85

3

T94

1

auto[1]

from_0to1

auto[0]

auto[0]

51

1

T95

1

T96

1

T331

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T4

1

T94

1

T95

2

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T7

1

T96

1

T69

1

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T4

1

T94

1

T95

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670

1

T4

11

T7

12

T85

11

auto[1]

669

1

T4

9

T7

7

T85

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

322

1

T4

5

T7

5

T85

7

from_0to1

331

1

T4

6

T7

5

T85

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T4

9

T7

10

T85

10

auto[1]

681

1

T4

11

T7

9

T85

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T4

10

T7

8

T85

12

auto[1]

671

1

T4

10

T7

11

T85

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

43

1

T4

1

T7

1

T85

1

auto[0]

from_1to0

auto[0]

auto[1]

34

1

T85

1

T94

1

T96

2

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T4

1

T85

2

T96

1

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T4

2

T7

3

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T4

2

T94

1

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T4

1

T7

2

T321

3

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T4

2

T85

2

T94

1

auto[0]

from_0to1

auto[1]

auto[1]

43

1

T85

1

T95

1

T96

1

auto[1]

from_1to0

auto[0]

auto[0]

35

1

T85

1

T94

1

T69

4

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T85

1

T95

1

T96

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T7

1

T85

1

T69

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T4

1

T331

2

T321

2

auto[1]

from_0to1

auto[0]

auto[0]

43

1

T7

1

T85

1

T331

2

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T85

1

T331

1

T69

3

auto[1]

from_0to1

auto[1]

auto[0]

33

1

T7

1

T85

1

T94

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T4

1

T7

1

T85

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676

1

T4

13

T7

6

T85

11

auto[1]

663

1

T4

7

T7

13

T85

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

316

1

T4

7

T7

3

T85

5

from_0to1

321

1

T4

7

T7

4

T85

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T4

12

T7

11

T85

13

auto[1]

639

1

T4

8

T7

8

T85

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

653

1

T4

8

T7

13

T85

11

auto[1]

686

1

T4

12

T7

6

T85

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

33

1

T4

2

T85

2

T94

1

auto[0]

from_1to0

auto[0]

auto[1]

41

1

T4

1

T94

2

T95

1

auto[0]

from_1to0

auto[1]

auto[0]

41

1

T94

1

T95

2

T96

1

auto[0]

from_1to0

auto[1]

auto[1]

41

1

T4

1

T69

2

T321

1

auto[0]

from_0to1

auto[0]

auto[0]

38

1

T4

1

T7

1

T94

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T4

2

T85

1

T94

1

auto[0]

from_0to1

auto[1]

auto[0]

36

1

T4

1

T69

1

T321

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T4

2

T85

1

T94

2

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T4

2

T7

1

T85

1

auto[1]

from_1to0

auto[0]

auto[1]

46

1

T85

1

T96

1

T69

3

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T7

1

T96

1

T331

1

auto[1]

from_1to0

auto[1]

auto[1]

41

1

T4

1

T7

1

T85

1

auto[1]

from_0to1

auto[0]

auto[0]

41

1

T4

1

T7

1

T85

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T7

1

T94

1

T95

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T7

1

T331

1

T322

1

auto[1]

from_0to1

auto[1]

auto[1]

28

1

T85

1

T94

1

T95

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687

1

T4

9

T7

14

T85

11

auto[1]

652

1

T4

11

T7

5

T85

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

294

1

T4

6

T7

1

T85

5

from_0to1

299

1

T4

7

T7

2

T85

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

671

1

T4

9

T7

10

T85

16

auto[1]

668

1

T4

11

T7

9

T85

4

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

674

1

T4

6

T7

6

T85

6

auto[1]

665

1

T4

14

T7

13

T85

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

39

1

T85

1

T95

1

T69

1

auto[0]

from_1to0

auto[0]

auto[1]

40

1

T4

2

T85

2

T95

1

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T94

2

T96

3

T69

2

auto[0]

from_1to0

auto[1]

auto[1]

42

1

T4

2

T7

1

T94

1

auto[0]

from_0to1

auto[0]

auto[0]

34

1

T85

1

T95

2

T96

1

auto[0]

from_0to1

auto[0]

auto[1]

41

1

T4

1

T7

1

T85

1

auto[0]

from_0to1

auto[1]

auto[0]

38

1

T96

1

T331

1

T69

1

auto[0]

from_0to1

auto[1]

auto[1]

39

1

T4

2

T7

1

T94

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T95

1

T96

2

T331

1

auto[1]

from_1to0

auto[0]

auto[1]

25

1

T85

1

T95

1

T96

1

auto[1]

from_1to0

auto[1]

auto[0]

36

1

T4

1

T95

1

T322

2

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T4

1

T85

1

T94

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T4

1

T94

2

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

38

1

T4

1

T85

2

T69

2

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T4

2

T85

1

T95

2

auto[1]

from_0to1

auto[1]

auto[1]

23

1

T85

1

T96

1

T69

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

673

1

T4

7

T7

15

T85

5

auto[1]

666

1

T4

13

T7

4

T85

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

320

1

T4

7

T7

4

T85

6

from_0to1

328

1

T4

8

T7

4

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

664

1

T4

11

T7

11

T85

11

auto[1]

675

1

T4

9

T7

8

T85

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644

1

T4

10

T7

10

T85

10

auto[1]

695

1

T4

10

T7

9

T85

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

42

1

T4

1

T7

1

T94

2

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T4

1

T94

2

T95

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T7

1

T96

2

T69

1

auto[0]

from_1to0

auto[1]

auto[1]

48

1

T4

2

T7

1

T85

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T4

1

T7

2

T85

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T94

3

T96

1

T322

1

auto[0]

from_0to1

auto[1]

auto[0]

50

1

T4

1

T7

1

T95

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T69

1

T321

1

T432

2

auto[1]

from_1to0

auto[0]

auto[0]

39

1

T7

1

T85

2

T96

1

auto[1]

from_1to0

auto[0]

auto[1]

32

1

T4

1

T85

1

T95

1

auto[1]

from_1to0

auto[1]

auto[0]

42

1

T4

1

T85

1

T95

3

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T4

1

T85

1

T94

1

auto[1]

from_0to1

auto[0]

auto[0]

32

1

T4

2

T7

1

T85

2

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T4

2

T85

1

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T95

2

T96

1

T331

2

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T4

2

T85

1

T94

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

671

1

T4

11

T7

9

T85

7

auto[1]

668

1

T4

9

T7

10

T85

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

309

1

T4

5

T7

4

T85

4

from_0to1

318

1

T4

5

T7

5

T85

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694

1

T4

9

T7

7

T85

8

auto[1]

645

1

T4

11

T7

12

T85

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

697

1

T4

9

T7

12

T85

13

auto[1]

642

1

T4

11

T7

7

T85

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T4

2

T94

2

T95

2

auto[0]

from_1to0

auto[0]

auto[1]

35

1

T95

1

T96

1

T69

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T7

1

T85

1

T96

1

auto[0]

from_1to0

auto[1]

auto[1]

30

1

T4

2

T69

2

T322

1

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T7

1

T94

1

T331

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T4

1

T95

1

T331

1

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T4

1

T85

1

T95

1

auto[0]

from_0to1

auto[1]

auto[1]

45

1

T4

1

T7

1

T95

1

auto[1]

from_1to0

auto[0]

auto[0]

38

1

T85

1

T331

1

T168

1

auto[1]

from_1to0

auto[0]

auto[1]

32

1

T94

2

T69

2

T177

2

auto[1]

from_1to0

auto[1]

auto[0]

43

1

T4

1

T7

1

T85

1

auto[1]

from_1to0

auto[1]

auto[1]

37

1

T7

2

T85

1

T94

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T4

1

T7

1

T85

1

auto[1]

from_0to1

auto[0]

auto[1]

45

1

T85

1

T95

1

T96

2

auto[1]

from_0to1

auto[1]

auto[0]

46

1

T7

2

T94

2

T96

1

auto[1]

from_0to1

auto[1]

auto[1]

30

1

T4

1

T85

1

T96

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

693

1

T4

6

T7

11

T85

9

auto[1]

646

1

T4

14

T7

8

T85

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

304

1

T4

5

T7

4

T85

5

from_0to1

301

1

T4

5

T7

3

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

678

1

T4

10

T7

9

T85

8

auto[1]

661

1

T4

10

T7

10

T85

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

667

1

T4

11

T7

10

T85

14

auto[1]

672

1

T4

9

T7

9

T85

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T7

1

T85

1

T95

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T4

1

T95

1

T96

3

auto[0]

from_1to0

auto[1]

auto[0]

37

1

T4

1

T7

1

T85

1

auto[0]

from_1to0

auto[1]

auto[1]

50

1

T7

1

T85

1

T95

1

auto[0]

from_0to1

auto[0]

auto[0]

41

1

T85

1

T331

1

T69

1

auto[0]

from_0to1

auto[0]

auto[1]

30

1

T95

1

T69

1

T168

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T7

1

T85

1

T95

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T94

3

T96

2

T69

2

auto[1]

from_1to0

auto[0]

auto[0]

31

1

T4

2

T94

1

T168

1

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T94

1

T321

1

T322

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T7

1

T85

1

T96

1

auto[1]

from_1to0

auto[1]

auto[1]

42

1

T4

1

T85

1

T94

1

auto[1]

from_0to1

auto[0]

auto[0]

40

1

T331

2

T69

2

T432

1

auto[1]

from_0to1

auto[0]

auto[1]

32

1

T4

3

T7

2

T94

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T4

1

T85

3

T96

2

auto[1]

from_0to1

auto[1]

auto[1]

41

1

T4

1

T95

2

T96

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

680

1

T4

11

T7

10

T85

10

auto[1]

659

1

T4

9

T7

9

T85

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

313

1

T4

3

T7

4

T85

5

from_0to1

310

1

T4

3

T7

5

T85

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T4

7

T7

7

T85

6

auto[1]

681

1

T4

13

T7

12

T85

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

703

1

T4

12

T7

12

T85

14

auto[1]

636

1

T4

8

T7

7

T85

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

41

1

T4

1

T7

2

T85

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T7

1

T95

1

T331

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T4

1

T85

1

T94

1

auto[0]

from_1to0

auto[1]

auto[1]

28

1

T85

1

T94

1

T95

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T69

1

T321

1

T322

1

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T85

1

T95

1

T96

1

auto[0]

from_0to1

auto[1]

auto[0]

44

1

T4

1

T7

1

T85

4

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T4

1

T7

2

T95

1

auto[1]

from_1to0

auto[0]

auto[0]

40

1

T94

1

T69

1

T321

2

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T4

1

T95

1

T321

1

auto[1]

from_1to0

auto[1]

auto[0]

35

1

T85

2

T95

1

T96

1

auto[1]

from_1to0

auto[1]

auto[1]

39

1

T7

1

T96

2

T69

1

auto[1]

from_0to1

auto[0]

auto[0]

29

1

T7

1

T94

1

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

39

1

T94

1

T96

2

T331

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T7

1

T94

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T4

1

T95

1

T96

1