Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151091	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115948

1

T4

41

T5

1

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	139583	1			T4	62		T5	2		T6	3
values[0x0]	63388	1			T4	29		T6	3		T1	3
values[0x1]	64068	1			T4	32		T6	6		T1	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121997	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145042

1

T4

50

T5

2

T6

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	965	1			T85	10		T69	7		T32	1
valid_sources[0x01]	1145	1			T27	6		T85	9		T298	2
valid_sources[0x02]	1025	1			T309	13		T433	1		T69	2
valid_sources[0x03]	1047	1			T1	1		T69	4		T32	1
valid_sources[0x04]	926	1			T12	1		T69	6		T51	1
valid_sources[0x05]	1079	1			T93	2		T69	1		T334	1
valid_sources[0x06]	833	1			T29	1		T93	1		T433	1
valid_sources[0x07]	2239	1			T7	40		T85	3		T69	4
valid_sources[0x08]	899	1			T69	2		T106	2		T322	2
valid_sources[0x09]	1089	1			T299	3		T69	3		T32	2
valid_sources[0x0a]	929	1			T14	2		T85	6		T69	2
valid_sources[0x0b]	978	1			T4	2		T93	1		T298	3
valid_sources[0x0c]	881	1			T4	1		T7	19		T93	1
valid_sources[0x0d]	1172	1			T315	3		T299	32		T69	4
valid_sources[0x0e]	1504	1			T93	1		T69	4		T164	1
valid_sources[0x0f]	670	1			T4	2		T30	2		T91	1
valid_sources[0x10]	1672	1			T4	1		T93	1		T298	2
valid_sources[0x11]	846	1			T4	2		T433	1		T69	4
valid_sources[0x12]	1346	1			T4	3		T14	1		T298	4
valid_sources[0x13]	1011	1			T18	1		T85	1		T67	1
valid_sources[0x14]	1433	1			T4	2		T298	1		T433	1
valid_sources[0x15]	687	1			T311	13		T69	3		T77	1
valid_sources[0x16]	873	1			T85	4		T298	2		T91	1
valid_sources[0x17]	1069	1			T69	4		T32	7		T106	1
valid_sources[0x18]	683	1			T13	5		T69	3		T32	1
valid_sources[0x19]	819	1			T4	2		T21	2		T93	1
valid_sources[0x1a]	831	1			T4	1		T433	1		T69	3
valid_sources[0x1b]	1027	1			T19	1		T21	1		T64	122
valid_sources[0x1c]	835	1			T204	1		T298	2		T69	1
valid_sources[0x1d]	849	1			T4	1		T85	5		T12	1
valid_sources[0x1e]	1084	1			T7	30		T69	5		T32	3
valid_sources[0x1f]	851	1			T12	1		T69	5		T70	1
valid_sources[0x20]	848	1			T1	1		T14	1		T15	1
valid_sources[0x21]	943	1			T69	5		T167	1		T106	3
valid_sources[0x22]	1162	1			T12	1		T309	5		T69	4
valid_sources[0x23]	1499	1			T76	1		T67	1		T69	2
valid_sources[0x24]	1013	1			T76	3		T90	1		T69	1
valid_sources[0x25]	970	1			T433	2		T329	1		T69	2
valid_sources[0x26]	1072	1			T3	1		T12	1		T298	4
valid_sources[0x27]	1258	1			T4	1		T14	2		T433	1
valid_sources[0x28]	1750	1			T91	6		T69	4		T32	2
valid_sources[0x29]	1310	1			T21	4		T69	3		T106	3
valid_sources[0x2a]	900	1			T4	3		T69	7		T51	1
valid_sources[0x2b]	825	1			T4	1		T433	1		T91	3
valid_sources[0x2c]	1077	1			T9	1		T12	2		T298	2
valid_sources[0x2d]	1009	1			T4	1		T14	2		T298	1
valid_sources[0x2e]	780	1			T19	1		T298	1		T315	1
valid_sources[0x2f]	801	1			T298	1		T69	3		T32	1
valid_sources[0x30]	872	1			T4	2		T298	2		T299	10
valid_sources[0x31]	897	1			T4	1		T18	3		T66	11
valid_sources[0x32]	949	1			T4	1		T93	2		T298	2
valid_sources[0x33]	926	1			T4	1		T69	4		T32	3
valid_sources[0x34]	884	1			T4	1		T115	3		T298	3
valid_sources[0x35]	1050	1			T4	1		T298	1		T315	2
valid_sources[0x36]	1894	1			T4	2		T14	1		T27	4
valid_sources[0x37]	990	1			T4	2		T298	2		T309	2
valid_sources[0x38]	1339	1			T12	1		T69	6		T167	2
valid_sources[0x39]	1000	1			T309	15		T315	1		T69	8
valid_sources[0x3a]	710	1			T93	1		T69	1		T32	3
valid_sources[0x3b]	794	1			T4	1		T14	1		T93	1
valid_sources[0x3c]	908	1			T4	1		T93	1		T69	3
valid_sources[0x3d]	1080	1			T4	1		T298	4		T315	1
valid_sources[0x3e]	1593	1			T93	2		T67	2		T204	1
valid_sources[0x3f]	779	1			T4	1		T93	1		T298	4
valid_sources[0x40]	958	1			T91	1		T69	2		T51	1
valid_sources[0x41]	1950	1			T21	7		T298	1		T308	3
valid_sources[0x42]	939	1			T4	3		T299	7		T69	1
valid_sources[0x43]	1011	1			T4	1		T1	1		T76	1
valid_sources[0x44]	1020	1			T4	1		T93	2		T433	1
valid_sources[0x45]	860	1			T93	1		T30	1		T204	1
valid_sources[0x46]	1005	1			T433	1		T91	3		T69	4
valid_sources[0x47]	891	1			T30	2		T12	1		T32	1
valid_sources[0x48]	1595	1			T4	1		T14	1		T69	5
valid_sources[0x49]	979	1			T7	29		T299	13		T69	1
valid_sources[0x4a]	885	1			T93	1		T78	35		T313	5
valid_sources[0x4b]	952	1			T65	1		T433	1		T91	5
valid_sources[0x4c]	869	1			T4	1		T13	2		T69	4
valid_sources[0x4d]	815	1			T4	1		T27	2		T93	2
valid_sources[0x4e]	937	1			T4	3		T22	1		T85	6
valid_sources[0x4f]	823	1			T21	3		T12	1		T204	1
valid_sources[0x50]	899	1			T4	1		T93	1		T298	3
valid_sources[0x51]	1123	1			T1	1		T14	1		T12	2
valid_sources[0x52]	921	1			T4	1		T14	1		T68	1
valid_sources[0x53]	1055	1			T85	5		T298	1		T69	4
valid_sources[0x54]	981	1			T4	1		T67	1		T69	1
valid_sources[0x55]	1148	1			T1	1		T12	3		T204	1
valid_sources[0x56]	1329	1			T7	2		T13	1		T68	1
valid_sources[0x57]	991	1			T4	1		T433	1		T69	2
valid_sources[0x58]	1076	1			T433	4		T69	6		T32	1
valid_sources[0x59]	853	1			T14	1		T85	2		T29	2
valid_sources[0x5a]	850	1			T14	1		T93	2		T12	1
valid_sources[0x5b]	1854	1			T4	1		T68	1		T69	4
valid_sources[0x5c]	1045	1			T14	1		T93	1		T298	1
valid_sources[0x5d]	915	1			T69	2		T32	2		T92	1
valid_sources[0x5e]	849	1			T4	2		T27	1		T12	1
valid_sources[0x5f]	1326	1			T27	1		T29	1		T315	1
valid_sources[0x60]	1819	1			T4	1		T20	14		T299	16
valid_sources[0x61]	973	1			T93	1		T298	1		T299	2
valid_sources[0x62]	831	1			T4	1		T21	3		T298	6
valid_sources[0x63]	965	1			T16	2		T298	2		T69	2
valid_sources[0x64]	1035	1			T18	1		T85	6		T298	4
valid_sources[0x65]	1007	1			T6	7		T14	1		T7	14
valid_sources[0x66]	1446	1			T4	1		T433	1		T69	3
valid_sources[0x67]	889	1			T14	2		T30	2		T40	1
valid_sources[0x68]	1709	1			T4	1		T86	2		T69	2
valid_sources[0x69]	958	1			T90	4		T69	4		T32	6
valid_sources[0x6a]	1350	1			T29	1		T298	2		T308	2
valid_sources[0x6b]	847	1			T69	5		T32	8		T104	4
valid_sources[0x6c]	890	1			T4	1		T76	1		T12	1
valid_sources[0x6d]	995	1			T14	1		T433	1		T91	5
valid_sources[0x6e]	931	1			T4	2		T1	1		T69	4
valid_sources[0x6f]	844	1			T4	1		T19	2		T433	1
valid_sources[0x70]	834	1			T40	6		T69	2		T70	1
valid_sources[0x71]	914	1			T4	1		T22	1		T69	4
valid_sources[0x72]	962	1			T4	1		T14	2		T89	44
valid_sources[0x73]	1078	1			T4	1		T95	123		T204	1
valid_sources[0x74]	879	1			T4	1		T21	1		T2	5
valid_sources[0x75]	970	1			T21	1		T91	3		T69	5
valid_sources[0x76]	862	1			T433	1		T167	1		T106	4
valid_sources[0x77]	850	1			T93	1		T69	5		T334	1
valid_sources[0x78]	863	1			T93	1		T433	1		T69	5
valid_sources[0x79]	985	1			T21	6		T309	6		T69	1
valid_sources[0x7a]	959	1			T7	8		T85	3		T298	2
valid_sources[0x7b]	851	1			T21	5		T309	5		T90	5
valid_sources[0x7c]	851	1			T14	1		T93	2		T67	1
valid_sources[0x7d]	896	1			T4	2		T298	4		T315	2
valid_sources[0x7e]	977	1			T93	2		T69	3		T32	3
valid_sources[0x7f]	2033	1			T4	2		T29	1		T12	2
valid_sources[0x80]	999	1			T4	1		T93	1		T69	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62248

1

T4

31

T5

1

T6

2

values[0x0]

all_enables

biggest_size

31272

1

T4

5

T6

1

T1

2

values[0x1]

all_enables

biggest_size

22428

1

T4

5

T6

2

T1

1