Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.sysrst_ctrl_csr_assert 100.00 100.00


Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.02 100.00 96.08 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 36 36 100.00 36 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 36 36 100.00 36 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 1064255403 11161 0 0
auto_block_debounce_ctl_rd_A 1064255403 1798 0 0
auto_block_out_ctl_rd_A 1064255403 2902 0 0
com_det_ctl_0_rd_A 1064255403 3522 0 0
com_det_ctl_1_rd_A 1064255403 3512 0 0
com_det_ctl_2_rd_A 1064255403 3810 0 0
com_det_ctl_3_rd_A 1064255403 3563 0 0
com_out_ctl_0_rd_A 1064255403 4159 0 0
com_out_ctl_1_rd_A 1064255403 4036 0 0
com_out_ctl_2_rd_A 1064255403 4329 0 0
com_out_ctl_3_rd_A 1064255403 4181 0 0
com_pre_det_ctl_0_rd_A 1064255403 1375 0 0
com_pre_det_ctl_1_rd_A 1064255403 1564 0 0
com_pre_det_ctl_2_rd_A 1064255403 1332 0 0
com_pre_det_ctl_3_rd_A 1064255403 1385 0 0
com_pre_sel_ctl_0_rd_A 1064255403 4476 0 0
com_pre_sel_ctl_1_rd_A 1064255403 4496 0 0
com_pre_sel_ctl_2_rd_A 1064255403 4228 0 0
com_pre_sel_ctl_3_rd_A 1064255403 4496 0 0
com_sel_ctl_0_rd_A 1064255403 4332 0 0
com_sel_ctl_1_rd_A 1064255403 4584 0 0
com_sel_ctl_2_rd_A 1064255403 4445 0 0
com_sel_ctl_3_rd_A 1064255403 4426 0 0
ec_rst_ctl_rd_A 1064255403 2192 0 0
intr_enable_rd_A 1064255403 1926 0 0
key_intr_ctl_rd_A 1064255403 4785 0 0
key_intr_debounce_ctl_rd_A 1064255403 1258 0 0
key_invert_ctl_rd_A 1064255403 5462 0 0
pin_allowed_ctl_rd_A 1064255403 6325 0 0
pin_out_ctl_rd_A 1064255403 4801 0 0
pin_out_value_rd_A 1064255403 4883 0 0
regwen_rd_A 1064255403 1486 0 0
ulp_ac_debounce_ctl_rd_A 1064255403 1430 0 0
ulp_ctl_rd_A 1064255403 1457 0 0
ulp_lid_debounce_ctl_rd_A 1064255403 1533 0 0
ulp_pwrb_debounce_ctl_rd_A 1064255403 1464 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 11161 0 0
T7 149196 8 0 0
T8 215008 0 0 0
T9 247460 0 0 0
T27 125646 0 0 0
T29 226393 0 0 0
T64 208647 0 0 0
T69 0 13 0 0
T72 0 9 0 0
T76 193249 0 0 0
T84 11231 0 0 0
T85 205999 0 0 0
T106 0 15 0 0
T115 50700 0 0 0
T127 0 6 0 0
T131 0 14 0 0
T140 0 12 0 0
T298 0 2 0 0
T299 0 21 0 0
T313 0 14 0 0

auto_block_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1798 0 0
T11 25876 0 0 0
T12 63538 0 0 0
T30 322014 10 0 0
T65 106849 0 0 0
T66 31066 0 0 0
T67 145790 0 0 0
T69 0 57 0 0
T72 0 42 0 0
T86 205081 0 0 0
T88 66846 0 0 0
T94 121082 0 0 0
T106 0 19 0 0
T142 0 56 0 0
T148 126814 0 0 0
T224 0 39 0 0
T226 0 6 0 0
T260 0 9 0 0
T298 0 27 0 0
T314 0 10 0 0

auto_block_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 2902 0 0
T11 25876 0 0 0
T12 63538 0 0 0
T30 322014 17 0 0
T65 106849 0 0 0
T66 31066 0 0 0
T67 145790 0 0 0
T69 0 42 0 0
T72 0 49 0 0
T86 205081 0 0 0
T88 66846 0 0 0
T94 121082 0 0 0
T106 0 11 0 0
T142 0 45 0 0
T148 126814 0 0 0
T224 0 9 0 0
T226 0 6 0 0
T260 0 4 0 0
T298 0 34 0 0
T314 0 1 0 0

com_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 3522 0 0
T43 0 45 0 0
T44 0 21 0 0
T61 0 43 0 0
T69 0 21 0 0
T72 0 37 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 8 0 0
T142 0 22 0 0
T224 0 17 0 0
T281 529860 0 0 0
T298 326208 15 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 6 0 0
T315 221679 0 0 0

com_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 3512 0 0
T43 0 28 0 0
T44 0 29 0 0
T61 0 36 0 0
T69 0 28 0 0
T72 0 31 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 18 0 0
T142 0 30 0 0
T224 0 24 0 0
T281 529860 0 0 0
T298 326208 17 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 16 0 0
T315 221679 0 0 0

com_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 3810 0 0
T43 0 26 0 0
T44 0 25 0 0
T61 0 61 0 0
T69 0 29 0 0
T72 0 57 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 18 0 0
T142 0 33 0 0
T224 0 25 0 0
T281 529860 0 0 0
T298 326208 7 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 9 0 0
T315 221679 0 0 0

com_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 3563 0 0
T43 0 49 0 0
T44 0 44 0 0
T61 0 38 0 0
T69 0 18 0 0
T72 0 28 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 15 0 0
T142 0 27 0 0
T224 0 12 0 0
T281 529860 0 0 0
T298 326208 7 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 5 0 0
T315 221679 0 0 0

com_out_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4159 0 0
T43 0 23 0 0
T44 0 34 0 0
T61 0 54 0 0
T69 0 40 0 0
T72 0 45 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 20 0 0
T142 0 36 0 0
T224 0 16 0 0
T281 529860 0 0 0
T298 326208 9 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 13 0 0
T315 221679 0 0 0

com_out_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4036 0 0
T43 0 52 0 0
T44 0 35 0 0
T61 0 52 0 0
T69 0 39 0 0
T72 0 42 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 16 0 0
T142 0 45 0 0
T224 0 18 0 0
T281 529860 0 0 0
T298 326208 10 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 16 0 0
T315 221679 0 0 0

com_out_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4329 0 0
T43 0 42 0 0
T44 0 37 0 0
T61 0 53 0 0
T69 0 33 0 0
T72 0 30 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 7 0 0
T142 0 34 0 0
T224 0 15 0 0
T281 529860 0 0 0
T298 326208 15 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 8 0 0
T315 221679 0 0 0

com_out_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4181 0 0
T43 0 37 0 0
T44 0 42 0 0
T61 0 47 0 0
T69 0 39 0 0
T72 0 47 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 12 0 0
T142 0 29 0 0
T224 0 16 0 0
T281 529860 0 0 0
T298 326208 15 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 12 0 0
T315 221679 0 0 0

com_pre_det_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1375 0 0
T69 0 41 0 0
T72 0 51 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 22 0 0
T142 0 28 0 0
T224 0 23 0 0
T281 529860 0 0 0
T298 326208 22 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 14 0 0
T315 221679 0 0 0
T316 0 24 0 0
T317 0 16 0 0
T318 0 24 0 0

com_pre_det_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1564 0 0
T69 0 36 0 0
T72 0 29 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 9 0 0
T142 0 65 0 0
T224 0 27 0 0
T281 529860 0 0 0
T298 326208 20 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 2 0 0
T315 221679 0 0 0
T316 0 19 0 0
T317 0 3 0 0
T318 0 19 0 0

com_pre_det_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1332 0 0
T69 0 39 0 0
T72 0 36 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 24 0 0
T142 0 21 0 0
T224 0 46 0 0
T281 529860 0 0 0
T298 326208 18 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 23 0 0
T315 221679 0 0 0
T316 0 26 0 0
T317 0 11 0 0
T318 0 14 0 0

com_pre_det_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1385 0 0
T69 0 34 0 0
T72 0 48 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 6 0 0
T142 0 31 0 0
T224 0 15 0 0
T281 529860 0 0 0
T298 326208 22 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 2 0 0
T315 221679 0 0 0
T316 0 21 0 0
T317 0 14 0 0
T318 0 19 0 0

com_pre_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4476 0 0
T43 0 39 0 0
T44 0 37 0 0
T61 0 58 0 0
T69 0 33 0 0
T72 0 41 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 22 0 0
T142 0 41 0 0
T224 0 29 0 0
T281 529860 0 0 0
T298 326208 14 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 17 0 0
T315 221679 0 0 0

com_pre_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4496 0 0
T43 0 30 0 0
T44 0 28 0 0
T61 0 53 0 0
T69 0 38 0 0
T72 0 21 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 11 0 0
T142 0 28 0 0
T224 0 36 0 0
T281 529860 0 0 0
T298 326208 4 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 8 0 0
T315 221679 0 0 0

com_pre_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4228 0 0
T43 0 14 0 0
T44 0 50 0 0
T61 0 50 0 0
T69 0 34 0 0
T72 0 41 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 20 0 0
T142 0 36 0 0
T224 0 22 0 0
T281 529860 0 0 0
T298 326208 8 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 25 0 0
T315 221679 0 0 0

com_pre_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4496 0 0
T43 0 37 0 0
T44 0 47 0 0
T61 0 41 0 0
T69 0 31 0 0
T72 0 32 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 10 0 0
T142 0 37 0 0
T224 0 21 0 0
T281 529860 0 0 0
T298 326208 5 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 8 0 0
T315 221679 0 0 0

com_sel_ctl_0_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4332 0 0
T43 0 18 0 0
T44 0 31 0 0
T61 0 48 0 0
T69 0 41 0 0
T72 0 39 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 19 0 0
T142 0 33 0 0
T224 0 19 0 0
T281 529860 0 0 0
T298 326208 20 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 13 0 0
T315 221679 0 0 0

com_sel_ctl_1_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4584 0 0
T43 0 42 0 0
T44 0 47 0 0
T61 0 63 0 0
T69 0 22 0 0
T72 0 47 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 14 0 0
T142 0 44 0 0
T224 0 32 0 0
T281 529860 0 0 0
T298 326208 10 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 9 0 0
T315 221679 0 0 0

com_sel_ctl_2_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4445 0 0
T43 0 28 0 0
T44 0 36 0 0
T61 0 53 0 0
T69 0 34 0 0
T72 0 15 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 16 0 0
T142 0 42 0 0
T224 0 19 0 0
T281 529860 0 0 0
T298 326208 25 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 10 0 0
T315 221679 0 0 0

com_sel_ctl_3_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4426 0 0
T43 0 32 0 0
T44 0 46 0 0
T61 0 39 0 0
T69 0 42 0 0
T72 0 49 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 17 0 0
T142 0 53 0 0
T224 0 25 0 0
T281 529860 0 0 0
T298 326208 21 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 6 0 0
T315 221679 0 0 0

ec_rst_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 2192 0 0
T33 0 2 0 0
T34 0 6 0 0
T69 0 39 0 0
T72 0 33 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 23 0 0
T141 0 2 0 0
T142 0 48 0 0
T165 0 4 0 0
T281 529860 0 0 0
T298 326208 19 0 0
T307 526172 2 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T315 221679 0 0 0

intr_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1926 0 0
T69 0 80 0 0
T72 0 52 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 28 0 0
T142 0 44 0 0
T224 0 22 0 0
T281 529860 0 0 0
T298 326208 24 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 26 0 0
T315 221679 0 0 0
T316 0 26 0 0
T317 0 7 0 0
T319 0 8 0 0

key_intr_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4785 0 0
T13 258519 2 0 0
T40 15943 0 0 0
T49 0 67 0 0
T57 0 7 0 0
T68 179814 0 0 0
T69 0 36 0 0
T72 0 21 0 0
T78 20780 0 0 0
T81 0 9 0 0
T89 59563 0 0 0
T95 60599 0 0 0
T106 0 10 0 0
T141 0 1 0 0
T142 0 62 0 0
T149 12575 0 0 0
T150 268279 0 0 0
T151 61687 0 0 0
T204 59347 0 0 0
T298 0 15 0 0

key_intr_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1258 0 0
T69 0 36 0 0
T72 0 25 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 12 0 0
T142 0 37 0 0
T224 0 30 0 0
T281 529860 0 0 0
T298 326208 23 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 12 0 0
T315 221679 0 0 0
T316 0 24 0 0
T317 0 3 0 0
T318 0 19 0 0

key_invert_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 5462 0 0
T2 129751 0 0 0
T14 239735 61 0 0
T15 11152 0 0 0
T16 66867 0 0 0
T17 63277 0 0 0
T18 46584 0 0 0
T19 55937 0 0 0
T20 66107 0 0 0
T21 65571 0 0 0
T22 97060 0 0 0
T27 0 21 0 0
T28 0 41 0 0
T69 0 85 0 0
T72 0 47 0 0
T89 0 77 0 0
T106 0 18 0 0
T132 0 54 0 0
T298 0 25 0 0
T320 0 43 0 0

pin_allowed_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 6325 0 0
T1 233518 0 0 0
T4 78281 28 0 0
T5 206588 0 0 0
T6 225286 0 0 0
T14 239735 0 0 0
T15 11152 0 0 0
T16 66867 0 0 0
T17 63277 0 0 0
T18 46584 0 0 0
T23 210501 0 0 0
T69 0 162 0 0
T72 0 112 0 0
T94 0 89 0 0
T96 0 67 0 0
T106 0 13 0 0
T177 0 52 0 0
T298 0 14 0 0
T321 0 57 0 0
T322 0 32 0 0

pin_out_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4801 0 0
T1 233518 0 0 0
T4 78281 35 0 0
T5 206588 0 0 0
T6 225286 0 0 0
T14 239735 0 0 0
T15 11152 0 0 0
T16 66867 0 0 0
T17 63277 0 0 0
T18 46584 0 0 0
T23 210501 0 0 0
T69 0 174 0 0
T72 0 80 0 0
T94 0 53 0 0
T96 0 100 0 0
T106 0 36 0 0
T177 0 26 0 0
T298 0 29 0 0
T321 0 75 0 0
T322 0 23 0 0

pin_out_value_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 4883 0 0
T1 233518 0 0 0
T4 78281 36 0 0
T5 206588 0 0 0
T6 225286 0 0 0
T14 239735 0 0 0
T15 11152 0 0 0
T16 66867 0 0 0
T17 63277 0 0 0
T18 46584 0 0 0
T23 210501 0 0 0
T69 0 155 0 0
T72 0 105 0 0
T94 0 63 0 0
T96 0 60 0 0
T106 0 24 0 0
T177 0 21 0 0
T298 0 16 0 0
T321 0 72 0 0
T322 0 16 0 0

regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1486 0 0
T69 0 43 0 0
T72 0 48 0 0
T79 63082 0 0 0
T90 64834 0 0 0
T106 0 19 0 0
T142 0 18 0 0
T224 0 10 0 0
T281 529860 0 0 0
T298 326208 16 0 0
T307 526172 0 0 0
T308 296473 0 0 0
T309 242649 0 0 0
T310 103759 0 0 0
T311 48768 0 0 0
T314 0 2 0 0
T315 221679 0 0 0
T316 0 33 0 0
T317 0 9 0 0
T318 0 22 0 0

ulp_ac_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1430 0 0
T3 116311 10 0 0
T7 149196 0 0 0
T8 215008 0 0 0
T27 125646 0 0 0
T29 226393 0 0 0
T64 208647 0 0 0
T69 0 34 0 0
T72 0 26 0 0
T75 101644 0 0 0
T76 193249 0 0 0
T80 0 7 0 0
T81 0 7 0 0
T82 0 2 0 0
T84 11231 0 0 0
T85 205999 0 0 0
T106 0 40 0 0
T142 0 33 0 0
T298 0 16 0 0
T323 0 9 0 0

ulp_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1457 0 0
T3 116311 14 0 0
T7 149196 0 0 0
T8 215008 0 0 0
T27 125646 0 0 0
T29 226393 0 0 0
T64 208647 0 0 0
T69 0 39 0 0
T72 0 33 0 0
T75 101644 0 0 0
T76 193249 0 0 0
T80 0 3 0 0
T81 0 7 0 0
T82 0 10 0 0
T84 11231 0 0 0
T85 205999 0 0 0
T106 0 32 0 0
T142 0 40 0 0
T298 0 11 0 0
T323 0 10 0 0

ulp_lid_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1533 0 0
T3 116311 8 0 0
T7 149196 0 0 0
T8 215008 0 0 0
T27 125646 0 0 0
T29 226393 0 0 0
T64 208647 0 0 0
T69 0 54 0 0
T72 0 30 0 0
T75 101644 0 0 0
T76 193249 0 0 0
T80 0 3 0 0
T81 0 6 0 0
T82 0 5 0 0
T84 11231 0 0 0
T85 205999 0 0 0
T106 0 9 0 0
T142 0 27 0 0
T298 0 19 0 0
T323 0 16 0 0

ulp_pwrb_debounce_ctl_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1064255403 1464 0 0
T3 116311 10 0 0
T7 149196 0 0 0
T8 215008 0 0 0
T27 125646 0 0 0
T29 226393 0 0 0
T64 208647 0 0 0
T69 0 33 0 0
T72 0 28 0 0
T75 101644 0 0 0
T76 193249 0 0 0
T80 0 16 0 0
T82 0 2 0 0
T84 11231 0 0 0
T85 205999 0 0 0
T106 0 22 0 0
T142 0 24 0 0
T224 0 16 0 0
T298 0 28 0 0
T323 0 17 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%