Module Definition
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Module Instance : tb.dut.u_reg.u_chk.u_tlul_data_integ_dec.u_data_chk

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_tlul_data_integ_dec


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_secded_inv_39_32_dec
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 160 160 100.00
Total Bits 0->1 80 80 100.00
Total Bits 1->0 80 80 100.00

Ports 4 4 100.00
Port Bits 160 160 100.00
Port Bits 0->1 80 80 100.00
Port Bits 1->0 80 80 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
data_i[38:0] Yes Yes T4,T6,T23 Yes T4,T6,T23 INPUT
data_o[31:0] Yes Yes T4,T6,T23 Yes T4,T6,T23 OUTPUT
syndrome_o[6:0] Yes Yes T4,T20,T21 Yes T4,T20,T21 OUTPUT
err_o[1:0] Yes Yes T4,T20,T21 Yes T4,T20,T21 OUTPUT