SYSRST_CTRL Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	12.040s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	11.990s	2.481ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	8.730s	2.201ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	9.370s	2.310ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	22.000s	6.030ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	11.900s	2.047ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	5.883m	71.081ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	13.550s	2.771ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	12.590s	2.068ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	11.900s	2.047ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.550s	2.771ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	12.258m	198.823ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	9.938m	209.933ms	95	100	95.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	3.680m	252.163ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	21.374m	1.768s	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	15.550s	2.513ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	10.870s	2.140ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	46.783m	783.246ms	48	50	96.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	12.750s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	9.334m	1.671s	46	50	92.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.869m	41.153ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	55.864m	1.826s	48	50	96.00
V2	alert_test	sysrst_ctrl_alert_test	11.300s	2.012ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	10.130s	2.011ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	13.050s	2.129ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	13.050s	2.129ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	22.000s	6.030ms	5	5	100.00
		sysrst_ctrl_csr_rw	11.900s	2.047ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.550s	2.771ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	46.270s	9.996ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	22.000s	6.030ms	5	5	100.00
		sysrst_ctrl_csr_rw	11.900s	2.047ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	13.550s	2.771ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	46.270s	9.996ms	20	20	100.00
V2		TOTAL			679	692	98.12
V2S	tl_intg_err	sysrst_ctrl_sec_cm	53.890s	22.013ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	3.110m	42.363ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	3.110m	42.363ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	30.230s	530.850ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			914	932	98.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	11	73.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.91	99.08	98.00	100.00	96.15	99.30	99.23	93.62

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:

Test sysrst_ctrl_ultra_low_pwr has 4 failures.

0.sysrst_ctrl_ultra_low_pwr.2954300477940566240644572256178082573232746924185410769436563384846938508720
Line 371, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2542894126 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 4220394126 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4220394126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.sysrst_ctrl_ultra_low_pwr.94745423718561469219383863971526546373670831471381372127470435446177446440028
Line 371, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2186912590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 2349412590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 4849412590 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 4860606660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test sysrst_ctrl_stress_all has 1 failures.

15.sysrst_ctrl_stress_all.50114667669338784571586824686435380691707191054175351245926437579848078561005
Line 396, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 33087866981 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 33180366981 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 35885366981 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 35911032839 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_ec_pwr_on_rst_vseq
  UVM_INFO @ 37910548835 ps: (sysrst_ctrl_ec_pwr_on_rst_vseq.sv:26) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] Starting the body from ec_pwr_on_rst_vseq

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 3 failures.

46.sysrst_ctrl_combo_detect_with_pre_cond.107852615161018410628396692121168273614499252104844234423323952005275708928080
Line 389, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 26156936863 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 26156936863 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26156936863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

50.sysrst_ctrl_combo_detect_with_pre_cond.56919081071190126400916132939500447932410759691880916924027763301639615149202
Line 385, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 26073558598 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 36350142685 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 36350183089 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x26
  UVM_INFO @ 37393848712 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 37393848712 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3

... and 1 more failures.

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

12.sysrst_ctrl_stress_all_with_rand_reset.53553632464654129042839437750127004082731212478391977005667247852466801554764
Line 463, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25326049705 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 25326049705 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 25326049705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:771) [sysrst_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

14.sysrst_ctrl_stress_all_with_rand_reset.4411110286825517415532012586417884237948524944876150893132031091385645168568
Line 382, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4206068505 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4206068505 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 4206068505 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_in_out_inverted_vseq
  UVM_INFO @ 4211068505 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

22.sysrst_ctrl_combo_detect_with_pre_cond.21755877428046339943694050650361703127613440294984838027400266231373209177736
Line 452, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 132002584743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
  UVM_INFO @ 132012584743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0
  UVM_INFO @ 132012584743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :3
  UVM_INFO @ 132197584743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 132217584743 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 24.sysrst_ctrl_ec_pwr_on_rst.76843157578556081169745935934000186272892397495638725299011971804319657071790
    Line 371, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2366970857 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2366970857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 28.sysrst_ctrl_ec_pwr_on_rst.47053486704314844017858024575212330875465182905836654328204865915997269591550
    Log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:115) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

31.sysrst_ctrl_stress_all_with_rand_reset.115514463545471705704025939518349193409391584414942545042792729177946683789972
Line 401, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8046123328 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 8049704973 ps: (cip_base_vseq.sv:795) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 4/5
  UVM_INFO @ 8054509878 ps: (dv_base_reg.sv:332) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 8063051613 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 5/5

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all has 1 failures.

37.sysrst_ctrl_stress_all.46079356362344587153801946479512514565890667301348426417098480629691048055939
Line 374, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 4472230963 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:116) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key0_out_value == cfg.vif.key0_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4587328472 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 1d
  UVM_INFO @ 4807230963 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:30
  UVM_INFO @ 4907281686 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 2f
  UVM_INFO @ 5207230963 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:37

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

38.sysrst_ctrl_stress_all_with_rand_reset.44293264445256983735225600919176509622532694783743485149307084497008856406502
Line 433, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 31042133309 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 31267518119 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_ec_rst_vseq
  UVM_INFO @ 33267518119 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:44) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Starting the body from combo detect ec_rst
  UVM_INFO @ 33322133309 ps: (sysrst_ctrl_combo_detect_ec_rst_vseq.sv:70) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_ec_rst_vseq] Value of wait_cycles:2
  UVM_INFO @ 33622318119 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

48.sysrst_ctrl_stress_all_with_rand_reset.11352868586657577922762792273794326043716206834677081982062384866197520627043
Line 384, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4254054606 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 4254054606 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 4254054606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

62.sysrst_ctrl_combo_detect_with_pre_cond.60549079737204488708092368305798351054702290068163904084105866627257602074990
Line 379, in log /workspaces/repo/scratch/os_regression_2024_09_17/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 15550696195 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 16330696195 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
  UVM_INFO @ 16330879501 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2
  UVM_INFO @ 16345696195 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 15
  UVM_INFO @ 17385696195 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :2