UART Simulation Results

Wednesday May 17 2023 07:05:42 UTC

GitHub Revision: 3df77bec1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2320738200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	43.460s	5.368ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	15.326us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	16.948us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.120s	57.376us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	28.237us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.240s	79.809us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	16.948us	20	20	100.00
		uart_csr_aliasing	0.770s	28.237us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	6.572m	167.649ms	50	50	100.00
V2	parity	uart_smoke	43.460s	5.368ms	50	50	100.00
		uart_tx_rx	6.572m	167.649ms	50	50	100.00
V2	parity_error	uart_intr	23.894m	607.365ms	50	50	100.00
		uart_rx_parity_err	5.238m	194.347ms	50	50	100.00
V2	watermark	uart_tx_rx	6.572m	167.649ms	50	50	100.00
		uart_intr	23.894m	607.365ms	50	50	100.00
V2	fifo_full	uart_fifo_full	5.076m	213.476ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	5.436m	193.095ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	13.654m	126.967ms	300	300	100.00
V2	rx_frame_err	uart_intr	23.894m	607.365ms	50	50	100.00
V2	rx_break_err	uart_intr	23.894m	607.365ms	50	50	100.00
V2	rx_timeout	uart_intr	23.894m	607.365ms	50	50	100.00
V2	perf	uart_perf	27.737m	32.916ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.400s	10.864ms	50	50	100.00
V2	line_loopback	uart_loopback	26.400s	10.864ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	10.306m	212.557ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.916m	72.825ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	39.200s	6.528ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	39.050s	4.674ms	49	50	98.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	16.559m	175.427ms	50	50	100.00
V2	stress_all	uart_stress_all	35.204m	385.861ms	50	50	100.00
V2	stress_all_with_reset	uart_stress_all_with_rand_reset	32.268m	91.416ms	100	100	100.00
V2	alert_test	uart_alert_test	0.600s	12.479us	50	50	100.00
V2	intr_test	uart_intr_test	0.610s	42.468us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.340s	559.144us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.340s	559.144us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	15.326us	5	5	100.00
		uart_csr_rw	0.640s	16.948us	20	20	100.00
		uart_csr_aliasing	0.770s	28.237us	5	5	100.00
		uart_same_csr_outstanding	0.780s	54.961us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	15.326us	5	5	100.00
		uart_csr_rw	0.640s	16.948us	20	20	100.00
		uart_csr_aliasing	0.770s	28.237us	5	5	100.00
		uart_same_csr_outstanding	0.780s	54.961us	20	20	100.00
V2		TOTAL			1189	1190	99.92
V2S	tl_intg_err	uart_sec_cm	0.950s	266.415us	5	5	100.00
		uart_tl_intg_err	1.280s	296.786us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.280s	296.786us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			1319	1320	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	19	19	18	94.74
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.29	99.80	98.45	100.00	--	99.76	100.00	97.74

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: uart_reg_block.val.rx reset value: * has 1 failures:
  • Test uart_rx_oversample has 1 failures.

    • 19.uart_rx_oversample.8092385
      Line 217, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_rx_oversample/latest/run.log

        UVM_ERROR @ 244685669 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (51661 [0xc9cd] vs 37787 [0x939b]) Regname: uart_reg_block.val.rx reset value: 0x0
        UVM_INFO @ 387819693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• 2023.05.16_19.36.41
• 2023.05.15_18.52.41
• 2023.05.14_18.22.23
• 2023.05.13_19.06.57
• 2023.05.12_18.57.39
• 2023.05.12_11.35.45
• 2023.05.11_18.13.31