Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.00						20.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	20.00						20.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.00						20.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.00						20.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	1	20.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	1	20.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	13513620	0	0
ctrl_rd_A	2147483647	0	0	0
intr_enable_rd_A	2147483647	0	0	0
ovrd_rd_A	2147483647	0	0	0
timeout_ctrl_rd_A	2147483647	0	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13513620	0	0
T1	2146	19	0	0
T2	8560	383	0	0
T3	7635	4	0	0
T4	0	19	0	0
T5	0	19	0	0
T6	0	383	0	0
T7	0	383	0	0
T8	0	19	0	0
T9	0	19	0	0
T10	0	19	0	0
T11	2521	0	0	0
T12	1261	0	0	0
T13	1275	0	0	0
T14	1275	0	0	0
T15	2521	0	0	0
T16	1221	0	0	0
T17	1275	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0