Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36748740	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24314480

1

T1

108

T11

246

T12

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52021275	1			T1	90		T11	129		T12	23
values[0x0]	4286235	1			T1	38		T11	63		T12	16
values[0x1]	4755710	1			T1	43		T11	54		T12	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26005880	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

35057340

1

T1

126

T11

246

T12

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	261655	1			T76	21		T77	21		T78	21
valid_sources[0x01]	229220	1			T2	4		T76	8		T6	4
valid_sources[0x02]	232660	1			T76	12		T77	12		T115	10
valid_sources[0x03]	218630	1			T3	6		T76	22		T77	22
valid_sources[0x04]	238040	1			T11	1		T2	4		T15	1
valid_sources[0x05]	229755	1			T76	11		T77	11		T78	11
valid_sources[0x06]	240870	1			T2	1		T76	2		T6	1
valid_sources[0x07]	231345	1			T2	2		T76	11		T6	2
valid_sources[0x08]	253515	1			T11	9		T13	4		T14	4
valid_sources[0x09]	252535	1			T11	2		T2	2		T3	17
valid_sources[0x0a]	239490	1			T2	1		T3	11		T6	1
valid_sources[0x0b]	261525	1			T3	6		T21	6		T22	6
valid_sources[0x0c]	259805	1			T2	2		T3	6		T76	9
valid_sources[0x0d]	248585	1			T2	5		T16	1		T59	1
valid_sources[0x0e]	243555	1			T11	3		T12	1		T15	3
valid_sources[0x0f]	246885	1			T76	6		T77	6		T115	1
valid_sources[0x10]	236820	1			T1	3		T11	3		T15	3
valid_sources[0x11]	212525	1			T11	6		T2	4		T15	6
valid_sources[0x12]	256790	1			T11	4		T2	1		T3	3
valid_sources[0x13]	218055	1			T1	3		T11	7		T12	3
valid_sources[0x14]	237675	1			T11	2		T2	3		T3	1
valid_sources[0x15]	238645	1			T2	1		T3	2		T76	7
valid_sources[0x16]	220175	1			T1	3		T3	7		T4	3
valid_sources[0x17]	226155	1			T2	6		T76	17		T6	6
valid_sources[0x18]	256345	1			T1	5		T12	4		T2	3
valid_sources[0x19]	241645	1			T1	1		T4	1		T5	1
valid_sources[0x1a]	235800	1			T76	10		T77	10		T78	10
valid_sources[0x1b]	239530	1			T1	1		T3	3		T4	1
valid_sources[0x1c]	231330	1			T3	1		T76	2		T77	2
valid_sources[0x1d]	236895	1			T2	1		T3	4		T76	9
valid_sources[0x1e]	227935	1			T2	1		T76	1		T6	1
valid_sources[0x1f]	226560	1			T2	5		T3	6		T76	8
valid_sources[0x20]	233475	1			T12	2		T2	3		T3	5
valid_sources[0x21]	240545	1			T76	19		T77	19		T78	19
valid_sources[0x22]	259825	1			T11	9		T2	5		T3	4
valid_sources[0x23]	229655	1			T1	6		T2	1		T3	6
valid_sources[0x24]	219830	1			T2	2		T3	5		T76	8
valid_sources[0x25]	235150	1			T16	2		T59	2		T116	2
valid_sources[0x26]	240590	1			T1	6		T11	10		T2	2
valid_sources[0x27]	235950	1			T3	5		T76	20		T77	20
valid_sources[0x28]	244910	1			T2	1		T76	8		T6	1
valid_sources[0x29]	238030	1			T76	14		T77	14		T115	2
valid_sources[0x2a]	238580	1			T11	1		T2	2		T15	1
valid_sources[0x2b]	220395	1			T11	2		T12	1		T3	4
valid_sources[0x2c]	254670	1			T1	3		T2	3		T3	7
valid_sources[0x2d]	244010	1			T11	3		T2	2		T3	4
valid_sources[0x2e]	242740	1			T2	1		T76	4		T6	1
valid_sources[0x2f]	246990	1			T1	4		T2	2		T13	5
valid_sources[0x30]	234350	1			T11	1		T15	1		T27	1
valid_sources[0x31]	235255	1			T12	6		T76	5		T77	5
valid_sources[0x32]	236265	1			T1	1		T4	1		T5	1
valid_sources[0x33]	236010	1			T2	1		T3	9		T76	12
valid_sources[0x34]	244735	1			T76	6		T77	6		T115	1
valid_sources[0x35]	229915	1			T11	5		T2	13		T3	1
valid_sources[0x36]	255245	1			T2	3		T76	27		T6	3
valid_sources[0x37]	260020	1			T3	1		T76	20		T77	20
valid_sources[0x38]	236920	1			T3	13		T76	2		T77	2
valid_sources[0x39]	233905	1			T76	3		T77	3		T115	8
valid_sources[0x3a]	244365	1			T2	1		T16	3		T59	3
valid_sources[0x3b]	246590	1			T1	2		T3	5		T4	2
valid_sources[0x3c]	271735	1			T11	1		T12	2		T2	4
valid_sources[0x3d]	257535	1			T3	8		T76	25		T77	25
valid_sources[0x3e]	240180	1			T11	8		T15	8		T27	8
valid_sources[0x3f]	223700	1			T11	4		T2	1		T15	4
valid_sources[0x40]	246395	1			T3	10		T76	18		T77	18
valid_sources[0x41]	238965	1			T3	4		T76	8		T77	8
valid_sources[0x42]	219645	1			T3	2		T76	1		T77	1
valid_sources[0x43]	248430	1			T11	1		T2	2		T3	3
valid_sources[0x44]	214685	1			T2	1		T16	1		T59	1
valid_sources[0x45]	235370	1			T76	4		T77	4		T78	4
valid_sources[0x46]	225975	1			T2	1		T76	11		T6	1
valid_sources[0x47]	228860	1			T2	1		T3	3		T76	6
valid_sources[0x48]	248760	1			T3	3		T76	10		T77	10
valid_sources[0x49]	239395	1			T12	1		T3	7		T76	10
valid_sources[0x4a]	232710	1			T76	2		T77	2		T78	2
valid_sources[0x4b]	237810	1			T1	5		T2	1		T3	1
valid_sources[0x4c]	241305	1			T2	2		T3	11		T76	9
valid_sources[0x4d]	254190	1			T76	16		T77	16		T115	2
valid_sources[0x4e]	221990	1			T76	17		T77	17		T115	1
valid_sources[0x4f]	254070	1			T2	2		T76	19		T6	2
valid_sources[0x50]	239570	1			T2	2		T3	7		T76	8
valid_sources[0x51]	234735	1			T11	3		T15	3		T27	3
valid_sources[0x52]	232385	1			T76	7		T77	7		T78	7
valid_sources[0x53]	239255	1			T12	1		T2	7		T3	8
valid_sources[0x54]	248295	1			T2	1		T76	15		T6	1
valid_sources[0x55]	242140	1			T2	7		T6	7		T7	7
valid_sources[0x56]	232825	1			T1	1		T11	2		T3	3
valid_sources[0x57]	246400	1			T18	7		T19	680		T20	23
valid_sources[0x58]	246805	1			T76	20		T77	20		T115	1
valid_sources[0x59]	242205	1			T76	21		T77	21		T78	21
valid_sources[0x5a]	237070	1			T3	9		T76	8		T77	8
valid_sources[0x5b]	233325	1			T11	6		T15	6		T27	6
valid_sources[0x5c]	246505	1			T1	1		T2	5		T3	3
valid_sources[0x5d]	229595	1			T76	9		T77	9		T78	9
valid_sources[0x5e]	256890	1			T13	2		T3	3		T14	2
valid_sources[0x5f]	243900	1			T2	1		T76	6		T6	1
valid_sources[0x60]	234280	1			T11	6		T2	6		T3	7
valid_sources[0x61]	249985	1			T12	4		T3	1		T76	39
valid_sources[0x62]	246990	1			T2	2		T3	5		T6	2
valid_sources[0x63]	244390	1			T1	7		T11	3		T12	4
valid_sources[0x64]	242410	1			T2	2		T76	4		T6	2
valid_sources[0x65]	237170	1			T2	3		T13	3		T3	1
valid_sources[0x66]	246630	1			T2	2		T3	2		T6	2
valid_sources[0x67]	236915	1			T76	11		T77	11		T115	2
valid_sources[0x68]	226485	1			T76	7		T77	7		T78	7
valid_sources[0x69]	235510	1			T2	2		T3	5		T76	14
valid_sources[0x6a]	239200	1			T2	4		T3	10		T76	13
valid_sources[0x6b]	256610	1			T11	17		T12	3		T2	2
valid_sources[0x6c]	242010	1			T11	3		T2	6		T15	3
valid_sources[0x6d]	253135	1			T76	7		T77	7		T78	7
valid_sources[0x6e]	234260	1			T2	2		T3	1		T6	2
valid_sources[0x6f]	253130	1			T2	1		T3	2		T76	14
valid_sources[0x70]	236385	1			T1	1		T11	1		T3	10
valid_sources[0x71]	229930	1			T2	4		T76	9		T6	4
valid_sources[0x72]	241610	1			T11	1		T2	7		T3	3
valid_sources[0x73]	237170	1			T1	9		T3	3		T16	1
valid_sources[0x74]	231345	1			T1	3		T11	9		T2	9
valid_sources[0x75]	220710	1			T3	8		T16	7		T59	7
valid_sources[0x76]	236095	1			T1	6		T11	2		T3	8
valid_sources[0x77]	236315	1			T1	1		T2	24		T4	1
valid_sources[0x78]	239500	1			T3	18		T76	8		T77	8
valid_sources[0x79]	230165	1			T2	1		T76	9		T6	1
valid_sources[0x7a]	250155	1			T11	3		T2	1		T15	3
valid_sources[0x7b]	237010	1			T3	15		T76	2		T77	2
valid_sources[0x7c]	236355	1			T2	2		T76	3		T6	2
valid_sources[0x7d]	242165	1			T2	2		T3	3		T76	3
valid_sources[0x7e]	230505	1			T76	1		T77	1		T78	1
valid_sources[0x7f]	235755	1			T3	1		T76	7		T77	7
valid_sources[0x80]	236140	1			T2	3		T76	26		T6	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16366750

1

T1

40

T11

129

T12

14

values[0x0]

all_enables

biggest_size

4023550

1

T1

32

T11

63

T12

10

values[0x1]

all_enables

biggest_size

3924180

1

T1

36

T11

54

T12

2