Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	336	1			T3	8		T5	5		T6	1
all_values[1]	336	1			T3	8		T5	5		T6	1
all_values[2]	336	1			T3	8		T5	5		T6	1
all_values[3]	336	1			T3	8		T5	5		T6	1
all_values[4]	336	1			T3	8		T5	5		T6	1
all_values[5]	336	1			T3	8		T5	5		T6	1
all_values[6]	336	1			T3	8		T5	5		T6	1
all_values[7]	336	1			T3	8		T5	5		T6	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1450

1

T3

28

T5

24

T6

8

auto[1]

1238

1

T3

36

T5

16

T9

21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1694

1

T3

43

T5

28

T6

8

auto[1]

994

1

T3

21

T5

12

T9

19

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	111	1			T3	1		T5	2		T6	1
all_values[0]	auto[0]	auto[1]	66	1			T3	6		T5	2		T43	1
all_values[0]	auto[1]	auto[0]	100	1			T3	1		T5	1		T9	1
all_values[0]	auto[1]	auto[1]	59	1			T8	1		T10	1		T32	2
all_values[1]	auto[0]	auto[0]	108	1			T3	3		T6	1		T11	1
all_values[1]	auto[0]	auto[1]	60	1			T5	1		T24	1		T32	4
all_values[1]	auto[1]	auto[0]	102	1			T3	1		T5	2		T9	2
all_values[1]	auto[1]	auto[1]	66	1			T3	4		T5	2		T9	3
all_values[2]	auto[0]	auto[0]	139	1			T3	5		T5	5		T6	1
all_values[2]	auto[0]	auto[1]	62	1			T9	1		T8	2		T10	2
all_values[2]	auto[1]	auto[0]	76	1			T3	1		T9	2		T10	1
all_values[2]	auto[1]	auto[1]	59	1			T3	2		T9	2		T8	3
all_values[3]	auto[0]	auto[0]	106	1			T3	1		T5	2		T6	1
all_values[3]	auto[0]	auto[1]	70	1			T3	2		T5	2		T9	1
all_values[3]	auto[1]	auto[0]	92	1			T3	3		T5	1		T9	1
all_values[3]	auto[1]	auto[1]	68	1			T3	2		T9	3		T24	1
all_values[4]	auto[0]	auto[0]	133	1			T3	1		T5	1		T6	1
all_values[4]	auto[0]	auto[1]	67	1			T3	1		T5	2		T9	2
all_values[4]	auto[1]	auto[0]	90	1			T3	4		T5	2		T8	4
all_values[4]	auto[1]	auto[1]	46	1			T3	2		T8	2		T24	2
all_values[5]	auto[0]	auto[0]	107	1			T3	5		T5	1		T6	1
all_values[5]	auto[0]	auto[1]	57	1			T5	2		T9	3		T8	3
all_values[5]	auto[1]	auto[0]	101	1			T3	3		T5	2		T8	2
all_values[5]	auto[1]	auto[1]	71	1			T9	1		T8	2		T24	1
all_values[6]	auto[0]	auto[0]	123	1			T3	3		T5	1		T6	1
all_values[6]	auto[0]	auto[1]	72	1			T5	1		T24	1		T10	1
all_values[6]	auto[1]	auto[0]	89	1			T3	3		T5	3		T9	4
all_values[6]	auto[1]	auto[1]	52	1			T3	2		T10	2		T32	1
all_values[7]	auto[0]	auto[0]	112	1			T5	2		T6	1		T9	1
all_values[7]	auto[0]	auto[1]	57	1			T9	2		T8	5		T24	1
all_values[7]	auto[1]	auto[0]	105	1			T3	8		T5	3		T9	1
all_values[7]	auto[1]	auto[1]	62	1			T9	1		T8	1		T24	1