Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
65.90	64.36	63.61	96.46		63.57	100.00	7.39

Total tests in report: 165

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
60.64	60.64	61.47	61.47	52.91	52.91	92.15	92.15			58.81	58.81	95.38	95.38	3.13	3.13	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3221527970
64.23	3.59	64.05	2.58	60.88	7.97	96.60	4.45			62.62	3.81	95.71	0.33	5.52	2.39	/workspace/coverage/cover_reg_top/9.uart_intr_test.162076025
65.34	1.11	64.05	0.00	62.31	1.43	99.48	2.88			62.86	0.24	97.03	1.32	6.32	0.80	/workspace/coverage/cover_reg_top/6.uart_tl_errors.384661228
66.00	0.66	64.36	0.31	62.90	0.59	99.74	0.26			63.57	0.71	99.01	1.98	6.42	0.10	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3556609219
66.12	0.12	64.36	0.00	62.90	0.00	99.74	0.00			63.57	0.00	99.01	0.00	7.16	0.73	/workspace/coverage/cover_reg_top/21.uart_intr_test.3025797654
66.23	0.11	64.36	0.00	62.90	0.00	99.74	0.00			63.57	0.00	99.67	0.66	7.16	0.00	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.206568078
66.31	0.08	64.36	0.00	63.38	0.48	99.74	0.00			63.57	0.00	99.67	0.00	7.16	0.00	/workspace/coverage/cover_reg_top/18.uart_tl_errors.1750012917
66.37	0.06	64.36	0.00	63.38	0.00	99.74	0.00			63.57	0.00	100.00	0.33	7.18	0.02	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.167264673
66.40	0.03	64.36	0.00	63.50	0.12	99.74	0.00			63.57	0.00	100.00	0.00	7.22	0.04	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.710776739
66.42	0.02	64.36	0.00	63.61	0.12	99.74	0.00			63.57	0.00	100.00	0.00	7.22	0.00	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.148204461
66.44	0.02	64.36	0.00	63.61	0.00	99.74	0.00			63.57	0.00	100.00	0.00	7.33	0.10	/workspace/coverage/cover_reg_top/45.uart_intr_test.3270639075
66.45	0.01	64.36	0.00	63.61	0.00	99.74	0.00			63.57	0.00	100.00	0.00	7.39	0.06	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2319319189

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1097135281
/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4058421423
/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4073817797
/workspace/coverage/cover_reg_top/0.uart_csr_rw.847670402
/workspace/coverage/cover_reg_top/0.uart_intr_test.4274385492
/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3863265601
/workspace/coverage/cover_reg_top/0.uart_tl_errors.3872861947
/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1146826395
/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3779686272
/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2824716646
/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3943976189
/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3364784988
/workspace/coverage/cover_reg_top/1.uart_csr_rw.3137186111
/workspace/coverage/cover_reg_top/1.uart_intr_test.1071846988
/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1353641959
/workspace/coverage/cover_reg_top/1.uart_tl_errors.2146998819
/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.559310350
/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2432470003
/workspace/coverage/cover_reg_top/10.uart_csr_rw.2794898942
/workspace/coverage/cover_reg_top/10.uart_intr_test.1106468104
/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3254044430
/workspace/coverage/cover_reg_top/10.uart_tl_errors.1044854220
/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1075796367
/workspace/coverage/cover_reg_top/11.uart_csr_rw.2822045122
/workspace/coverage/cover_reg_top/11.uart_intr_test.2239675037
/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4122760563
/workspace/coverage/cover_reg_top/11.uart_tl_errors.2266840056
/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3104084165
/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1807042087
/workspace/coverage/cover_reg_top/12.uart_csr_rw.2614765234
/workspace/coverage/cover_reg_top/12.uart_intr_test.1625567125
/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4252676741
/workspace/coverage/cover_reg_top/12.uart_tl_errors.1433113240
/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3895548743
/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3706333476
/workspace/coverage/cover_reg_top/13.uart_csr_rw.3860420304
/workspace/coverage/cover_reg_top/13.uart_intr_test.1145118287
/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3779136916
/workspace/coverage/cover_reg_top/13.uart_tl_errors.3471437346
/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.43516512
/workspace/coverage/cover_reg_top/14.uart_csr_rw.863755111
/workspace/coverage/cover_reg_top/14.uart_intr_test.333714680
/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2009110878
/workspace/coverage/cover_reg_top/14.uart_tl_errors.2010111008
/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3746532650
/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3557783999
/workspace/coverage/cover_reg_top/15.uart_csr_rw.465324907
/workspace/coverage/cover_reg_top/15.uart_intr_test.1060433400
/workspace/coverage/cover_reg_top/15.uart_tl_errors.4024654334
/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.694796125
/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4048035125
/workspace/coverage/cover_reg_top/16.uart_csr_rw.768078644
/workspace/coverage/cover_reg_top/16.uart_intr_test.3073124710
/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.818475679
/workspace/coverage/cover_reg_top/16.uart_tl_errors.3816117640
/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2062231222
/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2418806363
/workspace/coverage/cover_reg_top/17.uart_csr_rw.1699618328
/workspace/coverage/cover_reg_top/17.uart_intr_test.3346754958
/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3239021595
/workspace/coverage/cover_reg_top/17.uart_tl_errors.1867614746
/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4177248581
/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1415872179
/workspace/coverage/cover_reg_top/18.uart_csr_rw.3644785131
/workspace/coverage/cover_reg_top/18.uart_intr_test.2284196033
/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3178397237
/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1360249745
/workspace/coverage/cover_reg_top/19.uart_csr_rw.3056332191
/workspace/coverage/cover_reg_top/19.uart_intr_test.3337056261
/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.941286732
/workspace/coverage/cover_reg_top/19.uart_tl_errors.3735285204
/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2373546420
/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2359886580
/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3846191027
/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1863257306
/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1228669930
/workspace/coverage/cover_reg_top/2.uart_csr_rw.1056572142
/workspace/coverage/cover_reg_top/2.uart_intr_test.1769067219
/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.711429564
/workspace/coverage/cover_reg_top/2.uart_tl_errors.2530476861
/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1498801402
/workspace/coverage/cover_reg_top/20.uart_intr_test.4120984182
/workspace/coverage/cover_reg_top/22.uart_intr_test.248063952
/workspace/coverage/cover_reg_top/23.uart_intr_test.3865631720
/workspace/coverage/cover_reg_top/24.uart_intr_test.1455209257
/workspace/coverage/cover_reg_top/25.uart_intr_test.2187457481
/workspace/coverage/cover_reg_top/26.uart_intr_test.349648494
/workspace/coverage/cover_reg_top/27.uart_intr_test.3709397627
/workspace/coverage/cover_reg_top/28.uart_intr_test.3337353494
/workspace/coverage/cover_reg_top/29.uart_intr_test.528390328
/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2082832418
/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4248457826
/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1257234726
/workspace/coverage/cover_reg_top/3.uart_csr_rw.2830890909
/workspace/coverage/cover_reg_top/3.uart_intr_test.3976555641
/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2799770623
/workspace/coverage/cover_reg_top/3.uart_tl_errors.2427551856
/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1610775041
/workspace/coverage/cover_reg_top/30.uart_intr_test.3559799701
/workspace/coverage/cover_reg_top/31.uart_intr_test.2937356661
/workspace/coverage/cover_reg_top/32.uart_intr_test.2870244454
/workspace/coverage/cover_reg_top/33.uart_intr_test.934299491
/workspace/coverage/cover_reg_top/34.uart_intr_test.2829888972
/workspace/coverage/cover_reg_top/35.uart_intr_test.422082606
/workspace/coverage/cover_reg_top/36.uart_intr_test.522973795
/workspace/coverage/cover_reg_top/37.uart_intr_test.53022101
/workspace/coverage/cover_reg_top/38.uart_intr_test.2702224547
/workspace/coverage/cover_reg_top/39.uart_intr_test.1438686553
/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1424135630
/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3947587833
/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.561108881
/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.763378147
/workspace/coverage/cover_reg_top/4.uart_csr_rw.3424922397
/workspace/coverage/cover_reg_top/4.uart_intr_test.1631445562
/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4090020864
/workspace/coverage/cover_reg_top/4.uart_tl_errors.2573343889
/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2674217589
/workspace/coverage/cover_reg_top/40.uart_intr_test.2464474
/workspace/coverage/cover_reg_top/41.uart_intr_test.1575412644
/workspace/coverage/cover_reg_top/42.uart_intr_test.2167137609
/workspace/coverage/cover_reg_top/43.uart_intr_test.3375989842
/workspace/coverage/cover_reg_top/44.uart_intr_test.3259424108
/workspace/coverage/cover_reg_top/46.uart_intr_test.38920585
/workspace/coverage/cover_reg_top/47.uart_intr_test.1923780244
/workspace/coverage/cover_reg_top/48.uart_intr_test.293838391
/workspace/coverage/cover_reg_top/49.uart_intr_test.588916898
/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2618921124
/workspace/coverage/cover_reg_top/5.uart_csr_rw.2057315987
/workspace/coverage/cover_reg_top/5.uart_intr_test.757357546
/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.449824463
/workspace/coverage/cover_reg_top/5.uart_tl_errors.2617376972
/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.898829191
/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1409647023
/workspace/coverage/cover_reg_top/6.uart_csr_rw.2525313911
/workspace/coverage/cover_reg_top/6.uart_intr_test.3452946497
/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1863603426
/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2167634503
/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.194884287
/workspace/coverage/cover_reg_top/7.uart_csr_rw.243273218
/workspace/coverage/cover_reg_top/7.uart_intr_test.1531935327
/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1765297493
/workspace/coverage/cover_reg_top/7.uart_tl_errors.2601438368
/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2488680723
/workspace/coverage/cover_reg_top/8.uart_csr_rw.1672343454
/workspace/coverage/cover_reg_top/8.uart_intr_test.4203834259
/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.278621282
/workspace/coverage/cover_reg_top/8.uart_tl_errors.4082265869
/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2031241013
/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3763571822
/workspace/coverage/cover_reg_top/9.uart_csr_rw.3830872272
/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2775247586
/workspace/coverage/cover_reg_top/9.uart_tl_errors.4042070062
/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1705374303

Total test records in report: 165

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3221527970	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:33 PM PST 24	331577603 ps
T2	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2167634503	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:22 PM PST 24	47561157 ps
T3	/workspace/coverage/cover_reg_top/9.uart_intr_test.162076025	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:34 PM PST 24	32902781 ps
T5	/workspace/coverage/cover_reg_top/28.uart_intr_test.3337353494	Jan 10 12:55:38 PM PST 24	Jan 10 12:56:46 PM PST 24	14338656 ps
T7	/workspace/coverage/cover_reg_top/16.uart_csr_rw.768078644	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:42 PM PST 24	35908804 ps
T6	/workspace/coverage/cover_reg_top/18.uart_tl_errors.1750012917	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:42 PM PST 24	26158807 ps
T9	/workspace/coverage/cover_reg_top/45.uart_intr_test.3270639075	Jan 10 12:55:38 PM PST 24	Jan 10 12:56:46 PM PST 24	22087700 ps
T11	/workspace/coverage/cover_reg_top/4.uart_tl_errors.2573343889	Jan 10 12:55:20 PM PST 24	Jan 10 12:56:28 PM PST 24	121503362 ps
T12	/workspace/coverage/cover_reg_top/0.uart_csr_rw.847670402	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:15 PM PST 24	34665186 ps
T13	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1097135281	Jan 10 12:55:07 PM PST 24	Jan 10 12:56:12 PM PST 24	83698407 ps
T8	/workspace/coverage/cover_reg_top/46.uart_intr_test.38920585	Jan 10 12:55:41 PM PST 24	Jan 10 12:56:51 PM PST 24	23487386 ps
T23	/workspace/coverage/cover_reg_top/10.uart_csr_rw.2794898942	Jan 10 12:55:27 PM PST 24	Jan 10 12:56:34 PM PST 24	171029919 ps
T14	/workspace/coverage/cover_reg_top/6.uart_tl_errors.384661228	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:25 PM PST 24	218528400 ps
T24	/workspace/coverage/cover_reg_top/31.uart_intr_test.2937356661	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	38259154 ps
T25	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.711429564	Jan 10 12:55:20 PM PST 24	Jan 10 12:56:28 PM PST 24	38194235 ps
T10	/workspace/coverage/cover_reg_top/40.uart_intr_test.2464474	Jan 10 12:55:42 PM PST 24	Jan 10 12:56:50 PM PST 24	37408972 ps
T32	/workspace/coverage/cover_reg_top/21.uart_intr_test.3025797654	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:43 PM PST 24	16723722 ps
T26	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.449824463	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:26 PM PST 24	65674454 ps
T33	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3424922397	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:27 PM PST 24	43811330 ps
T34	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.167264673	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	63125525 ps
T4	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3556609219	Jan 10 12:55:28 PM PST 24	Jan 10 12:56:35 PM PST 24	1063697715 ps
T41	/workspace/coverage/cover_reg_top/8.uart_intr_test.4203834259	Jan 10 12:57:06 PM PST 24	Jan 10 12:58:18 PM PST 24	53337350 ps
T27	/workspace/coverage/cover_reg_top/19.uart_csr_rw.3056332191	Jan 10 12:55:34 PM PST 24	Jan 10 12:56:42 PM PST 24	14137425 ps
T15	/workspace/coverage/cover_reg_top/13.uart_tl_errors.3471437346	Jan 10 12:55:30 PM PST 24	Jan 10 12:56:39 PM PST 24	331015978 ps
T42	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3763571822	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:33 PM PST 24	99343598 ps
T43	/workspace/coverage/cover_reg_top/10.uart_intr_test.1106468104	Jan 10 12:55:28 PM PST 24	Jan 10 12:56:35 PM PST 24	67382026 ps
T44	/workspace/coverage/cover_reg_top/25.uart_intr_test.2187457481	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:43 PM PST 24	13999800 ps
T28	/workspace/coverage/cover_reg_top/14.uart_csr_rw.863755111	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:33 PM PST 24	22279058 ps
T16	/workspace/coverage/cover_reg_top/7.uart_tl_errors.2601438368	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:25 PM PST 24	41231901 ps
T17	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2488680723	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	237917184 ps
T49	/workspace/coverage/cover_reg_top/15.uart_intr_test.1060433400	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:33 PM PST 24	46137133 ps
T50	/workspace/coverage/cover_reg_top/2.uart_intr_test.1769067219	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:21 PM PST 24	43250661 ps
T29	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4252676741	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:34 PM PST 24	28419254 ps
T52	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4058421423	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:15 PM PST 24	15403599 ps
T51	/workspace/coverage/cover_reg_top/2.uart_csr_rw.1056572142	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:21 PM PST 24	23320811 ps
T18	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2418806363	Jan 10 12:55:43 PM PST 24	Jan 10 12:56:52 PM PST 24	64394616 ps
T55	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.559310350	Jan 10 12:55:09 PM PST 24	Jan 10 12:56:14 PM PST 24	48778795 ps
T30	/workspace/coverage/cover_reg_top/15.uart_csr_rw.465324907	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	12849301 ps
T65	/workspace/coverage/cover_reg_top/20.uart_intr_test.4120984182	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	51752789 ps
T19	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1807042087	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:34 PM PST 24	29094773 ps
T53	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3943976189	Jan 10 12:55:06 PM PST 24	Jan 10 12:56:12 PM PST 24	16307029 ps
T63	/workspace/coverage/cover_reg_top/43.uart_intr_test.3375989842	Jan 10 12:55:53 PM PST 24	Jan 10 12:57:01 PM PST 24	51501834 ps
T21	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.694796125	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:34 PM PST 24	121032296 ps
T20	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2146998819	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:16 PM PST 24	275275732 ps
T66	/workspace/coverage/cover_reg_top/13.uart_intr_test.1145118287	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:32 PM PST 24	40852844 ps
T22	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3816117640	Jan 10 12:55:30 PM PST 24	Jan 10 12:56:38 PM PST 24	42734972 ps
T31	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2359886580	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	20200230 ps
T67	/workspace/coverage/cover_reg_top/8.uart_csr_rw.1672343454	Jan 10 12:55:20 PM PST 24	Jan 10 12:56:27 PM PST 24	22492037 ps
T35	/workspace/coverage/cover_reg_top/6.uart_csr_rw.2525313911	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	13040908 ps
T68	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2009110878	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	19199285 ps
T69	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4073817797	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:15 PM PST 24	92977623 ps
T70	/workspace/coverage/cover_reg_top/7.uart_intr_test.1531935327	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:24 PM PST 24	36796323 ps
T71	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2822045122	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:33 PM PST 24	43320030 ps
T72	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2082832418	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:22 PM PST 24	38384822 ps
T59	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4177248581	Jan 10 12:55:54 PM PST 24	Jan 10 12:57:03 PM PST 24	44619257 ps
T64	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3557783999	Jan 10 12:55:27 PM PST 24	Jan 10 12:56:35 PM PST 24	14863600 ps
T73	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.278621282	Jan 10 12:55:31 PM PST 24	Jan 10 12:56:38 PM PST 24	151502865 ps
T36	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1424135630	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:20 PM PST 24	201044601 ps
T74	/workspace/coverage/cover_reg_top/44.uart_intr_test.3259424108	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:43 PM PST 24	46956254 ps
T75	/workspace/coverage/cover_reg_top/16.uart_intr_test.3073124710	Jan 10 12:55:52 PM PST 24	Jan 10 12:57:00 PM PST 24	50353375 ps
T76	/workspace/coverage/cover_reg_top/6.uart_intr_test.3452946497	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:24 PM PST 24	22787828 ps
T77	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2618921124	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	20927447 ps
T78	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3239021595	Jan 10 12:55:50 PM PST 24	Jan 10 12:56:58 PM PST 24	63590130 ps
T79	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1415872179	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	29129918 ps
T80	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1360249745	Jan 10 12:55:39 PM PST 24	Jan 10 12:56:47 PM PST 24	16200925 ps
T81	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4248457826	Jan 10 12:55:13 PM PST 24	Jan 10 12:56:21 PM PST 24	257294352 ps
T54	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2674217589	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:28 PM PST 24	372110866 ps
T82	/workspace/coverage/cover_reg_top/9.uart_csr_rw.3830872272	Jan 10 12:55:28 PM PST 24	Jan 10 12:56:36 PM PST 24	40758242 ps
T83	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1433113240	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	68842924 ps
T84	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3895548743	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:36 PM PST 24	50594427 ps
T37	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.561108881	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:27 PM PST 24	15141655 ps
T85	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2319319189	Jan 10 12:55:22 PM PST 24	Jan 10 12:56:31 PM PST 24	92887490 ps
T86	/workspace/coverage/cover_reg_top/17.uart_intr_test.3346754958	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:43 PM PST 24	39470226 ps
T87	/workspace/coverage/cover_reg_top/17.uart_tl_errors.1867614746	Jan 10 12:55:36 PM PST 24	Jan 10 12:56:45 PM PST 24	54164124 ps
T88	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3860420304	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	31139802 ps
T89	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4122760563	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	32066743 ps
T90	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3872861947	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:16 PM PST 24	167296798 ps
T91	/workspace/coverage/cover_reg_top/39.uart_intr_test.1438686553	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	41560765 ps
T92	/workspace/coverage/cover_reg_top/1.uart_csr_rw.3137186111	Jan 10 12:55:09 PM PST 24	Jan 10 12:56:14 PM PST 24	78322729 ps
T93	/workspace/coverage/cover_reg_top/30.uart_intr_test.3559799701	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:42 PM PST 24	58532215 ps
T94	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.763378147	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:24 PM PST 24	28563339 ps
T95	/workspace/coverage/cover_reg_top/11.uart_intr_test.2239675037	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	40546320 ps
T96	/workspace/coverage/cover_reg_top/37.uart_intr_test.53022101	Jan 10 12:55:41 PM PST 24	Jan 10 12:56:49 PM PST 24	93167314 ps
T97	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2775247586	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	52196118 ps
T38	/workspace/coverage/cover_reg_top/17.uart_csr_rw.1699618328	Jan 10 12:55:32 PM PST 24	Jan 10 12:56:39 PM PST 24	24493512 ps
T98	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4090020864	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	29755808 ps
T99	/workspace/coverage/cover_reg_top/8.uart_tl_errors.4082265869	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:27 PM PST 24	412293701 ps
T100	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1409647023	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	76480759 ps
T101	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3846191027	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:29 PM PST 24	184146824 ps
T62	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1146826395	Jan 10 12:55:08 PM PST 24	Jan 10 12:56:14 PM PST 24	1605896986 ps
T102	/workspace/coverage/cover_reg_top/18.uart_intr_test.2284196033	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	58490969 ps
T103	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.941286732	Jan 10 12:55:32 PM PST 24	Jan 10 12:56:40 PM PST 24	31670830 ps
T104	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2266840056	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	238951356 ps
T56	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2373546420	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	294420743 ps
T105	/workspace/coverage/cover_reg_top/12.uart_csr_rw.2614765234	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:32 PM PST 24	13842221 ps
T106	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1228669930	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:26 PM PST 24	51919957 ps
T107	/workspace/coverage/cover_reg_top/10.uart_tl_errors.1044854220	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:34 PM PST 24	122263269 ps
T108	/workspace/coverage/cover_reg_top/14.uart_intr_test.333714680	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:34 PM PST 24	22645025 ps
T109	/workspace/coverage/cover_reg_top/36.uart_intr_test.522973795	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:42 PM PST 24	30151601 ps
T110	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1765297493	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	104741398 ps
T111	/workspace/coverage/cover_reg_top/34.uart_intr_test.2829888972	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:42 PM PST 24	13579876 ps
T112	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1353641959	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	68020598 ps
T113	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3706333476	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:31 PM PST 24	88260495 ps
T114	/workspace/coverage/cover_reg_top/0.uart_intr_test.4274385492	Jan 10 12:55:09 PM PST 24	Jan 10 12:56:14 PM PST 24	32034398 ps
T115	/workspace/coverage/cover_reg_top/27.uart_intr_test.3709397627	Jan 10 12:55:34 PM PST 24	Jan 10 12:56:42 PM PST 24	23006385 ps
T39	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1863257306	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:21 PM PST 24	13106586 ps
T116	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1610775041	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:28 PM PST 24	50595049 ps
T117	/workspace/coverage/cover_reg_top/23.uart_intr_test.3865631720	Jan 10 12:55:36 PM PST 24	Jan 10 12:56:45 PM PST 24	14051689 ps
T118	/workspace/coverage/cover_reg_top/14.uart_tl_errors.2010111008	Jan 10 12:55:40 PM PST 24	Jan 10 12:56:50 PM PST 24	74396326 ps
T119	/workspace/coverage/cover_reg_top/29.uart_intr_test.528390328	Jan 10 12:55:34 PM PST 24	Jan 10 12:56:42 PM PST 24	24545006 ps
T120	/workspace/coverage/cover_reg_top/1.uart_intr_test.1071846988	Jan 10 12:55:12 PM PST 24	Jan 10 12:56:18 PM PST 24	14198029 ps
T121	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1257234726	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:24 PM PST 24	15348681 ps
T122	/workspace/coverage/cover_reg_top/26.uart_intr_test.349648494	Jan 10 12:55:36 PM PST 24	Jan 10 12:56:45 PM PST 24	47971963 ps
T123	/workspace/coverage/cover_reg_top/35.uart_intr_test.422082606	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:16 PM PST 24	12489222 ps
T124	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1075796367	Jan 10 12:55:30 PM PST 24	Jan 10 12:56:37 PM PST 24	58341095 ps
T40	/workspace/coverage/cover_reg_top/3.uart_csr_rw.2830890909	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:23 PM PST 24	46585584 ps
T45	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3644785131	Jan 10 12:55:44 PM PST 24	Jan 10 12:56:53 PM PST 24	55635890 ps
T125	/workspace/coverage/cover_reg_top/48.uart_intr_test.293838391	Jan 10 12:55:42 PM PST 24	Jan 10 12:56:51 PM PST 24	32476506 ps
T46	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.206568078	Jan 10 12:55:10 PM PST 24	Jan 10 12:56:16 PM PST 24	959422952 ps
T126	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.43516512	Jan 10 12:55:27 PM PST 24	Jan 10 12:56:35 PM PST 24	24348054 ps
T127	/workspace/coverage/cover_reg_top/5.uart_intr_test.757357546	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:21 PM PST 24	12186962 ps
T128	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.898829191	Jan 10 12:55:17 PM PST 24	Jan 10 12:56:25 PM PST 24	42705839 ps
T57	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.148204461	Jan 10 12:55:36 PM PST 24	Jan 10 12:56:45 PM PST 24	71885496 ps
T129	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3178397237	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:42 PM PST 24	53179059 ps
T130	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2432470003	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:33 PM PST 24	61293691 ps
T131	/workspace/coverage/cover_reg_top/15.uart_tl_errors.4024654334	Jan 10 12:55:24 PM PST 24	Jan 10 12:56:34 PM PST 24	124251939 ps
T132	/workspace/coverage/cover_reg_top/22.uart_intr_test.248063952	Jan 10 12:55:39 PM PST 24	Jan 10 12:56:47 PM PST 24	26755554 ps
T47	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3779686272	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:20 PM PST 24	30356488 ps
T133	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2799770623	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	36841147 ps
T134	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4048035125	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	19037642 ps
T58	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1705374303	Jan 10 12:55:28 PM PST 24	Jan 10 12:56:35 PM PST 24	42118731 ps
T135	/workspace/coverage/cover_reg_top/24.uart_intr_test.1455209257	Jan 10 12:55:34 PM PST 24	Jan 10 12:56:42 PM PST 24	12665576 ps
T136	/workspace/coverage/cover_reg_top/19.uart_tl_errors.3735285204	Jan 10 12:55:36 PM PST 24	Jan 10 12:56:47 PM PST 24	204651293 ps
T137	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3779136916	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:34 PM PST 24	17891999 ps
T138	/workspace/coverage/cover_reg_top/38.uart_intr_test.2702224547	Jan 10 12:55:35 PM PST 24	Jan 10 12:56:43 PM PST 24	14083968 ps
T139	/workspace/coverage/cover_reg_top/5.uart_tl_errors.2617376972	Jan 10 12:55:17 PM PST 24	Jan 10 12:56:26 PM PST 24	243939254 ps
T140	/workspace/coverage/cover_reg_top/4.uart_intr_test.1631445562	Jan 10 12:55:16 PM PST 24	Jan 10 12:56:24 PM PST 24	90973220 ps
T60	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2062231222	Jan 10 12:55:25 PM PST 24	Jan 10 12:56:33 PM PST 24	177928292 ps
T141	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3104084165	Jan 10 12:55:26 PM PST 24	Jan 10 12:56:35 PM PST 24	363810594 ps
T142	/workspace/coverage/cover_reg_top/12.uart_intr_test.1625567125	Jan 10 12:55:28 PM PST 24	Jan 10 12:56:36 PM PST 24	14656373 ps
T143	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3364784988	Jan 10 12:55:15 PM PST 24	Jan 10 12:56:22 PM PST 24	65181003 ps
T144	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2824716646	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:27 PM PST 24	226032347 ps
T145	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2530476861	Jan 10 12:55:19 PM PST 24	Jan 10 12:56:28 PM PST 24	469941573 ps
T146	/workspace/coverage/cover_reg_top/33.uart_intr_test.934299491	Jan 10 12:55:51 PM PST 24	Jan 10 12:56:59 PM PST 24	23828980 ps
T147	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.818475679	Jan 10 12:55:42 PM PST 24	Jan 10 12:56:51 PM PST 24	62591847 ps
T148	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2057315987	Jan 10 12:55:17 PM PST 24	Jan 10 12:56:25 PM PST 24	61016464 ps
T149	/workspace/coverage/cover_reg_top/3.uart_intr_test.3976555641	Jan 10 12:55:14 PM PST 24	Jan 10 12:56:22 PM PST 24	22857038 ps
T150	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3947587833	Jan 10 12:55:17 PM PST 24	Jan 10 12:56:26 PM PST 24	110523219 ps
T151	/workspace/coverage/cover_reg_top/42.uart_intr_test.2167137609	Jan 10 12:55:40 PM PST 24	Jan 10 12:56:48 PM PST 24	15170481 ps
T152	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.194884287	Jan 10 12:57:05 PM PST 24	Jan 10 12:58:18 PM PST 24	29504928 ps
T153	/workspace/coverage/cover_reg_top/41.uart_intr_test.1575412644	Jan 10 12:55:55 PM PST 24	Jan 10 12:57:04 PM PST 24	55536270 ps
T154	/workspace/coverage/cover_reg_top/32.uart_intr_test.2870244454	Jan 10 12:55:38 PM PST 24	Jan 10 12:56:46 PM PST 24	23449422 ps
T155	/workspace/coverage/cover_reg_top/19.uart_intr_test.3337056261	Jan 10 12:55:33 PM PST 24	Jan 10 12:56:41 PM PST 24	30775622 ps
T156	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3254044430	Jan 10 12:55:30 PM PST 24	Jan 10 12:56:37 PM PST 24	29826552 ps
T157	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2031241013	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:26 PM PST 24	217042393 ps
T48	/workspace/coverage/cover_reg_top/7.uart_csr_rw.243273218	Jan 10 12:55:20 PM PST 24	Jan 10 12:56:28 PM PST 24	73849238 ps
T158	/workspace/coverage/cover_reg_top/47.uart_intr_test.1923780244	Jan 10 12:55:39 PM PST 24	Jan 10 12:56:47 PM PST 24	43988476 ps
T61	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.710776739	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	144769412 ps
T159	/workspace/coverage/cover_reg_top/49.uart_intr_test.588916898	Jan 10 12:55:41 PM PST 24	Jan 10 12:56:50 PM PST 24	52349769 ps
T160	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3746532650	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:32 PM PST 24	83300561 ps
T161	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1498801402	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:26 PM PST 24	109365721 ps
T162	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1863603426	Jan 10 12:55:17 PM PST 24	Jan 10 12:56:25 PM PST 24	103653000 ps
T163	/workspace/coverage/cover_reg_top/3.uart_tl_errors.2427551856	Jan 10 12:55:18 PM PST 24	Jan 10 12:56:27 PM PST 24	148238496 ps
T164	/workspace/coverage/cover_reg_top/9.uart_tl_errors.4042070062	Jan 10 12:55:23 PM PST 24	Jan 10 12:56:33 PM PST 24	335147935 ps
T165	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3863265601	Jan 10 12:55:07 PM PST 24	Jan 10 12:56:13 PM PST 24	27594030 ps

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3221527970
Short name	T1
Test name
Test status
Simulation time	331577603 ps
CPU time	1.3 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	199344 kb
Host	smart-2e302cd4-e5ba-481b-af56-8853b66ae440
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221527970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3221527970
Directory	/workspace/13.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_intr_test.162076025
Short name	T3
Test name
Test status
Simulation time	32902781 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	194348 kb
Host	smart-8f43117a-5669-4b12-b92d-05d8660575be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162076025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.162076025
Directory	/workspace/9.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_errors.384661228
Short name	T14
Test name
Test status
Simulation time	218528400 ps
CPU time	1.5 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	200112 kb
Host	smart-5f48eec7-f73f-467b-8fec-4b619d43b44a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384661228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.384661228
Directory	/workspace/6.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.3556609219
Short name	T4
Test name
Test status
Simulation time	1063697715 ps
CPU time	0.93 seconds
Started	Jan 10 12:55:28 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	195464 kb
Host	smart-a22a4403-9a46-4a62-a924-a5181a7d27d5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556609219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.3556609219
Directory	/workspace/3.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/21.uart_intr_test.3025797654
Short name	T32
Test name
Test status
Simulation time	16723722 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:43 PM PST 24
Peak memory	185136 kb
Host	smart-645c25f2-f3e7-49f8-beae-186df2f9deab
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025797654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3025797654
Directory	/workspace/21.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.206568078
Short name	T46
Test name
Test status
Simulation time	959422952 ps
CPU time	2.5 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:16 PM PST 24
Peak memory	197860 kb
Host	smart-7064428f-e5e1-4027-a2ac-5eda4b79dab2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206568078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.206568078
Directory	/workspace/0.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_errors.1750012917
Short name	T6
Test name
Test status
Simulation time	26158807 ps
CPU time	1.25 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	200088 kb
Host	smart-4dc14ea6-f829-4fae-b4e5-459f72414a91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750012917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1750012917
Directory	/workspace/18.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.167264673
Short name	T34
Test name
Test status
Simulation time	63125525 ps
CPU time	0.62 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195900 kb
Host	smart-d67bd00e-8a12-4837-aaea-b275533c803f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167264673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr _outstanding.167264673
Directory	/workspace/15.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_intg_err.710776739
Short name	T61
Test name
Test status
Simulation time	144769412 ps
CPU time	0.86 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	198828 kb
Host	smart-ead8d305-9c98-4b49-8533-d091f1d8e87c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710776739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.710776739
Directory	/workspace/10.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.148204461
Short name	T57
Test name
Test status
Simulation time	71885496 ps
CPU time	1.28 seconds
Started	Jan 10 12:55:36 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	199280 kb
Host	smart-e9205c64-4c77-4bc9-88bd-9a92729b7380
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148204461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.148204461
Directory	/workspace/18.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/45.uart_intr_test.3270639075
Short name	T9
Test name
Test status
Simulation time	22087700 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:38 PM PST 24
Finished	Jan 10 12:56:46 PM PST 24
Peak memory	194356 kb
Host	smart-a3308b99-512a-4648-8c2d-a5b92c9b1c52
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270639075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.3270639075
Directory	/workspace/45.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2319319189
Short name	T85
Test name
Test status
Simulation time	92887490 ps
CPU time	0.82 seconds
Started	Jan 10 12:55:22 PM PST 24
Finished	Jan 10 12:56:31 PM PST 24
Peak memory	199580 kb
Host	smart-30ee79bb-5eb4-41cd-ac44-7c1cdca13f7e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319319189 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2319319189
Directory	/workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1097135281
Short name	T13
Test name
Test status
Simulation time	83698407 ps
CPU time	0.66 seconds
Started	Jan 10 12:55:07 PM PST 24
Finished	Jan 10 12:56:12 PM PST 24
Peak memory	195456 kb
Host	smart-41c88c33-8fdb-4fea-bbbf-06f3f7598f8f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097135281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1097135281
Directory	/workspace/0.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.4058421423
Short name	T52
Test name
Test status
Simulation time	15403599 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:15 PM PST 24
Peak memory	195540 kb
Host	smart-4c53a192-69b7-490d-ae40-1f05a81cd897
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058421423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.4058421423
Directory	/workspace/0.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.4073817797
Short name	T69
Test name
Test status
Simulation time	92977623 ps
CPU time	1.07 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:15 PM PST 24
Peak memory	200092 kb
Host	smart-c661cd8e-a870-4120-98b6-2bb7484059ec
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073817797 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.4073817797
Directory	/workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_csr_rw.847670402
Short name	T12
Test name
Test status
Simulation time	34665186 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:15 PM PST 24
Peak memory	195468 kb
Host	smart-56165629-a981-4dd5-91ba-dc7da334f3e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847670402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.847670402
Directory	/workspace/0.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_intr_test.4274385492
Short name	T114
Test name
Test status
Simulation time	32034398 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:09 PM PST 24
Finished	Jan 10 12:56:14 PM PST 24
Peak memory	185180 kb
Host	smart-63d8b117-f8ec-4ac3-a8f7-81698256ff1a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274385492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4274385492
Directory	/workspace/0.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.3863265601
Short name	T165
Test name
Test status
Simulation time	27594030 ps
CPU time	0.74 seconds
Started	Jan 10 12:55:07 PM PST 24
Finished	Jan 10 12:56:13 PM PST 24
Peak memory	197024 kb
Host	smart-04a639b3-2189-43f0-a1d1-b84fe36efc4e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863265601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.3863265601
Directory	/workspace/0.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_errors.3872861947
Short name	T90
Test name
Test status
Simulation time	167296798 ps
CPU time	2.13 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:16 PM PST 24
Peak memory	200088 kb
Host	smart-8ff6ed85-dbbd-43fe-a09b-242847a4d062
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872861947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3872861947
Directory	/workspace/0.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1146826395
Short name	T62
Test name
Test status
Simulation time	1605896986 ps
CPU time	1.43 seconds
Started	Jan 10 12:55:08 PM PST 24
Finished	Jan 10 12:56:14 PM PST 24
Peak memory	199068 kb
Host	smart-deba73fb-ea93-401e-8964-1d1a51a9ff7a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146826395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1146826395
Directory	/workspace/0.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3779686272
Short name	T47
Test name
Test status
Simulation time	30356488 ps
CPU time	0.83 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:20 PM PST 24
Peak memory	196376 kb
Host	smart-e6686758-a5e6-4b19-baf2-dfd39e44cf31
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779686272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3779686272
Directory	/workspace/1.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2824716646
Short name	T144
Test name
Test status
Simulation time	226032347 ps
CPU time	1.41 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	197564 kb
Host	smart-d3cc6e83-8308-4420-afa8-c71afcf06c4a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824716646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2824716646
Directory	/workspace/1.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.3943976189
Short name	T53
Test name
Test status
Simulation time	16307029 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:06 PM PST 24
Finished	Jan 10 12:56:12 PM PST 24
Peak memory	195536 kb
Host	smart-1d44b98a-77ff-414c-a842-6c589b2a2e0e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943976189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.3943976189
Directory	/workspace/1.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3364784988
Short name	T143
Test name
Test status
Simulation time	65181003 ps
CPU time	0.76 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	199844 kb
Host	smart-353c78bb-3e99-4c54-a88c-719f1f1994d9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364784988 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3364784988
Directory	/workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_csr_rw.3137186111
Short name	T92
Test name
Test status
Simulation time	78322729 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:09 PM PST 24
Finished	Jan 10 12:56:14 PM PST 24
Peak memory	195456 kb
Host	smart-db8bf079-1fe7-46f4-94a1-1774c1f7c65e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137186111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3137186111
Directory	/workspace/1.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_intr_test.1071846988
Short name	T120
Test name
Test status
Simulation time	14198029 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:12 PM PST 24
Finished	Jan 10 12:56:18 PM PST 24
Peak memory	185116 kb
Host	smart-83390f14-fa14-4abd-8dd5-3297b319483a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071846988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1071846988
Directory	/workspace/1.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1353641959
Short name	T112
Test name
Test status
Simulation time	68020598 ps
CPU time	0.74 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	197168 kb
Host	smart-2e288064-60cd-4fd1-a0d1-afb909667fd7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353641959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.1353641959
Directory	/workspace/1.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_errors.2146998819
Short name	T20
Test name
Test status
Simulation time	275275732 ps
CPU time	1.58 seconds
Started	Jan 10 12:55:10 PM PST 24
Finished	Jan 10 12:56:16 PM PST 24
Peak memory	200088 kb
Host	smart-a6a9632d-26d5-422d-ae9d-a71bc0c6cbc2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146998819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2146998819
Directory	/workspace/1.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.559310350
Short name	T55
Test name
Test status
Simulation time	48778795 ps
CPU time	0.98 seconds
Started	Jan 10 12:55:09 PM PST 24
Finished	Jan 10 12:56:14 PM PST 24
Peak memory	199212 kb
Host	smart-394f3368-53e2-4829-aef4-6686a10cf16b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559310350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.559310350
Directory	/workspace/1.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2432470003
Short name	T130
Test name
Test status
Simulation time	61293691 ps
CPU time	0.64 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	196468 kb
Host	smart-c80a96a8-ec74-46cf-9827-d650b99804f3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432470003 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2432470003
Directory	/workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_csr_rw.2794898942
Short name	T23
Test name
Test status
Simulation time	171029919 ps
CPU time	0.61 seconds
Started	Jan 10 12:55:27 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	195572 kb
Host	smart-1b6d9623-3e93-4f0f-bea0-3976c33f8d87
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794898942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2794898942
Directory	/workspace/10.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_intr_test.1106468104
Short name	T43
Test name
Test status
Simulation time	67382026 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:28 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	194428 kb
Host	smart-b934fd05-bc3c-458e-a7e0-b4c5ba403423
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106468104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1106468104
Directory	/workspace/10.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3254044430
Short name	T156
Test name
Test status
Simulation time	29826552 ps
CPU time	0.67 seconds
Started	Jan 10 12:55:30 PM PST 24
Finished	Jan 10 12:56:37 PM PST 24
Peak memory	195732 kb
Host	smart-03c286cd-adf8-42b4-809a-52c31f498794
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254044430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3254044430
Directory	/workspace/10.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.uart_tl_errors.1044854220
Short name	T107
Test name
Test status
Simulation time	122263269 ps
CPU time	1.8 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	200000 kb
Host	smart-9f248eb1-8e12-4a54-b389-0b5993143740
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044854220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.1044854220
Directory	/workspace/10.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1075796367
Short name	T124
Test name
Test status
Simulation time	58341095 ps
CPU time	0.77 seconds
Started	Jan 10 12:55:30 PM PST 24
Finished	Jan 10 12:56:37 PM PST 24
Peak memory	199392 kb
Host	smart-527f4543-83b5-4ae7-bceb-bf78ffe82330
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075796367 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1075796367
Directory	/workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_csr_rw.2822045122
Short name	T71
Test name
Test status
Simulation time	43320030 ps
CPU time	0.6 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195452 kb
Host	smart-db1ba376-5935-4ec7-ad2b-43481c0b615d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822045122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2822045122
Directory	/workspace/11.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_intr_test.2239675037
Short name	T95
Test name
Test status
Simulation time	40546320 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	185116 kb
Host	smart-2976f04c-416e-4767-9641-3ee87697397c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239675037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2239675037
Directory	/workspace/11.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.4122760563
Short name	T89
Test name
Test status
Simulation time	32066743 ps
CPU time	0.62 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195888 kb
Host	smart-192bef11-9a1b-4728-9226-3283a8c1e16b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122760563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.4122760563
Directory	/workspace/11.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_errors.2266840056
Short name	T104
Test name
Test status
Simulation time	238951356 ps
CPU time	1.27 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	200052 kb
Host	smart-b41d4cd3-2810-4d8c-a816-62fc26295ce1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266840056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2266840056
Directory	/workspace/11.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.3104084165
Short name	T141
Test name
Test status
Simulation time	363810594 ps
CPU time	1.34 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	199512 kb
Host	smart-ed790c31-60f4-4d56-8ada-5cc8160c85de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104084165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.3104084165
Directory	/workspace/11.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1807042087
Short name	T19
Test name
Test status
Simulation time	29094773 ps
CPU time	1.5 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	200144 kb
Host	smart-77531c85-f49d-4ebb-a09f-dc6f48221e6a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807042087 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1807042087
Directory	/workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_csr_rw.2614765234
Short name	T105
Test name
Test status
Simulation time	13842221 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	195532 kb
Host	smart-fa0a06c1-af9a-48ee-bd12-9cce7a159103
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614765234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2614765234
Directory	/workspace/12.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_intr_test.1625567125
Short name	T142
Test name
Test status
Simulation time	14656373 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:28 PM PST 24
Finished	Jan 10 12:56:36 PM PST 24
Peak memory	185172 kb
Host	smart-7dd048d6-b8f1-4018-9cac-2cae4c27501e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625567125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1625567125
Directory	/workspace/12.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.4252676741
Short name	T29
Test name
Test status
Simulation time	28419254 ps
CPU time	0.72 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	196892 kb
Host	smart-58ba5946-87dc-41aa-8b6d-3f03b673be8b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252676741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.4252676741
Directory	/workspace/12.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_errors.1433113240
Short name	T83
Test name
Test status
Simulation time	68842924 ps
CPU time	1.4 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	200124 kb
Host	smart-7e372d69-2471-40a4-a9c7-4ac7d216d4e5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433113240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1433113240
Directory	/workspace/12.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3895548743
Short name	T84
Test name
Test status
Simulation time	50594427 ps
CPU time	0.98 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:36 PM PST 24
Peak memory	199012 kb
Host	smart-a7269808-559a-4fe1-9974-b6290aff7780
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895548743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3895548743
Directory	/workspace/12.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3706333476
Short name	T113
Test name
Test status
Simulation time	88260495 ps
CPU time	0.79 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:31 PM PST 24
Peak memory	199604 kb
Host	smart-39cd6662-6cf1-41a0-b635-7501ed564585
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706333476 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3706333476
Directory	/workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_csr_rw.3860420304
Short name	T88
Test name
Test status
Simulation time	31139802 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195568 kb
Host	smart-b5d2ce94-5845-4a54-8764-6c737080ff83
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860420304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3860420304
Directory	/workspace/13.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_intr_test.1145118287
Short name	T66
Test name
Test status
Simulation time	40852844 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	185164 kb
Host	smart-036522d5-7ca3-4aa9-a5bd-b37a45dd73c6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145118287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.1145118287
Directory	/workspace/13.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3779136916
Short name	T137
Test name
Test status
Simulation time	17891999 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	195500 kb
Host	smart-a4f81f25-a357-4874-90de-aa06d086c065
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779136916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.3779136916
Directory	/workspace/13.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.uart_tl_errors.3471437346
Short name	T15
Test name
Test status
Simulation time	331015978 ps
CPU time	1.67 seconds
Started	Jan 10 12:55:30 PM PST 24
Finished	Jan 10 12:56:39 PM PST 24
Peak memory	200100 kb
Host	smart-eed1a4bd-d25b-4e96-ae40-e0527359f711
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471437346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3471437346
Directory	/workspace/13.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.43516512
Short name	T126
Test name
Test status
Simulation time	24348054 ps
CPU time	0.8 seconds
Started	Jan 10 12:55:27 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	199096 kb
Host	smart-1c53d686-615e-49c5-b19e-82c8a41713ae
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43516512 -assert nopostproc +UVM_TESTNAME=u art_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.43516512
Directory	/workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_csr_rw.863755111
Short name	T28
Test name
Test status
Simulation time	22279058 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195540 kb
Host	smart-c627afa5-c1f5-4b12-88ed-6ce8941002e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863755111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.863755111
Directory	/workspace/14.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_intr_test.333714680
Short name	T108
Test name
Test status
Simulation time	22645025 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	194416 kb
Host	smart-39805ffd-ca4b-497c-88d1-1881287c4bb2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333714680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.333714680
Directory	/workspace/14.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2009110878
Short name	T68
Test name
Test status
Simulation time	19199285 ps
CPU time	0.64 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195592 kb
Host	smart-14072d03-9e7b-44a0-a0ca-9b9b56faf905
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009110878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.2009110878
Directory	/workspace/14.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_errors.2010111008
Short name	T118
Test name
Test status
Simulation time	74396326 ps
CPU time	1.51 seconds
Started	Jan 10 12:55:40 PM PST 24
Finished	Jan 10 12:56:50 PM PST 24
Peak memory	200088 kb
Host	smart-bb29303c-5e69-4478-9e4c-fac7004f9d7e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010111008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2010111008
Directory	/workspace/14.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3746532650
Short name	T160
Test name
Test status
Simulation time	83300561 ps
CPU time	0.98 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	198916 kb
Host	smart-cbd14dc5-4872-4864-999a-5bd0e58b9bbc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746532650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3746532650
Directory	/workspace/14.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3557783999
Short name	T64
Test name
Test status
Simulation time	14863600 ps
CPU time	0.73 seconds
Started	Jan 10 12:55:27 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	197912 kb
Host	smart-bfc20f7c-0d2a-4504-be3f-77cc4356e22f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557783999 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3557783999
Directory	/workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_csr_rw.465324907
Short name	T30
Test name
Test status
Simulation time	12849301 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	195508 kb
Host	smart-d6da9c10-8ffe-4754-b61d-b6533356403b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465324907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.465324907
Directory	/workspace/15.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_intr_test.1060433400
Short name	T49
Test name
Test status
Simulation time	46137133 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	185156 kb
Host	smart-549f8ccb-987f-4db8-8fd5-4df8d64fb94d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060433400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1060433400
Directory	/workspace/15.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_errors.4024654334
Short name	T131
Test name
Test status
Simulation time	124251939 ps
CPU time	1.86 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	200076 kb
Host	smart-498b3118-51d9-4e11-aa53-1ceac373138a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024654334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.4024654334
Directory	/workspace/15.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.694796125
Short name	T21
Test name
Test status
Simulation time	121032296 ps
CPU time	1.3 seconds
Started	Jan 10 12:55:26 PM PST 24
Finished	Jan 10 12:56:34 PM PST 24
Peak memory	199124 kb
Host	smart-df72cf76-2fc3-4d03-8e30-36e146efb555
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694796125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.694796125
Directory	/workspace/15.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.4048035125
Short name	T134
Test name
Test status
Simulation time	19037642 ps
CPU time	0.73 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	199072 kb
Host	smart-42b379c6-6500-42bf-9ccb-bc42d87b1a4c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048035125 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.4048035125
Directory	/workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_csr_rw.768078644
Short name	T7
Test name
Test status
Simulation time	35908804 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	195452 kb
Host	smart-2fc7db8a-8c6d-48f0-802c-2fbd088d9500
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768078644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.768078644
Directory	/workspace/16.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_intr_test.3073124710
Short name	T75
Test name
Test status
Simulation time	50353375 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:52 PM PST 24
Finished	Jan 10 12:57:00 PM PST 24
Peak memory	194324 kb
Host	smart-6a753037-65a3-4bba-8829-b3f9529dbdc6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073124710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3073124710
Directory	/workspace/16.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.818475679
Short name	T147
Test name
Test status
Simulation time	62591847 ps
CPU time	0.75 seconds
Started	Jan 10 12:55:42 PM PST 24
Finished	Jan 10 12:56:51 PM PST 24
Peak memory	197000 kb
Host	smart-ff15b53c-1237-48a5-b3da-78b0f22f9804
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818475679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr _outstanding.818475679
Directory	/workspace/16.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_errors.3816117640
Short name	T22
Test name
Test status
Simulation time	42734972 ps
CPU time	1.32 seconds
Started	Jan 10 12:55:30 PM PST 24
Finished	Jan 10 12:56:38 PM PST 24
Peak memory	200108 kb
Host	smart-27a833da-665d-487c-a5eb-aa5bb288c2fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816117640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3816117640
Directory	/workspace/16.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2062231222
Short name	T60
Test name
Test status
Simulation time	177928292 ps
CPU time	0.96 seconds
Started	Jan 10 12:55:25 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	199164 kb
Host	smart-8f67c715-c787-470a-b3b5-288fdb848423
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062231222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2062231222
Directory	/workspace/16.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2418806363
Short name	T18
Test name
Test status
Simulation time	64394616 ps
CPU time	0.7 seconds
Started	Jan 10 12:55:43 PM PST 24
Finished	Jan 10 12:56:52 PM PST 24
Peak memory	196936 kb
Host	smart-cea79f16-891e-48ac-a90e-9497be004792
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418806363 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2418806363
Directory	/workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_csr_rw.1699618328
Short name	T38
Test name
Test status
Simulation time	24493512 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:32 PM PST 24
Finished	Jan 10 12:56:39 PM PST 24
Peak memory	195712 kb
Host	smart-8994c702-17c8-4b9f-9896-53c492756659
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699618328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1699618328
Directory	/workspace/17.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_intr_test.3346754958
Short name	T86
Test name
Test status
Simulation time	39470226 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:43 PM PST 24
Peak memory	185124 kb
Host	smart-8a514c2a-cb0d-4176-be1d-a81eb69a9beb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346754958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3346754958
Directory	/workspace/17.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3239021595
Short name	T78
Test name
Test status
Simulation time	63590130 ps
CPU time	0.62 seconds
Started	Jan 10 12:55:50 PM PST 24
Finished	Jan 10 12:56:58 PM PST 24
Peak memory	195552 kb
Host	smart-7ae9ab88-e16c-4cd3-8501-aec5dfadd11e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239021595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.3239021595
Directory	/workspace/17.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_errors.1867614746
Short name	T87
Test name
Test status
Simulation time	54164124 ps
CPU time	1.28 seconds
Started	Jan 10 12:55:36 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	199920 kb
Host	smart-26f4a422-8905-4db5-a12e-46d8966d50e8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867614746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1867614746
Directory	/workspace/17.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.4177248581
Short name	T59
Test name
Test status
Simulation time	44619257 ps
CPU time	0.89 seconds
Started	Jan 10 12:55:54 PM PST 24
Finished	Jan 10 12:57:03 PM PST 24
Peak memory	198616 kb
Host	smart-f2333d82-36c0-4634-9751-6e24c8c770d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177248581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.4177248581
Directory	/workspace/17.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1415872179
Short name	T79
Test name
Test status
Simulation time	29129918 ps
CPU time	0.8 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	198944 kb
Host	smart-557e017f-8721-4c72-9ebe-d35332d1fb78
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415872179 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1415872179
Directory	/workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_csr_rw.3644785131
Short name	T45
Test name
Test status
Simulation time	55635890 ps
CPU time	0.61 seconds
Started	Jan 10 12:55:44 PM PST 24
Finished	Jan 10 12:56:53 PM PST 24
Peak memory	195520 kb
Host	smart-f5aedd35-f02b-4d0c-8076-6e462a29bd59
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644785131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3644785131
Directory	/workspace/18.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_intr_test.2284196033
Short name	T102
Test name
Test status
Simulation time	58490969 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	194336 kb
Host	smart-345a487c-0ffa-43ed-83dc-59e4e9ec2a53
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284196033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2284196033
Directory	/workspace/18.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3178397237
Short name	T129
Test name
Test status
Simulation time	53179059 ps
CPU time	0.74 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	197004 kb
Host	smart-3d3e4af7-94dd-4cb4-a94d-303c4d3dd4d8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178397237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3178397237
Directory	/workspace/18.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.1360249745
Short name	T80
Test name
Test status
Simulation time	16200925 ps
CPU time	0.68 seconds
Started	Jan 10 12:55:39 PM PST 24
Finished	Jan 10 12:56:47 PM PST 24
Peak memory	198064 kb
Host	smart-6595d169-dfd9-4342-a5b7-e59699145358
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360249745 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.1360249745
Directory	/workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_csr_rw.3056332191
Short name	T27
Test name
Test status
Simulation time	14137425 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:34 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	195560 kb
Host	smart-c1f47c72-9374-42e3-9283-ebb5275d924f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056332191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3056332191
Directory	/workspace/19.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_intr_test.3337056261
Short name	T155
Test name
Test status
Simulation time	30775622 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	194352 kb
Host	smart-7ec9e757-84c5-45b6-a8e4-96fa0c360d28
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337056261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3337056261
Directory	/workspace/19.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.941286732
Short name	T103
Test name
Test status
Simulation time	31670830 ps
CPU time	0.74 seconds
Started	Jan 10 12:55:32 PM PST 24
Finished	Jan 10 12:56:40 PM PST 24
Peak memory	197152 kb
Host	smart-f5869ddf-31a2-425d-9aa7-0a6306223612
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941286732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr _outstanding.941286732
Directory	/workspace/19.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_errors.3735285204
Short name	T136
Test name
Test status
Simulation time	204651293 ps
CPU time	1.74 seconds
Started	Jan 10 12:55:36 PM PST 24
Finished	Jan 10 12:56:47 PM PST 24
Peak memory	200080 kb
Host	smart-127d1a91-aa9e-4a6f-9086-3f77e250083b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735285204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3735285204
Directory	/workspace/19.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2373546420
Short name	T56
Test name
Test status
Simulation time	294420743 ps
CPU time	1.25 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	199232 kb
Host	smart-05cd039c-2304-48c4-9c5a-20d17757e471
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373546420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2373546420
Directory	/workspace/19.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2359886580
Short name	T31
Test name
Test status
Simulation time	20200230 ps
CPU time	0.66 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	195116 kb
Host	smart-f3efc502-9dc1-4cb4-b982-09e64b2f5091
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359886580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2359886580
Directory	/workspace/2.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3846191027
Short name	T101
Test name
Test status
Simulation time	184146824 ps
CPU time	2.46 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:29 PM PST 24
Peak memory	197872 kb
Host	smart-caa87122-4a1f-43d2-a7a4-01c25f964992
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846191027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3846191027
Directory	/workspace/2.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1863257306
Short name	T39
Test name
Test status
Simulation time	13106586 ps
CPU time	0.6 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:21 PM PST 24
Peak memory	195548 kb
Host	smart-6697aafb-5edd-4292-a05f-dcb7d68783c2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863257306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1863257306
Directory	/workspace/2.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1228669930
Short name	T106
Test name
Test status
Simulation time	51919957 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	196464 kb
Host	smart-180ae35b-157a-4c62-b321-774299e4dff1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228669930 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1228669930
Directory	/workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_csr_rw.1056572142
Short name	T51
Test name
Test status
Simulation time	23320811 ps
CPU time	0.6 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:21 PM PST 24
Peak memory	195560 kb
Host	smart-21a1ea88-a1d1-4b31-af28-613d3c88ff54
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056572142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1056572142
Directory	/workspace/2.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_intr_test.1769067219
Short name	T50
Test name
Test status
Simulation time	43250661 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:21 PM PST 24
Peak memory	185168 kb
Host	smart-34a4e4fc-bf94-48c4-812e-55808f9bccdb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769067219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1769067219
Directory	/workspace/2.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.711429564
Short name	T25
Test name
Test status
Simulation time	38194235 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:20 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	195612 kb
Host	smart-90cd372c-7109-4981-9738-adcec42c6506
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711429564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_ outstanding.711429564
Directory	/workspace/2.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_errors.2530476861
Short name	T145
Test name
Test status
Simulation time	469941573 ps
CPU time	2.07 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	200144 kb
Host	smart-32d16fc9-edc9-4eb1-9c93-68877605f878
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530476861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2530476861
Directory	/workspace/2.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1498801402
Short name	T161
Test name
Test status
Simulation time	109365721 ps
CPU time	0.94 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	198892 kb
Host	smart-baa46244-bc07-4d43-9319-f56cc453e3ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498801402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1498801402
Directory	/workspace/2.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.uart_intr_test.4120984182
Short name	T65
Test name
Test status
Simulation time	51752789 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	194388 kb
Host	smart-5ee8a4ca-c71f-4c49-a018-025ca15be709
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120984182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4120984182
Directory	/workspace/20.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.uart_intr_test.248063952
Short name	T132
Test name
Test status
Simulation time	26755554 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:39 PM PST 24
Finished	Jan 10 12:56:47 PM PST 24
Peak memory	194436 kb
Host	smart-85b21b3c-f3a9-47fb-ba20-f5fd2e3bfa89
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248063952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.248063952
Directory	/workspace/22.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.uart_intr_test.3865631720
Short name	T117
Test name
Test status
Simulation time	14051689 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:36 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	185076 kb
Host	smart-0d9f3fb8-ea27-4620-abe8-73680960aaa2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865631720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3865631720
Directory	/workspace/23.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.uart_intr_test.1455209257
Short name	T135
Test name
Test status
Simulation time	12665576 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:34 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185112 kb
Host	smart-de841c0a-c1d0-43d3-93ff-8bf7f7d9fe9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455209257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1455209257
Directory	/workspace/24.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.uart_intr_test.2187457481
Short name	T44
Test name
Test status
Simulation time	13999800 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:43 PM PST 24
Peak memory	185200 kb
Host	smart-03a6620b-2add-4302-bfb4-3e50d64aec68
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187457481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2187457481
Directory	/workspace/25.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.uart_intr_test.349648494
Short name	T122
Test name
Test status
Simulation time	47971963 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:36 PM PST 24
Finished	Jan 10 12:56:45 PM PST 24
Peak memory	185204 kb
Host	smart-47fd9be8-0dfd-4898-907a-3414832fa881
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349648494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.349648494
Directory	/workspace/26.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.uart_intr_test.3709397627
Short name	T115
Test name
Test status
Simulation time	23006385 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:34 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185080 kb
Host	smart-0f1926f0-01fe-48b7-80ad-ed5c37d99837
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709397627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3709397627
Directory	/workspace/27.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.uart_intr_test.3337353494
Short name	T5
Test name
Test status
Simulation time	14338656 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:38 PM PST 24
Finished	Jan 10 12:56:46 PM PST 24
Peak memory	185116 kb
Host	smart-6d17e701-9858-4588-8f8b-e070dc182e34
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337353494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3337353494
Directory	/workspace/28.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.uart_intr_test.528390328
Short name	T119
Test name
Test status
Simulation time	24545006 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:34 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185108 kb
Host	smart-8b11c84a-edf8-460a-9d9a-279f05f9edbe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528390328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.528390328
Directory	/workspace/29.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2082832418
Short name	T72
Test name
Test status
Simulation time	38384822 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	194752 kb
Host	smart-db11befd-43b4-4a0f-831f-bc055ab22bf4
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082832418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2082832418
Directory	/workspace/3.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.4248457826
Short name	T81
Test name
Test status
Simulation time	257294352 ps
CPU time	2.6 seconds
Started	Jan 10 12:55:13 PM PST 24
Finished	Jan 10 12:56:21 PM PST 24
Peak memory	197940 kb
Host	smart-57e35eb0-2283-49ab-8e8b-2557689e1169
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248457826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.4248457826
Directory	/workspace/3.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1257234726
Short name	T121
Test name
Test status
Simulation time	15348681 ps
CPU time	0.72 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:24 PM PST 24
Peak memory	197808 kb
Host	smart-a307a8a8-9486-486b-afc5-41f066574905
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257234726 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1257234726
Directory	/workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_csr_rw.2830890909
Short name	T40
Test name
Test status
Simulation time	46585584 ps
CPU time	0.62 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:23 PM PST 24
Peak memory	195632 kb
Host	smart-cfcb5cba-f850-495e-8308-01cd85a4e8ef
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830890909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2830890909
Directory	/workspace/3.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_intr_test.3976555641
Short name	T149
Test name
Test status
Simulation time	22857038 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	194416 kb
Host	smart-c1b91c61-b4fd-4820-ac73-3d7cc4ed446e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976555641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.3976555641
Directory	/workspace/3.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2799770623
Short name	T133
Test name
Test status
Simulation time	36841147 ps
CPU time	0.69 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	195532 kb
Host	smart-6e210ae3-6d46-42cd-99fb-9ff798ae68fe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799770623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.2799770623
Directory	/workspace/3.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_errors.2427551856
Short name	T163
Test name
Test status
Simulation time	148238496 ps
CPU time	2.06 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	200084 kb
Host	smart-dabba412-1472-4a22-b31d-ea442b01f36e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427551856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2427551856
Directory	/workspace/3.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.1610775041
Short name	T116
Test name
Test status
Simulation time	50595049 ps
CPU time	0.89 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	199080 kb
Host	smart-052e457b-53cf-43f8-922a-179dfca8ff3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610775041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.1610775041
Directory	/workspace/3.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.uart_intr_test.3559799701
Short name	T93
Test name
Test status
Simulation time	58532215 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185168 kb
Host	smart-e09bb43c-13ea-496c-a38e-c0fe9f2b686a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559799701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3559799701
Directory	/workspace/30.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.uart_intr_test.2937356661
Short name	T24
Test name
Test status
Simulation time	38259154 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	185108 kb
Host	smart-26d8da90-f85f-4c8b-bb6d-cc5b68c8b349
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937356661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2937356661
Directory	/workspace/31.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.uart_intr_test.2870244454
Short name	T154
Test name
Test status
Simulation time	23449422 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:38 PM PST 24
Finished	Jan 10 12:56:46 PM PST 24
Peak memory	185184 kb
Host	smart-5ec9c696-fc1a-4a1d-8fd7-016ed9f76dc0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870244454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2870244454
Directory	/workspace/32.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.uart_intr_test.934299491
Short name	T146
Test name
Test status
Simulation time	23828980 ps
CPU time	0.53 seconds
Started	Jan 10 12:55:51 PM PST 24
Finished	Jan 10 12:56:59 PM PST 24
Peak memory	185196 kb
Host	smart-54f0b6ec-7d7a-4aff-af6c-b4bf75dbcb2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934299491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.934299491
Directory	/workspace/33.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.uart_intr_test.2829888972
Short name	T111
Test name
Test status
Simulation time	13579876 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185184 kb
Host	smart-1fae40dd-6de4-46be-974f-de496ee352de
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829888972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2829888972
Directory	/workspace/34.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.uart_intr_test.422082606
Short name	T123
Test name
Test status
Simulation time	12489222 ps
CPU time	0.55 seconds
Started	Jan 10 12:56:05 PM PST 24
Finished	Jan 10 12:57:16 PM PST 24
Peak memory	185284 kb
Host	smart-ae5ffcbe-1f35-4d61-afac-a9adab790bb4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422082606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.422082606
Directory	/workspace/35.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.uart_intr_test.522973795
Short name	T109
Test name
Test status
Simulation time	30151601 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:42 PM PST 24
Peak memory	185180 kb
Host	smart-b69d0195-507d-4df2-abf4-786644c1ea4f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522973795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.522973795
Directory	/workspace/36.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.uart_intr_test.53022101
Short name	T96
Test name
Test status
Simulation time	93167314 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:41 PM PST 24
Finished	Jan 10 12:56:49 PM PST 24
Peak memory	185084 kb
Host	smart-6d8a63e7-d5e5-432a-b03a-314865ae249d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53022101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.53022101
Directory	/workspace/37.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.uart_intr_test.2702224547
Short name	T138
Test name
Test status
Simulation time	14083968 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:43 PM PST 24
Peak memory	194436 kb
Host	smart-10e72cd4-a374-4b15-9614-9960bd20495c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702224547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.2702224547
Directory	/workspace/38.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.uart_intr_test.1438686553
Short name	T91
Test name
Test status
Simulation time	41560765 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:33 PM PST 24
Finished	Jan 10 12:56:41 PM PST 24
Peak memory	185184 kb
Host	smart-c904c42c-9008-4984-9413-d7004e43d87f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438686553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1438686553
Directory	/workspace/39.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.1424135630
Short name	T36
Test name
Test status
Simulation time	201044601 ps
CPU time	0.68 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:20 PM PST 24
Peak memory	194888 kb
Host	smart-2e393d5b-6381-473a-9348-0bcc386e88be
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424135630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.1424135630
Directory	/workspace/4.uart_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3947587833
Short name	T150
Test name
Test status
Simulation time	110523219 ps
CPU time	2.31 seconds
Started	Jan 10 12:55:17 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	198032 kb
Host	smart-0176d013-7814-4586-9b89-77ff3ab25d37
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947587833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3947587833
Directory	/workspace/4.uart_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.561108881
Short name	T37
Test name
Test status
Simulation time	15141655 ps
CPU time	0.6 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	195556 kb
Host	smart-017f331d-386d-47ab-9bee-3ca8e6420b86
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561108881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.561108881
Directory	/workspace/4.uart_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.763378147
Short name	T94
Test name
Test status
Simulation time	28563339 ps
CPU time	0.68 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:24 PM PST 24
Peak memory	196932 kb
Host	smart-df721ec2-1489-49d3-ae29-51a752ecd5bc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763378147 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.763378147
Directory	/workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_csr_rw.3424922397
Short name	T33
Test name
Test status
Simulation time	43811330 ps
CPU time	0.59 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	195552 kb
Host	smart-c01f3726-cc34-4acc-8b8d-42583bbfbca7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424922397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3424922397
Directory	/workspace/4.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_intr_test.1631445562
Short name	T140
Test name
Test status
Simulation time	90973220 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:24 PM PST 24
Peak memory	185120 kb
Host	smart-b2d524fa-dc27-40f1-bb79-798df24b604e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631445562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1631445562
Directory	/workspace/4.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4090020864
Short name	T98
Test name
Test status
Simulation time	29755808 ps
CPU time	0.72 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	195956 kb
Host	smart-6cdc0f5f-dbd8-46f6-a8bb-1ed0f3e05297
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090020864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.4090020864
Directory	/workspace/4.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_errors.2573343889
Short name	T11
Test name
Test status
Simulation time	121503362 ps
CPU time	1.65 seconds
Started	Jan 10 12:55:20 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	199972 kb
Host	smart-6d42d152-8fee-41b4-8f80-049d8f07dd50
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573343889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2573343889
Directory	/workspace/4.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2674217589
Short name	T54
Test name
Test status
Simulation time	372110866 ps
CPU time	1.28 seconds
Started	Jan 10 12:55:19 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	199248 kb
Host	smart-ce69617b-658c-4af5-a286-6b9f2b74c5f1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674217589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2674217589
Directory	/workspace/4.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.uart_intr_test.2464474
Short name	T10
Test name
Test status
Simulation time	37408972 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:42 PM PST 24
Finished	Jan 10 12:56:50 PM PST 24
Peak memory	185184 kb
Host	smart-a224fa40-3804-4af5-a7f6-20fac327f8f8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2464474
Directory	/workspace/40.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.uart_intr_test.1575412644
Short name	T153
Test name
Test status
Simulation time	55536270 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:55 PM PST 24
Finished	Jan 10 12:57:04 PM PST 24
Peak memory	185216 kb
Host	smart-9c2736fe-f496-4ab5-ba86-ad6ac33b44b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575412644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.1575412644
Directory	/workspace/41.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.uart_intr_test.2167137609
Short name	T151
Test name
Test status
Simulation time	15170481 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:40 PM PST 24
Finished	Jan 10 12:56:48 PM PST 24
Peak memory	185112 kb
Host	smart-92ed6408-ceee-4bb9-a34b-6c7634362fcd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167137609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2167137609
Directory	/workspace/42.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.uart_intr_test.3375989842
Short name	T63
Test name
Test status
Simulation time	51501834 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:53 PM PST 24
Finished	Jan 10 12:57:01 PM PST 24
Peak memory	185180 kb
Host	smart-79880507-b57c-471a-ac51-509bdfe3bfd4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375989842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3375989842
Directory	/workspace/43.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.uart_intr_test.3259424108
Short name	T74
Test name
Test status
Simulation time	46956254 ps
CPU time	0.55 seconds
Started	Jan 10 12:55:35 PM PST 24
Finished	Jan 10 12:56:43 PM PST 24
Peak memory	194336 kb
Host	smart-92d9e393-0568-497f-9903-7e5a5fcaee66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259424108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3259424108
Directory	/workspace/44.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.uart_intr_test.38920585
Short name	T8
Test name
Test status
Simulation time	23487386 ps
CPU time	0.58 seconds
Started	Jan 10 12:55:41 PM PST 24
Finished	Jan 10 12:56:51 PM PST 24
Peak memory	185132 kb
Host	smart-4c8f27bf-a396-4dbd-86f7-d2be6b4bfa66
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38920585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.38920585
Directory	/workspace/46.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.uart_intr_test.1923780244
Short name	T158
Test name
Test status
Simulation time	43988476 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:39 PM PST 24
Finished	Jan 10 12:56:47 PM PST 24
Peak memory	194316 kb
Host	smart-5d826c7d-0cde-46ed-b86e-9c171f9f1ace
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923780244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1923780244
Directory	/workspace/47.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.uart_intr_test.293838391
Short name	T125
Test name
Test status
Simulation time	32476506 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:42 PM PST 24
Finished	Jan 10 12:56:51 PM PST 24
Peak memory	185092 kb
Host	smart-55b6be51-0fee-40d2-871e-393846de2f48
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293838391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.293838391
Directory	/workspace/48.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.uart_intr_test.588916898
Short name	T159
Test name
Test status
Simulation time	52349769 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:41 PM PST 24
Finished	Jan 10 12:56:50 PM PST 24
Peak memory	185140 kb
Host	smart-5a474b27-d302-4532-9f34-7d06b5dbf188
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588916898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.588916898
Directory	/workspace/49.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2618921124
Short name	T77
Test name
Test status
Simulation time	20927447 ps
CPU time	0.69 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	197256 kb
Host	smart-ec7986f0-bc71-465c-8a97-327c9c4abbda
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618921124 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2618921124
Directory	/workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_csr_rw.2057315987
Short name	T148
Test name
Test status
Simulation time	61016464 ps
CPU time	0.62 seconds
Started	Jan 10 12:55:17 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	195564 kb
Host	smart-f575814b-561d-47ca-b4ba-ceade6147ff5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057315987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.2057315987
Directory	/workspace/5.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_intr_test.757357546
Short name	T127
Test name
Test status
Simulation time	12186962 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:21 PM PST 24
Peak memory	185216 kb
Host	smart-031fe22f-1d5e-41bd-923a-979f919c4a57
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757357546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.757357546
Directory	/workspace/5.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.449824463
Short name	T26
Test name
Test status
Simulation time	65674454 ps
CPU time	0.67 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	195688 kb
Host	smart-f7819a1b-23ae-4b40-8a67-ae6b18dbf3ac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449824463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_ outstanding.449824463
Directory	/workspace/5.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_errors.2617376972
Short name	T139
Test name
Test status
Simulation time	243939254 ps
CPU time	1.5 seconds
Started	Jan 10 12:55:17 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	200016 kb
Host	smart-bac2b549-945f-4ac2-b6c7-4cf7151bd591
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617376972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2617376972
Directory	/workspace/5.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.898829191
Short name	T128
Test name
Test status
Simulation time	42705839 ps
CPU time	0.98 seconds
Started	Jan 10 12:55:17 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	198844 kb
Host	smart-0ac72814-1ebf-4e1b-86f4-11c64d1c51a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898829191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.898829191
Directory	/workspace/5.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1409647023
Short name	T100
Test name
Test status
Simulation time	76480759 ps
CPU time	0.99 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	199860 kb
Host	smart-4dc69835-0792-4451-bece-32020c364b7d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409647023 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1409647023
Directory	/workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_csr_rw.2525313911
Short name	T35
Test name
Test status
Simulation time	13040908 ps
CPU time	0.6 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	195480 kb
Host	smart-bda5b003-3e6f-4a52-83ec-eb3b786b6337
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525313911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2525313911
Directory	/workspace/6.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_intr_test.3452946497
Short name	T76
Test name
Test status
Simulation time	22787828 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:24 PM PST 24
Peak memory	194428 kb
Host	smart-ce52a18a-fcbf-4790-bf70-0fb80eab9964
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452946497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3452946497
Directory	/workspace/6.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1863603426
Short name	T162
Test name
Test status
Simulation time	103653000 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:17 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	195820 kb
Host	smart-44202d56-639b-40eb-8aea-e61563c18fda
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863603426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr _outstanding.1863603426
Directory	/workspace/6.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.2167634503
Short name	T2
Test name
Test status
Simulation time	47561157 ps
CPU time	0.9 seconds
Started	Jan 10 12:55:14 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	198900 kb
Host	smart-1c26351b-558c-4250-a826-5b7d9de7556b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167634503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.2167634503
Directory	/workspace/6.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.194884287
Short name	T152
Test name
Test status
Simulation time	29504928 ps
CPU time	0.66 seconds
Started	Jan 10 12:57:05 PM PST 24
Finished	Jan 10 12:58:18 PM PST 24
Peak memory	196616 kb
Host	smart-195cd700-f89b-4890-87eb-a241cbeb81e7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194884287 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.194884287
Directory	/workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_csr_rw.243273218
Short name	T48
Test name
Test status
Simulation time	73849238 ps
CPU time	0.56 seconds
Started	Jan 10 12:55:20 PM PST 24
Finished	Jan 10 12:56:28 PM PST 24
Peak memory	195512 kb
Host	smart-59386df5-ea74-4750-99a6-0f740c324650
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243273218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.243273218
Directory	/workspace/7.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_intr_test.1531935327
Short name	T70
Test name
Test status
Simulation time	36796323 ps
CPU time	0.54 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:24 PM PST 24
Peak memory	194328 kb
Host	smart-f7ee3a87-2a00-49c8-be93-e9caff14175b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531935327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1531935327
Directory	/workspace/7.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1765297493
Short name	T110
Test name
Test status
Simulation time	104741398 ps
CPU time	0.7 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	195120 kb
Host	smart-4f7f0051-59dd-4d64-867a-4cf6e4cb26ae
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765297493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.1765297493
Directory	/workspace/7.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_errors.2601438368
Short name	T16
Test name
Test status
Simulation time	41231901 ps
CPU time	2.02 seconds
Started	Jan 10 12:55:16 PM PST 24
Finished	Jan 10 12:56:25 PM PST 24
Peak memory	200084 kb
Host	smart-f778579c-c158-4915-8282-24dc6ca9e374
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601438368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2601438368
Directory	/workspace/7.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2488680723
Short name	T17
Test name
Test status
Simulation time	237917184 ps
CPU time	0.99 seconds
Started	Jan 10 12:55:15 PM PST 24
Finished	Jan 10 12:56:22 PM PST 24
Peak memory	198664 kb
Host	smart-8594ee5d-aee3-4bc5-a18b-9bc7bab41d8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488680723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2488680723
Directory	/workspace/7.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_csr_rw.1672343454
Short name	T67
Test name
Test status
Simulation time	22492037 ps
CPU time	0.63 seconds
Started	Jan 10 12:55:20 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	195536 kb
Host	smart-ba9c2561-f9d2-4842-8784-2d4d3f26a346
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672343454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1672343454
Directory	/workspace/8.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_intr_test.4203834259
Short name	T41
Test name
Test status
Simulation time	53337350 ps
CPU time	0.55 seconds
Started	Jan 10 12:57:06 PM PST 24
Finished	Jan 10 12:58:18 PM PST 24
Peak memory	194084 kb
Host	smart-24eb0ed8-fc45-44b9-a4ca-e9e66be70111
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203834259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.4203834259
Directory	/workspace/8.uart_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.278621282
Short name	T73
Test name
Test status
Simulation time	151502865 ps
CPU time	0.72 seconds
Started	Jan 10 12:55:31 PM PST 24
Finished	Jan 10 12:56:38 PM PST 24
Peak memory	197016 kb
Host	smart-dcf0e884-ad9c-4d96-9c2c-8777fa697856
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278621282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr_ outstanding.278621282
Directory	/workspace/8.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_errors.4082265869
Short name	T99
Test name
Test status
Simulation time	412293701 ps
CPU time	2.03 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:27 PM PST 24
Peak memory	200080 kb
Host	smart-a6872366-2f7b-40de-a8b1-315da8ec8104
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082265869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.4082265869
Directory	/workspace/8.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.2031241013
Short name	T157
Test name
Test status
Simulation time	217042393 ps
CPU time	0.96 seconds
Started	Jan 10 12:55:18 PM PST 24
Finished	Jan 10 12:56:26 PM PST 24
Peak memory	198952 kb
Host	smart-d0c7c0be-68c2-47cf-b254-2685e75a25ae
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031241013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.2031241013
Directory	/workspace/8.uart_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3763571822
Short name	T42
Test name
Test status
Simulation time	99343598 ps
CPU time	0.91 seconds
Started	Jan 10 12:55:24 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	199344 kb
Host	smart-83cbbdb9-6f5f-49c6-9f5b-e20d946097c6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763571822 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3763571822
Directory	/workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_csr_rw.3830872272
Short name	T82
Test name
Test status
Simulation time	40758242 ps
CPU time	0.57 seconds
Started	Jan 10 12:55:28 PM PST 24
Finished	Jan 10 12:56:36 PM PST 24
Peak memory	195460 kb
Host	smart-51e68eb9-156a-415e-8b15-85c803a5a069
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830872272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3830872272
Directory	/workspace/9.uart_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2775247586
Short name	T97
Test name
Test status
Simulation time	52196118 ps
CPU time	0.69 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:32 PM PST 24
Peak memory	196912 kb
Host	smart-a4a41a10-409b-4235-a624-df549830fa5d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775247586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.2775247586
Directory	/workspace/9.uart_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_errors.4042070062
Short name	T164
Test name
Test status
Simulation time	335147935 ps
CPU time	1.73 seconds
Started	Jan 10 12:55:23 PM PST 24
Finished	Jan 10 12:56:33 PM PST 24
Peak memory	199992 kb
Host	smart-00adf907-0958-4b18-b057-2ec74ad0012b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042070062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.4042070062
Directory	/workspace/9.uart_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1705374303
Short name	T58
Test name
Test status
Simulation time	42118731 ps
CPU time	0.91 seconds
Started	Jan 10 12:55:28 PM PST 24
Finished	Jan 10 12:56:35 PM PST 24
Peak memory	199124 kb
Host	smart-c497faf1-45de-4a23-b79e-6f95ec64c294
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705374303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1705374303
Directory	/workspace/9.uart_tl_intg_err/latest