Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
14.29	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	10	3	23.08
Crosses	22	20	2	9.09

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	10	1	9.09	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	20	2	9.09	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

475

1

T1

21

T2

11

T3

1

auto[UartRx]

475

1

T1

21

T2

11

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	10	1	9.09

User Defined Bins for cp_rst_pos

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[1]	0	1	1
values[2]	0	1	1
values[3]	0	1	1
values[4]	0	1	1
values[5]	0	1	1
values[6]	0	1	1
values[7]	0	1	1
values[8]	0	1	1
values[9]	0	1	1
values[10]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0]

950

1

T1

42

T2

22

T3

2

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	20	2	9.09	20

Automatically Generated Cross Bins for uart_reset_cg_cc

Element holes

cp_dir	cp_rst_pos	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7] , values[8] , values[9] , values[10]]	--	--	20

Covered bins

cp_dir

cp_rst_pos

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

values[0]

475

1

T1

21

T2

11

T3

1

auto[UartRx]

values[0]

475

1

T1

21

T2

11

T3

1