SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
0.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 12 | 12 | 0 | 0.00 |
Crosses | 34 | 34 | 0 | 0.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_baud_rate | 7 | 7 | 0 | 0.00 | 100 | 1 | 1 | 0 | |
cp_clk_freq | 5 | 5 | 0 | 0.00 | 100 | 1 | 1 | 0 |
CROSS | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | PRINT MISSING | COMMENT |
baud_rate_w_core_clk_cg_cc | 34 | 34 | 0 | 0.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 7 | 7 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[BaudRate9600] | 0 | 1 | 1 | |
auto[BaudRate115200] | 0 | 1 | 1 | |
auto[BaudRate230400] | 0 | 1 | 1 | |
auto[BaudRate128Kbps] | 0 | 1 | 1 | |
auto[BaudRate256Kbps] | 0 | 1 | 1 | |
auto[BaudRate1Mbps] | 0 | 1 | 1 | |
auto[BaudRate1p5Mbps] | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 5 | 5 | 0 | 0.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
freqs[24] | 0 | 1 | 1 | |
freqs[25] | 0 | 1 | 1 | |
freqs[48] | 0 | 1 | 1 | |
freqs[50] | 0 | 1 | 1 | |
freqs[100] | 0 | 1 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL | 34 | 34 | 0 | 0.00 | 34 |
Automatically Generated Cross Bins | 34 | 34 | 0 | 0.00 | 34 |
User Defined Cross Bins | 0 | 0 | 0 |
cp_baud_rate | cp_clk_freq | COUNT | AT LEAST | NUMBER | STATUS |
[auto[BaudRate9600] , auto[BaudRate115200] , auto[BaudRate230400] , auto[BaudRate128Kbps] , auto[BaudRate256Kbps] , auto[BaudRate1Mbps]] | * | -- | -- | 30 |
cp_baud_rate | cp_clk_freq | COUNT | AT LEAST | NUMBER | STATUS |
[auto[BaudRate1p5Mbps]] | [freqs[25] , freqs[48] , freqs[50] , freqs[100]] | -- | -- | 4 |
NAME | COUNT | STATUS |
unsupported | 0 | Excluded |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |