Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	336	1			T3	8		T5	5		T6	1
all_pins[1]	336	1			T3	8		T5	5		T6	1
all_pins[2]	336	1			T3	8		T5	5		T6	1
all_pins[3]	336	1			T3	8		T5	5		T6	1
all_pins[4]	336	1			T3	8		T5	5		T6	1
all_pins[5]	336	1			T3	8		T5	5		T6	1
all_pins[6]	336	1			T3	8		T5	5		T6	1
all_pins[7]	336	1			T3	8		T5	5		T6	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2205	1			T3	52		T5	38		T6	8
values[0x1]	483	1			T3	12		T5	2		T9	10
transitions[0x0=>0x1]	359	1			T3	12		T5	2		T9	6
transitions[0x1=>0x0]	369	1			T3	12		T5	2		T9	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	277	1			T3	8		T5	5		T6	1
all_pins[0]	values[0x1]	59	1			T8	1		T10	1		T32	2
all_pins[0]	transitions[0x0=>0x1]	42	1			T8	1		T32	1		T41	2
all_pins[0]	transitions[0x1=>0x0]	49	1			T3	4		T5	2		T9	3
all_pins[1]	values[0x0]	270	1			T3	4		T5	3		T6	1
all_pins[1]	values[0x1]	66	1			T3	4		T5	2		T9	3
all_pins[1]	transitions[0x0=>0x1]	49	1			T3	4		T5	2		T9	1
all_pins[1]	transitions[0x1=>0x0]	42	1			T3	2		T8	3		T24	1
all_pins[2]	values[0x0]	277	1			T3	6		T5	5		T6	1
all_pins[2]	values[0x1]	59	1			T3	2		T9	2		T8	3
all_pins[2]	transitions[0x0=>0x1]	42	1			T3	2		T8	3		T24	1
all_pins[2]	transitions[0x1=>0x0]	51	1			T3	2		T9	1		T24	1
all_pins[3]	values[0x0]	268	1			T3	6		T5	5		T6	1
all_pins[3]	values[0x1]	68	1			T3	2		T9	3		T24	1
all_pins[3]	transitions[0x0=>0x1]	60	1			T3	2		T9	3		T24	1
all_pins[3]	transitions[0x1=>0x0]	38	1			T3	2		T8	2		T24	2
all_pins[4]	values[0x0]	290	1			T3	6		T5	5		T6	1
all_pins[4]	values[0x1]	46	1			T3	2		T8	2		T24	2
all_pins[4]	transitions[0x0=>0x1]	32	1			T3	2		T8	1		T24	2
all_pins[4]	transitions[0x1=>0x0]	57	1			T9	1		T8	1		T24	1
all_pins[5]	values[0x0]	265	1			T3	8		T5	5		T6	1
all_pins[5]	values[0x1]	71	1			T9	1		T8	2		T24	1
all_pins[5]	transitions[0x0=>0x1]	51	1			T9	1		T8	2		T24	1
all_pins[5]	transitions[0x1=>0x0]	32	1			T3	2		T10	2		T41	1
all_pins[6]	values[0x0]	284	1			T3	6		T5	5		T6	1
all_pins[6]	values[0x1]	52	1			T3	2		T10	2		T32	1
all_pins[6]	transitions[0x0=>0x1]	41	1			T3	2		T10	2		T41	4
all_pins[6]	transitions[0x1=>0x0]	51	1			T9	1		T8	1		T24	1
all_pins[7]	values[0x0]	274	1			T3	8		T5	5		T6	1
all_pins[7]	values[0x1]	62	1			T9	1		T8	1		T24	1
all_pins[7]	transitions[0x0=>0x1]	42	1			T9	1		T8	1		T24	1
all_pins[7]	transitions[0x1=>0x0]	49	1			T8	1		T10	1		T32	2