Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	0	48	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	0	48	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T3	7		T5	4		T9	4
all_values[1]	266	1			T3	7		T5	4		T9	4
all_values[2]	266	1			T3	7		T5	4		T9	4
all_values[3]	266	1			T3	7		T5	4		T9	4
all_values[4]	266	1			T3	7		T5	4		T9	4
all_values[5]	266	1			T3	7		T5	4		T9	4
all_values[6]	266	1			T3	7		T5	4		T9	4
all_values[7]	266	1			T3	7		T5	4		T9	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1171

1

T3

21

T5

22

T9

15

auto[1]

957

1

T3

35

T5

10

T9

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

828

1

T3

26

T5

14

T9

13

auto[1]

1300

1

T3

30

T5

18

T9

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1274

1

T3

34

T5

20

T9

21

auto[1]

854

1

T3

22

T5

12

T9

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	52	1			T5	1		T9	3		T8	3
all_values[0]	auto[0]	auto[0]	auto[1]	27	1			T3	1		T5	1		T44	2
all_values[0]	auto[0]	auto[1]	auto[0]	50	1			T9	1		T8	2		T24	3
all_values[0]	auto[0]	auto[1]	auto[1]	20	1			T3	1		T8	1		T41	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1			T3	4		T5	1		T32	1
all_values[0]	auto[1]	auto[1]	auto[1]	52	1			T3	1		T5	1		T8	1
all_values[1]	auto[0]	auto[0]	auto[0]	59	1			T3	1		T8	3		T24	1
all_values[1]	auto[0]	auto[0]	auto[1]	24	1			T32	3		T50	1		T63	1
all_values[1]	auto[0]	auto[1]	auto[0]	40	1			T9	1		T8	4		T24	1
all_values[1]	auto[0]	auto[1]	auto[1]	31	1			T3	2		T5	1		T9	1
all_values[1]	auto[1]	auto[0]	auto[1]	51	1			T3	3		T5	2		T24	1
all_values[1]	auto[1]	auto[1]	auto[1]	61	1			T3	1		T5	1		T9	2
all_values[2]	auto[0]	auto[0]	auto[0]	65	1			T3	3		T5	4		T8	1
all_values[2]	auto[0]	auto[0]	auto[1]	20	1			T10	1		T32	1		T43	1
all_values[2]	auto[0]	auto[1]	auto[0]	42	1			T3	1		T9	1		T10	1
all_values[2]	auto[0]	auto[1]	auto[1]	29	1			T9	1		T41	2		T43	1
all_values[2]	auto[1]	auto[0]	auto[1]	63	1			T9	1		T8	1		T24	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1			T3	3		T9	1		T8	5
all_values[3]	auto[0]	auto[0]	auto[0]	49	1			T5	1		T8	1		T24	1
all_values[3]	auto[0]	auto[0]	auto[1]	33	1			T5	1		T9	1		T41	1
all_values[3]	auto[0]	auto[1]	auto[0]	42	1			T3	2		T8	5		T24	2
all_values[3]	auto[0]	auto[1]	auto[1]	38	1			T3	2		T9	2		T10	1
all_values[3]	auto[1]	auto[0]	auto[1]	65	1			T3	2		T5	1		T9	1
all_values[3]	auto[1]	auto[1]	auto[1]	39	1			T3	1		T5	1		T8	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1			T5	1		T9	2		T8	1
all_values[4]	auto[0]	auto[0]	auto[1]	29	1			T5	1		T8	1		T24	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1			T3	3		T5	1		T8	2
all_values[4]	auto[0]	auto[1]	auto[1]	23	1			T3	1		T24	1		T41	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1			T3	1		T9	2		T8	1
all_values[4]	auto[1]	auto[1]	auto[1]	34	1			T3	2		T5	1		T8	2
all_values[5]	auto[0]	auto[0]	auto[0]	52	1			T3	2		T5	1		T8	1
all_values[5]	auto[0]	auto[0]	auto[1]	22	1			T5	1		T9	1		T8	1
all_values[5]	auto[0]	auto[1]	auto[0]	48	1			T3	4		T8	1		T24	1
all_values[5]	auto[0]	auto[1]	auto[1]	31	1			T24	1		T32	1		T41	1
all_values[5]	auto[1]	auto[0]	auto[1]	66	1			T9	1		T8	2		T10	1
all_values[5]	auto[1]	auto[1]	auto[1]	47	1			T3	1		T5	2		T9	2
all_values[6]	auto[0]	auto[0]	auto[0]	66	1			T3	4		T5	1		T9	2
all_values[6]	auto[0]	auto[0]	auto[1]	30	1			T5	1		T24	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	38	1			T5	1		T9	2		T8	2
all_values[6]	auto[0]	auto[1]	auto[1]	26	1			T3	1		T10	2		T41	2
all_values[6]	auto[1]	auto[0]	auto[1]	65	1			T5	1		T8	1		T24	1
all_values[6]	auto[1]	auto[1]	auto[1]	41	1			T3	2		T8	1		T10	1
all_values[7]	auto[0]	auto[0]	auto[0]	54	1			T5	2		T8	1		T10	2
all_values[7]	auto[0]	auto[0]	auto[1]	31	1			T9	1		T8	4		T32	1
all_values[7]	auto[0]	auto[1]	auto[0]	56	1			T3	6		T5	1		T9	1
all_values[7]	auto[0]	auto[1]	auto[1]	32	1			T9	1		T24	1		T32	1
all_values[7]	auto[1]	auto[0]	auto[1]	54	1			T5	1		T8	1		T24	1
all_values[7]	auto[1]	auto[1]	auto[1]	39	1			T3	1		T9	1		T8	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal