Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

22887

1

T1

85

T2

112

T3

172

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19877	1			T1	238		T2	52		T3	111
values[0x0]	9555	1			T1	57		T2	32		T3	63
values[0x1]	10119	1			T1	45		T2	29		T3	61

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

27568

1

T1

181

T2

112

T3

188

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	118	1			T1	13		T3	1		T4	1
valid_sources[0x01]	107	1			T3	1		T4	1		T5	6
valid_sources[0x02]	81	1			T1	2		T3	1		T5	5
valid_sources[0x03]	119	1			T1	1		T4	4		T13	1
valid_sources[0x04]	240	1			T1	2		T4	1		T12	128
valid_sources[0x05]	161	1			T2	1		T4	6		T5	1
valid_sources[0x06]	147	1			T1	1		T2	1		T3	2
valid_sources[0x07]	108	1			T4	3		T5	1		T24	2
valid_sources[0x08]	124	1			T3	2		T4	5		T5	4
valid_sources[0x09]	134	1			T2	2		T4	3		T5	2
valid_sources[0x0a]	124	1			T4	1		T15	1		T23	1
valid_sources[0x0b]	199	1			T2	2		T3	1		T5	2
valid_sources[0x0c]	124	1			T1	3		T5	5		T14	1
valid_sources[0x0d]	96	1			T2	1		T3	5		T14	1
valid_sources[0x0e]	167	1			T2	1		T5	2		T14	2
valid_sources[0x0f]	349	1			T1	2		T4	1		T14	8
valid_sources[0x10]	210	1			T1	2		T2	1		T4	1
valid_sources[0x11]	236	1			T4	2		T5	1		T12	128
valid_sources[0x12]	132	1			T1	2		T2	1		T3	1
valid_sources[0x13]	108	1			T5	1		T15	1		T23	2
valid_sources[0x14]	214	1			T5	2		T15	1		T16	17
valid_sources[0x15]	106	1			T1	1		T3	1		T4	1
valid_sources[0x16]	180	1			T14	1		T16	12		T57	2
valid_sources[0x17]	111	1			T3	3		T5	1		T14	4
valid_sources[0x18]	145	1			T4	1		T5	6		T14	1
valid_sources[0x19]	99	1			T2	3		T24	1		T56	2
valid_sources[0x1a]	145	1			T1	5		T3	1		T13	1
valid_sources[0x1b]	126	1			T1	1		T2	1		T3	1
valid_sources[0x1c]	177	1			T3	6		T13	1		T5	2
valid_sources[0x1d]	237	1			T3	3		T4	2		T5	1
valid_sources[0x1e]	173	1			T1	4		T4	4		T14	3
valid_sources[0x1f]	110	1			T2	2		T7	1		T24	2
valid_sources[0x20]	95	1			T1	1		T2	1		T5	1
valid_sources[0x21]	180	1			T3	1		T4	2		T57	1
valid_sources[0x22]	111	1			T24	3		T17	6		T78	3
valid_sources[0x23]	108	1			T1	3		T4	1		T5	2
valid_sources[0x24]	170	1			T13	1		T24	1		T31	15
valid_sources[0x25]	126	1			T1	6		T3	2		T4	2
valid_sources[0x26]	118	1			T1	1		T4	3		T14	4
valid_sources[0x27]	146	1			T1	3		T2	1		T4	1
valid_sources[0x28]	98	1			T1	3		T3	2		T4	1
valid_sources[0x29]	128	1			T3	5		T4	2		T24	1
valid_sources[0x2a]	227	1			T1	2		T3	3		T4	3
valid_sources[0x2b]	163	1			T4	2		T24	2		T16	1
valid_sources[0x2c]	129	1			T4	1		T24	1		T57	1
valid_sources[0x2d]	84	1			T3	3		T14	1		T7	1
valid_sources[0x2e]	102	1			T4	1		T14	2		T7	1
valid_sources[0x2f]	110	1			T1	3		T2	2		T56	1
valid_sources[0x30]	107	1			T1	2		T3	1		T14	1
valid_sources[0x31]	78	1			T3	1		T4	2		T5	2
valid_sources[0x32]	97	1			T1	2		T4	1		T57	1
valid_sources[0x33]	121	1			T5	5		T24	8		T57	1
valid_sources[0x34]	128	1			T1	2		T3	1		T4	1
valid_sources[0x35]	129	1			T5	2		T14	1		T24	5
valid_sources[0x36]	84	1			T4	2		T5	2		T24	6
valid_sources[0x37]	132	1			T2	1		T3	2		T5	2
valid_sources[0x38]	238	1			T1	1		T3	3		T5	2
valid_sources[0x39]	98	1			T1	2		T4	4		T13	1
valid_sources[0x3a]	200	1			T1	1		T5	2		T15	3
valid_sources[0x3b]	112	1			T4	1		T24	6		T16	5
valid_sources[0x3c]	101	1			T1	6		T5	2		T57	2
valid_sources[0x3d]	116	1			T1	1		T3	1		T7	1
valid_sources[0x3e]	101	1			T3	2		T4	2		T5	4
valid_sources[0x3f]	91	1			T1	5		T3	2		T4	2
valid_sources[0x40]	130	1			T2	1		T3	1		T4	1
valid_sources[0x41]	167	1			T3	2		T4	1		T5	5
valid_sources[0x42]	95	1			T2	1		T4	1		T14	2
valid_sources[0x43]	192	1			T4	2		T5	3		T24	3
valid_sources[0x44]	313	1			T2	1		T3	1		T5	7
valid_sources[0x45]	108	1			T2	2		T3	1		T4	1
valid_sources[0x46]	85	1			T2	1		T14	3		T57	1
valid_sources[0x47]	135	1			T4	3		T13	1		T14	1
valid_sources[0x48]	134	1			T1	5		T2	1		T4	3
valid_sources[0x49]	306	1			T3	1		T4	1		T5	4
valid_sources[0x4a]	291	1			T1	1		T5	3		T14	3
valid_sources[0x4b]	159	1			T4	4		T5	4		T7	1
valid_sources[0x4c]	180	1			T1	2		T2	1		T4	2
valid_sources[0x4d]	100	1			T5	4		T56	2		T17	2
valid_sources[0x4e]	246	1			T4	3		T5	7		T57	1
valid_sources[0x4f]	172	1			T1	4		T2	1		T4	2
valid_sources[0x50]	177	1			T1	2		T3	7		T14	1
valid_sources[0x51]	97	1			T1	1		T3	5		T4	2
valid_sources[0x52]	101	1			T2	1		T4	2		T5	2
valid_sources[0x53]	123	1			T1	1		T4	2		T5	2
valid_sources[0x54]	144	1			T3	1		T14	7		T57	3
valid_sources[0x55]	217	1			T1	2		T2	3		T4	1
valid_sources[0x56]	115	1			T14	1		T57	1		T17	1
valid_sources[0x57]	126	1			T2	2		T3	1		T4	1
valid_sources[0x58]	211	1			T2	1		T3	1		T4	1
valid_sources[0x59]	172	1			T1	5		T4	1		T7	1
valid_sources[0x5a]	144	1			T3	3		T4	1		T5	3
valid_sources[0x5b]	107	1			T2	1		T13	1		T5	5
valid_sources[0x5c]	220	1			T2	2		T15	1		T7	1
valid_sources[0x5d]	133	1			T1	1		T3	2		T4	1
valid_sources[0x5e]	89	1			T5	4		T23	2		T57	1
valid_sources[0x5f]	102	1			T5	6		T24	3		T11	1
valid_sources[0x60]	127	1			T1	3		T4	1		T15	1
valid_sources[0x61]	143	1			T1	6		T4	1		T5	1
valid_sources[0x62]	240	1			T1	3		T2	2		T3	1
valid_sources[0x63]	280	1			T2	1		T4	3		T5	4
valid_sources[0x64]	133	1			T4	1		T24	6		T16	3
valid_sources[0x65]	142	1			T3	2		T9	1		T56	5
valid_sources[0x66]	121	1			T2	1		T4	1		T24	5
valid_sources[0x67]	137	1			T1	2		T15	1		T24	2
valid_sources[0x68]	203	1			T1	9		T3	1		T4	3
valid_sources[0x69]	116	1			T4	1		T5	1		T15	2
valid_sources[0x6a]	102	1			T1	2		T4	1		T5	4
valid_sources[0x6b]	129	1			T3	1		T5	2		T15	1
valid_sources[0x6c]	165	1			T1	6		T2	1		T4	1
valid_sources[0x6d]	131	1			T1	7		T5	3		T14	1
valid_sources[0x6e]	243	1			T2	1		T3	4		T4	3
valid_sources[0x6f]	88	1			T1	1		T2	1		T4	1
valid_sources[0x70]	114	1			T1	1		T2	1		T3	1
valid_sources[0x71]	178	1			T1	1		T2	1		T3	1
valid_sources[0x72]	153	1			T5	6		T14	1		T24	2
valid_sources[0x73]	199	1			T1	2		T3	2		T4	6
valid_sources[0x74]	150	1			T2	1		T4	2		T5	5
valid_sources[0x75]	184	1			T4	1		T14	2		T15	1
valid_sources[0x76]	110	1			T3	4		T4	2		T5	7
valid_sources[0x77]	153	1			T1	1		T2	2		T3	1
valid_sources[0x78]	239	1			T2	1		T4	2		T5	7
valid_sources[0x79]	111	1			T1	1		T3	1		T4	3
valid_sources[0x7a]	155	1			T7	1		T57	2		T17	2
valid_sources[0x7b]	175	1			T2	1		T3	2		T4	3
valid_sources[0x7c]	124	1			T3	6		T4	1		T5	1
valid_sources[0x7d]	98	1			T2	1		T4	1		T5	1
valid_sources[0x7e]	135	1			T1	1		T3	1		T4	3
valid_sources[0x7f]	254	1			T4	3		T5	1		T12	128
valid_sources[0x80]	191	1			T3	3		T5	2		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

8706

1

T1

26

T2

51

T3

57

values[0x0]

all_enables

biggest_size

7438

1

T1

37

T2

32

T3

59

values[0x1]

all_enables

biggest_size

6743

1

T1

22

T2

29

T3

56